1 // SPDX-License-Identifier: GPL-2.0-only
3 * Motorola CPCAP PMIC RTC driver
5 * Based on cpcap-regulator.c from Motorola Linux kernel tree
6 * Copyright (C) 2009 Motorola, Inc.
8 * Rewritten for mainline kernel
11 * - use standard interrupt framework
12 * - use managed device resources
13 * - remove custom "secure clock daemon" helpers
15 * Copyright (C) 2017 Sebastian Reichel <sre@kernel.org>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/mod_devicetable.h>
20 #include <linux/init.h>
21 #include <linux/device.h>
22 #include <linux/platform_device.h>
23 #include <linux/rtc.h>
24 #include <linux/err.h>
25 #include <linux/regmap.h>
26 #include <linux/mfd/motorola-cpcap.h>
27 #include <linux/slab.h>
28 #include <linux/sched.h>
30 #define SECS_PER_DAY 86400
31 #define DAY_MASK 0x7FFF
32 #define TOD1_MASK 0x00FF
33 #define TOD2_MASK 0x01FF
42 struct regmap
*regmap
;
43 struct rtc_device
*rtc_dev
;
51 static void cpcap2rtc_time(struct rtc_time
*rtc
, struct cpcap_time
*cpcap
)
53 unsigned long int tod
;
54 unsigned long int time
;
56 tod
= (cpcap
->tod1
& TOD1_MASK
) | ((cpcap
->tod2
& TOD2_MASK
) << 8);
57 time
= tod
+ ((cpcap
->day
& DAY_MASK
) * SECS_PER_DAY
);
59 rtc_time64_to_tm(time
, rtc
);
62 static void rtc2cpcap_time(struct cpcap_time
*cpcap
, struct rtc_time
*rtc
)
66 time
= rtc_tm_to_time64(rtc
);
68 cpcap
->day
= time
/ SECS_PER_DAY
;
70 cpcap
->tod2
= (time
>> 8) & TOD2_MASK
;
71 cpcap
->tod1
= time
& TOD1_MASK
;
74 static int cpcap_rtc_alarm_irq_enable(struct device
*dev
, unsigned int enabled
)
76 struct cpcap_rtc
*rtc
= dev_get_drvdata(dev
);
78 if (rtc
->alarm_enabled
== enabled
)
82 enable_irq(rtc
->alarm_irq
);
84 disable_irq(rtc
->alarm_irq
);
86 rtc
->alarm_enabled
= !!enabled
;
91 static int cpcap_rtc_read_time(struct device
*dev
, struct rtc_time
*tm
)
93 struct cpcap_rtc
*rtc
;
94 struct cpcap_time cpcap_tm
;
98 rtc
= dev_get_drvdata(dev
);
100 ret
= regmap_read(rtc
->regmap
, CPCAP_REG_TOD2
, &temp_tod2
);
101 ret
|= regmap_read(rtc
->regmap
, CPCAP_REG_DAY
, &cpcap_tm
.day
);
102 ret
|= regmap_read(rtc
->regmap
, CPCAP_REG_TOD1
, &cpcap_tm
.tod1
);
103 ret
|= regmap_read(rtc
->regmap
, CPCAP_REG_TOD2
, &cpcap_tm
.tod2
);
105 if (temp_tod2
> cpcap_tm
.tod2
)
106 ret
|= regmap_read(rtc
->regmap
, CPCAP_REG_DAY
, &cpcap_tm
.day
);
109 dev_err(dev
, "Failed to read time\n");
113 cpcap2rtc_time(tm
, &cpcap_tm
);
118 static int cpcap_rtc_set_time(struct device
*dev
, struct rtc_time
*tm
)
120 struct cpcap_rtc
*rtc
;
121 struct cpcap_time cpcap_tm
;
124 rtc
= dev_get_drvdata(dev
);
126 rtc2cpcap_time(&cpcap_tm
, tm
);
128 if (rtc
->alarm_enabled
)
129 disable_irq(rtc
->alarm_irq
);
130 if (rtc
->update_enabled
)
131 disable_irq(rtc
->update_irq
);
133 if (rtc
->vendor
== CPCAP_VENDOR_ST
) {
134 /* The TOD1 and TOD2 registers MUST be written in this order
135 * for the change to properly set.
137 ret
|= regmap_update_bits(rtc
->regmap
, CPCAP_REG_TOD1
,
138 TOD1_MASK
, cpcap_tm
.tod1
);
139 ret
|= regmap_update_bits(rtc
->regmap
, CPCAP_REG_TOD2
,
140 TOD2_MASK
, cpcap_tm
.tod2
);
141 ret
|= regmap_update_bits(rtc
->regmap
, CPCAP_REG_DAY
,
142 DAY_MASK
, cpcap_tm
.day
);
144 /* Clearing the upper lower 8 bits of the TOD guarantees that
145 * the upper half of TOD (TOD2) will not increment for 0xFF RTC
146 * ticks (255 seconds). During this time we can safely write
147 * to DAY, TOD2, then TOD1 (in that order) and expect RTC to be
148 * synchronized to the exact time requested upon the final write
151 ret
|= regmap_update_bits(rtc
->regmap
, CPCAP_REG_TOD1
,
153 ret
|= regmap_update_bits(rtc
->regmap
, CPCAP_REG_DAY
,
154 DAY_MASK
, cpcap_tm
.day
);
155 ret
|= regmap_update_bits(rtc
->regmap
, CPCAP_REG_TOD2
,
156 TOD2_MASK
, cpcap_tm
.tod2
);
157 ret
|= regmap_update_bits(rtc
->regmap
, CPCAP_REG_TOD1
,
158 TOD1_MASK
, cpcap_tm
.tod1
);
161 if (rtc
->update_enabled
)
162 enable_irq(rtc
->update_irq
);
163 if (rtc
->alarm_enabled
)
164 enable_irq(rtc
->alarm_irq
);
169 static int cpcap_rtc_read_alarm(struct device
*dev
, struct rtc_wkalrm
*alrm
)
171 struct cpcap_rtc
*rtc
;
172 struct cpcap_time cpcap_tm
;
175 rtc
= dev_get_drvdata(dev
);
177 alrm
->enabled
= rtc
->alarm_enabled
;
179 ret
= regmap_read(rtc
->regmap
, CPCAP_REG_DAYA
, &cpcap_tm
.day
);
180 ret
|= regmap_read(rtc
->regmap
, CPCAP_REG_TODA2
, &cpcap_tm
.tod2
);
181 ret
|= regmap_read(rtc
->regmap
, CPCAP_REG_TODA1
, &cpcap_tm
.tod1
);
184 dev_err(dev
, "Failed to read time\n");
188 cpcap2rtc_time(&alrm
->time
, &cpcap_tm
);
189 return rtc_valid_tm(&alrm
->time
);
192 static int cpcap_rtc_set_alarm(struct device
*dev
, struct rtc_wkalrm
*alrm
)
194 struct cpcap_rtc
*rtc
;
195 struct cpcap_time cpcap_tm
;
198 rtc
= dev_get_drvdata(dev
);
200 rtc2cpcap_time(&cpcap_tm
, &alrm
->time
);
202 if (rtc
->alarm_enabled
)
203 disable_irq(rtc
->alarm_irq
);
205 ret
= regmap_update_bits(rtc
->regmap
, CPCAP_REG_DAYA
, DAY_MASK
,
207 ret
|= regmap_update_bits(rtc
->regmap
, CPCAP_REG_TODA2
, TOD2_MASK
,
209 ret
|= regmap_update_bits(rtc
->regmap
, CPCAP_REG_TODA1
, TOD1_MASK
,
213 enable_irq(rtc
->alarm_irq
);
214 rtc
->alarm_enabled
= true;
220 static const struct rtc_class_ops cpcap_rtc_ops
= {
221 .read_time
= cpcap_rtc_read_time
,
222 .set_time
= cpcap_rtc_set_time
,
223 .read_alarm
= cpcap_rtc_read_alarm
,
224 .set_alarm
= cpcap_rtc_set_alarm
,
225 .alarm_irq_enable
= cpcap_rtc_alarm_irq_enable
,
228 static irqreturn_t
cpcap_rtc_alarm_irq(int irq
, void *data
)
230 struct cpcap_rtc
*rtc
= data
;
232 rtc_update_irq(rtc
->rtc_dev
, 1, RTC_AF
| RTC_IRQF
);
236 static irqreturn_t
cpcap_rtc_update_irq(int irq
, void *data
)
238 struct cpcap_rtc
*rtc
= data
;
240 rtc_update_irq(rtc
->rtc_dev
, 1, RTC_UF
| RTC_IRQF
);
244 static int cpcap_rtc_probe(struct platform_device
*pdev
)
246 struct device
*dev
= &pdev
->dev
;
247 struct cpcap_rtc
*rtc
;
250 rtc
= devm_kzalloc(dev
, sizeof(*rtc
), GFP_KERNEL
);
254 rtc
->regmap
= dev_get_regmap(dev
->parent
, NULL
);
258 platform_set_drvdata(pdev
, rtc
);
259 rtc
->rtc_dev
= devm_rtc_allocate_device(dev
);
260 if (IS_ERR(rtc
->rtc_dev
))
261 return PTR_ERR(rtc
->rtc_dev
);
263 rtc
->rtc_dev
->ops
= &cpcap_rtc_ops
;
264 rtc
->rtc_dev
->range_max
= (timeu64_t
) (DAY_MASK
+ 1) * SECS_PER_DAY
- 1;
266 err
= cpcap_get_vendor(dev
, rtc
->regmap
, &rtc
->vendor
);
270 rtc
->alarm_irq
= platform_get_irq(pdev
, 0);
271 err
= devm_request_threaded_irq(dev
, rtc
->alarm_irq
, NULL
,
272 cpcap_rtc_alarm_irq
, IRQF_TRIGGER_NONE
,
275 dev_err(dev
, "Could not request alarm irq: %d\n", err
);
278 disable_irq(rtc
->alarm_irq
);
280 /* Stock Android uses the 1 Hz interrupt for "secure clock daemon",
281 * which is not supported by the mainline kernel. The mainline kernel
282 * does not use the irq at the moment, but we explicitly request and
283 * disable it, so that its masked and does not wake up the processor
286 rtc
->update_irq
= platform_get_irq(pdev
, 1);
287 err
= devm_request_threaded_irq(dev
, rtc
->update_irq
, NULL
,
288 cpcap_rtc_update_irq
, IRQF_TRIGGER_NONE
,
291 dev_err(dev
, "Could not request update irq: %d\n", err
);
294 disable_irq(rtc
->update_irq
);
296 err
= device_init_wakeup(dev
, 1);
298 dev_err(dev
, "wakeup initialization failed (%d)\n", err
);
299 /* ignore error and continue without wakeup support */
302 return rtc_register_device(rtc
->rtc_dev
);
305 static const struct of_device_id cpcap_rtc_of_match
[] = {
306 { .compatible
= "motorola,cpcap-rtc", },
309 MODULE_DEVICE_TABLE(of
, cpcap_rtc_of_match
);
311 static struct platform_driver cpcap_rtc_driver
= {
312 .probe
= cpcap_rtc_probe
,
315 .of_match_table
= cpcap_rtc_of_match
,
319 module_platform_driver(cpcap_rtc_driver
);
321 MODULE_ALIAS("platform:cpcap-rtc");
322 MODULE_DESCRIPTION("CPCAP RTC driver");
323 MODULE_AUTHOR("Sebastian Reichel <sre@kernel.org>");
324 MODULE_LICENSE("GPL");