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net: ipv6: RTF_PCPU should not be settable from userspace
[linux/fpc-iii.git] / include / video / omapdss.h
blobf001a356fd98f896ae617fe64db45745e1dc4736
1 /*
2 * Copyright (C) 2008 Nokia Corporation
3 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18 #ifndef __OMAP_OMAPDSS_H
19 #define __OMAP_OMAPDSS_H
20
21 #include <linux/list.h>
22 #include <linux/kobject.h>
23 #include <linux/device.h>
24 #include <linux/interrupt.h>
25
26 #include <video/videomode.h>
27
28 #define DISPC_IRQ_FRAMEDONE (1 << 0)
29 #define DISPC_IRQ_VSYNC (1 << 1)
30 #define DISPC_IRQ_EVSYNC_EVEN (1 << 2)
31 #define DISPC_IRQ_EVSYNC_ODD (1 << 3)
32 #define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4)
33 #define DISPC_IRQ_PROG_LINE_NUM (1 << 5)
34 #define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6)
35 #define DISPC_IRQ_GFX_END_WIN (1 << 7)
36 #define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8)
37 #define DISPC_IRQ_OCP_ERR (1 << 9)
38 #define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10)
39 #define DISPC_IRQ_VID1_END_WIN (1 << 11)
40 #define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12)
41 #define DISPC_IRQ_VID2_END_WIN (1 << 13)
42 #define DISPC_IRQ_SYNC_LOST (1 << 14)
43 #define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15)
44 #define DISPC_IRQ_WAKEUP (1 << 16)
45 #define DISPC_IRQ_SYNC_LOST2 (1 << 17)
46 #define DISPC_IRQ_VSYNC2 (1 << 18)
47 #define DISPC_IRQ_VID3_END_WIN (1 << 19)
48 #define DISPC_IRQ_VID3_FIFO_UNDERFLOW (1 << 20)
49 #define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21)
50 #define DISPC_IRQ_FRAMEDONE2 (1 << 22)
51 #define DISPC_IRQ_FRAMEDONEWB (1 << 23)
52 #define DISPC_IRQ_FRAMEDONETV (1 << 24)
53 #define DISPC_IRQ_WBBUFFEROVERFLOW (1 << 25)
54 #define DISPC_IRQ_SYNC_LOST3 (1 << 27)
55 #define DISPC_IRQ_VSYNC3 (1 << 28)
56 #define DISPC_IRQ_ACBIAS_COUNT_STAT3 (1 << 29)
57 #define DISPC_IRQ_FRAMEDONE3 (1 << 30)
58
59 struct omap_dss_device;
60 struct omap_overlay_manager;
61 struct dss_lcd_mgr_config;
62 struct snd_aes_iec958;
63 struct snd_cea_861_aud_if;
64 struct hdmi_avi_infoframe;
65
66 enum omap_display_type {
67 OMAP_DISPLAY_TYPE_NONE = 0,
68 OMAP_DISPLAY_TYPE_DPI = 1 << 0,
69 OMAP_DISPLAY_TYPE_DBI = 1 << 1,
70 OMAP_DISPLAY_TYPE_SDI = 1 << 2,
71 OMAP_DISPLAY_TYPE_DSI = 1 << 3,
72 OMAP_DISPLAY_TYPE_VENC = 1 << 4,
73 OMAP_DISPLAY_TYPE_HDMI = 1 << 5,
74 OMAP_DISPLAY_TYPE_DVI = 1 << 6,
75 };
76
77 enum omap_plane {
78 OMAP_DSS_GFX = 0,
79 OMAP_DSS_VIDEO1 = 1,
80 OMAP_DSS_VIDEO2 = 2,
81 OMAP_DSS_VIDEO3 = 3,
82 OMAP_DSS_WB = 4,
83 };
84
85 enum omap_channel {
86 OMAP_DSS_CHANNEL_LCD = 0,
87 OMAP_DSS_CHANNEL_DIGIT = 1,
88 OMAP_DSS_CHANNEL_LCD2 = 2,
89 OMAP_DSS_CHANNEL_LCD3 = 3,
90 };
91
92 enum omap_color_mode {
93 OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */
94 OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */
95 OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */
96 OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */
97 OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */
98 OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */
99 OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */
100 OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */
101 OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */
102 OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */
103 OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */
104 OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */
105 OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */
106 OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */
107 OMAP_DSS_COLOR_NV12 = 1 << 14, /* NV12 format: YUV 4:2:0 */
108 OMAP_DSS_COLOR_RGBA16 = 1 << 15, /* RGBA16 - 4444 */
109 OMAP_DSS_COLOR_RGBX16 = 1 << 16, /* RGBx16 - 4444 */
110 OMAP_DSS_COLOR_ARGB16_1555 = 1 << 17, /* ARGB16 - 1555 */
111 OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, /* xRGB16 - 1555 */
112 };
113
114 enum omap_dss_load_mode {
115 OMAP_DSS_LOAD_CLUT_AND_FRAME = 0,
116 OMAP_DSS_LOAD_CLUT_ONLY = 1,
117 OMAP_DSS_LOAD_FRAME_ONLY = 2,
118 OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3,
119 };
120
121 enum omap_dss_trans_key_type {
122 OMAP_DSS_COLOR_KEY_GFX_DST = 0,
123 OMAP_DSS_COLOR_KEY_VID_SRC = 1,
124 };
125
126 enum omap_rfbi_te_mode {
127 OMAP_DSS_RFBI_TE_MODE_1 = 1,
128 OMAP_DSS_RFBI_TE_MODE_2 = 2,
129 };
130
131 enum omap_dss_signal_level {
132 OMAPDSS_SIG_ACTIVE_LOW,
133 OMAPDSS_SIG_ACTIVE_HIGH,
134 };
135
136 enum omap_dss_signal_edge {
137 OMAPDSS_DRIVE_SIG_FALLING_EDGE,
138 OMAPDSS_DRIVE_SIG_RISING_EDGE,
139 };
140
141 enum omap_dss_venc_type {
142 OMAP_DSS_VENC_TYPE_COMPOSITE,
143 OMAP_DSS_VENC_TYPE_SVIDEO,
144 };
145
146 enum omap_dss_dsi_pixel_format {
147 OMAP_DSS_DSI_FMT_RGB888,
148 OMAP_DSS_DSI_FMT_RGB666,
149 OMAP_DSS_DSI_FMT_RGB666_PACKED,
150 OMAP_DSS_DSI_FMT_RGB565,
151 };
152
153 enum omap_dss_dsi_mode {
154 OMAP_DSS_DSI_CMD_MODE = 0,
155 OMAP_DSS_DSI_VIDEO_MODE,
156 };
157
158 enum omap_display_caps {
159 OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0,
160 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1,
161 };
162
163 enum omap_dss_display_state {
164 OMAP_DSS_DISPLAY_DISABLED = 0,
165 OMAP_DSS_DISPLAY_ACTIVE,
166 };
167
168 struct omap_dss_audio {
169 struct snd_aes_iec958 *iec;
170 struct snd_cea_861_aud_if *cea;
171 };
172
173 enum omap_dss_rotation_type {
174 OMAP_DSS_ROT_DMA = 1 << 0,
175 OMAP_DSS_ROT_VRFB = 1 << 1,
176 OMAP_DSS_ROT_TILER = 1 << 2,
177 };
178
179 /* clockwise rotation angle */
180 enum omap_dss_rotation_angle {
181 OMAP_DSS_ROT_0 = 0,
182 OMAP_DSS_ROT_90 = 1,
183 OMAP_DSS_ROT_180 = 2,
184 OMAP_DSS_ROT_270 = 3,
185 };
186
187 enum omap_overlay_caps {
188 OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
189 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1,
190 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2,
191 OMAP_DSS_OVL_CAP_ZORDER = 1 << 3,
192 OMAP_DSS_OVL_CAP_POS = 1 << 4,
193 OMAP_DSS_OVL_CAP_REPLICATION = 1 << 5,
194 };
195
196 enum omap_overlay_manager_caps {
197 OMAP_DSS_DUMMY_VALUE, /* add a dummy value to prevent compiler error */
198 };
199
200 enum omap_dss_clk_source {
201 OMAP_DSS_CLK_SRC_FCK = 0, /* OMAP2/3: DSS1_ALWON_FCLK
202 * OMAP4: DSS_FCLK */
203 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* OMAP3: DSI1_PLL_FCLK
204 * OMAP4: PLL1_CLK1 */
205 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* OMAP3: DSI2_PLL_FCLK
206 * OMAP4: PLL1_CLK2 */
207 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC, /* OMAP4: PLL2_CLK1 */
208 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI, /* OMAP4: PLL2_CLK2 */
209 };
210
211 enum omap_hdmi_flags {
212 OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP = 1 << 0,
213 };
214
215 enum omap_dss_output_id {
216 OMAP_DSS_OUTPUT_DPI = 1 << 0,
217 OMAP_DSS_OUTPUT_DBI = 1 << 1,
218 OMAP_DSS_OUTPUT_SDI = 1 << 2,
219 OMAP_DSS_OUTPUT_DSI1 = 1 << 3,
220 OMAP_DSS_OUTPUT_DSI2 = 1 << 4,
221 OMAP_DSS_OUTPUT_VENC = 1 << 5,
222 OMAP_DSS_OUTPUT_HDMI = 1 << 6,
223 };
224
225 /* RFBI */
226
227 struct rfbi_timings {
228 int cs_on_time;
229 int cs_off_time;
230 int we_on_time;
231 int we_off_time;
232 int re_on_time;
233 int re_off_time;
234 int we_cycle_time;
235 int re_cycle_time;
236 int cs_pulse_width;
237 int access_time;
238
239 int clk_div;
240
241 u32 tim[5]; /* set by rfbi_convert_timings() */
242
243 int converted;
244 };
245
246 /* DSI */
247
248 enum omap_dss_dsi_trans_mode {
249 /* Sync Pulses: both sync start and end packets sent */
250 OMAP_DSS_DSI_PULSE_MODE,
251 /* Sync Events: only sync start packets sent */
252 OMAP_DSS_DSI_EVENT_MODE,
253 /* Burst: only sync start packets sent, pixels are time compressed */
254 OMAP_DSS_DSI_BURST_MODE,
255 };
256
257 struct omap_dss_dsi_videomode_timings {
258 unsigned long hsclk;
259
260 unsigned ndl;
261 unsigned bitspp;
262
263 /* pixels */
264 u16 hact;
265 /* lines */
266 u16 vact;
267
268 /* DSI video mode blanking data */
269 /* Unit: byte clock cycles */
270 u16 hss;
271 u16 hsa;
272 u16 hse;
273 u16 hfp;
274 u16 hbp;
275 /* Unit: line clocks */
276 u16 vsa;
277 u16 vfp;
278 u16 vbp;
279
280 /* DSI blanking modes */
281 int blanking_mode;
282 int hsa_blanking_mode;
283 int hbp_blanking_mode;
284 int hfp_blanking_mode;
285
286 enum omap_dss_dsi_trans_mode trans_mode;
287
288 bool ddr_clk_always_on;
289 int window_sync;
290 };
291
292 struct omap_dss_dsi_config {
293 enum omap_dss_dsi_mode mode;
294 enum omap_dss_dsi_pixel_format pixel_format;
295 const struct omap_video_timings *timings;
296
297 unsigned long hs_clk_min, hs_clk_max;
298 unsigned long lp_clk_min, lp_clk_max;
299
300 bool ddr_clk_always_on;
301 enum omap_dss_dsi_trans_mode trans_mode;
302 };
303
304 enum omapdss_version {
305 OMAPDSS_VER_UNKNOWN = 0,
306 OMAPDSS_VER_OMAP24xx,
307 OMAPDSS_VER_OMAP34xx_ES1, /* OMAP3430 ES1.0, 2.0 */
308 OMAPDSS_VER_OMAP34xx_ES3, /* OMAP3430 ES3.0+ */
309 OMAPDSS_VER_OMAP3630,
310 OMAPDSS_VER_AM35xx,
311 OMAPDSS_VER_OMAP4430_ES1, /* OMAP4430 ES1.0 */
312 OMAPDSS_VER_OMAP4430_ES2, /* OMAP4430 ES2.0, 2.1, 2.2 */
313 OMAPDSS_VER_OMAP4, /* All other OMAP4s */
314 OMAPDSS_VER_OMAP5,
315 OMAPDSS_VER_AM43xx,
316 OMAPDSS_VER_DRA7xx,
317 };
318
319 /* Board specific data */
320 struct omap_dss_board_info {
321 int num_devices;
322 struct omap_dss_device **devices;
323 struct omap_dss_device *default_device;
324 const char *default_display_name;
325 int (*dsi_enable_pads)(int dsi_id, unsigned lane_mask);
326 void (*dsi_disable_pads)(int dsi_id, unsigned lane_mask);
327 int (*set_min_bus_tput)(struct device *dev, unsigned long r);
328 enum omapdss_version version;
329 };
330
331 /* Init with the board info */
332 extern int omap_display_init(struct omap_dss_board_info *board_data);
333 /* HDMI mux init*/
334 extern int omap_hdmi_init(enum omap_hdmi_flags flags);
335
336 struct omap_video_timings {
337 /* Unit: pixels */
338 u16 x_res;
339 /* Unit: pixels */
340 u16 y_res;
341 /* Unit: Hz */
342 u32 pixelclock;
343 /* Unit: pixel clocks */
344 u16 hsw; /* Horizontal synchronization pulse width */
345 /* Unit: pixel clocks */
346 u16 hfp; /* Horizontal front porch */
347 /* Unit: pixel clocks */
348 u16 hbp; /* Horizontal back porch */
349 /* Unit: line clocks */
350 u16 vsw; /* Vertical synchronization pulse width */
351 /* Unit: line clocks */
352 u16 vfp; /* Vertical front porch */
353 /* Unit: line clocks */
354 u16 vbp; /* Vertical back porch */
355
356 /* Vsync logic level */
357 enum omap_dss_signal_level vsync_level;
358 /* Hsync logic level */
359 enum omap_dss_signal_level hsync_level;
360 /* Interlaced or Progressive timings */
361 bool interlace;
362 /* Pixel clock edge to drive LCD data */
363 enum omap_dss_signal_edge data_pclk_edge;
364 /* Data enable logic level */
365 enum omap_dss_signal_level de_level;
366 /* Pixel clock edges to drive HSYNC and VSYNC signals */
367 enum omap_dss_signal_edge sync_pclk_edge;
368 };
369
370 #ifdef CONFIG_OMAP2_DSS_VENC
371 /* Hardcoded timings for tv modes. Venc only uses these to
372 * identify the mode, and does not actually use the configs
373 * itself. However, the configs should be something that
374 * a normal monitor can also show */
375 extern const struct omap_video_timings omap_dss_pal_timings;
376 extern const struct omap_video_timings omap_dss_ntsc_timings;
377 #endif
378
379 struct omap_dss_cpr_coefs {
380 s16 rr, rg, rb;
381 s16 gr, gg, gb;
382 s16 br, bg, bb;
383 };
384
385 struct omap_overlay_info {
386 dma_addr_t paddr;
387 dma_addr_t p_uv_addr; /* for NV12 format */
388 u16 screen_width;
389 u16 width;
390 u16 height;
391 enum omap_color_mode color_mode;
392 u8 rotation;
393 enum omap_dss_rotation_type rotation_type;
394 bool mirror;
395
396 u16 pos_x;
397 u16 pos_y;
398 u16 out_width; /* if 0, out_width == width */
399 u16 out_height; /* if 0, out_height == height */
400 u8 global_alpha;
401 u8 pre_mult_alpha;
402 u8 zorder;
403 };
404
405 struct omap_overlay {
406 struct kobject kobj;
407 struct list_head list;
408
409 /* static fields */
410 const char *name;
411 enum omap_plane id;
412 enum omap_color_mode supported_modes;
413 enum omap_overlay_caps caps;
414
415 /* dynamic fields */
416 struct omap_overlay_manager *manager;
417
418 /*
419 * The following functions do not block:
420 *
421 * is_enabled
422 * set_overlay_info
423 * get_overlay_info
424 *
425 * The rest of the functions may block and cannot be called from
426 * interrupt context
427 */
428
429 int (*enable)(struct omap_overlay *ovl);
430 int (*disable)(struct omap_overlay *ovl);
431 bool (*is_enabled)(struct omap_overlay *ovl);
432
433 int (*set_manager)(struct omap_overlay *ovl,
434 struct omap_overlay_manager *mgr);
435 int (*unset_manager)(struct omap_overlay *ovl);
436
437 int (*set_overlay_info)(struct omap_overlay *ovl,
438 struct omap_overlay_info *info);
439 void (*get_overlay_info)(struct omap_overlay *ovl,
440 struct omap_overlay_info *info);
441
442 int (*wait_for_go)(struct omap_overlay *ovl);
443
444 struct omap_dss_device *(*get_device)(struct omap_overlay *ovl);
445 };
446
447 struct omap_overlay_manager_info {
448 u32 default_color;
449
450 enum omap_dss_trans_key_type trans_key_type;
451 u32 trans_key;
452 bool trans_enabled;
453
454 bool partial_alpha_enabled;
455
456 bool cpr_enable;
457 struct omap_dss_cpr_coefs cpr_coefs;
458 };
459
460 struct omap_overlay_manager {
461 struct kobject kobj;
462
463 /* static fields */
464 const char *name;
465 enum omap_channel id;
466 enum omap_overlay_manager_caps caps;
467 struct list_head overlays;
468 enum omap_display_type supported_displays;
469 enum omap_dss_output_id supported_outputs;
470
471 /* dynamic fields */
472 struct omap_dss_device *output;
473
474 /*
475 * The following functions do not block:
476 *
477 * set_manager_info
478 * get_manager_info
479 * apply
480 *
481 * The rest of the functions may block and cannot be called from
482 * interrupt context
483 */
484
485 int (*set_output)(struct omap_overlay_manager *mgr,
486 struct omap_dss_device *output);
487 int (*unset_output)(struct omap_overlay_manager *mgr);
488
489 int (*set_manager_info)(struct omap_overlay_manager *mgr,
490 struct omap_overlay_manager_info *info);
491 void (*get_manager_info)(struct omap_overlay_manager *mgr,
492 struct omap_overlay_manager_info *info);
493
494 int (*apply)(struct omap_overlay_manager *mgr);
495 int (*wait_for_go)(struct omap_overlay_manager *mgr);
496 int (*wait_for_vsync)(struct omap_overlay_manager *mgr);
497
498 struct omap_dss_device *(*get_device)(struct omap_overlay_manager *mgr);
499 };
500
501 /* 22 pins means 1 clk lane and 10 data lanes */
502 #define OMAP_DSS_MAX_DSI_PINS 22
503
504 struct omap_dsi_pin_config {
505 int num_pins;
506 /*
507 * pin numbers in the following order:
508 * clk+, clk-
509 * data1+, data1-
510 * data2+, data2-
511 * ...
512 */
513 int pins[OMAP_DSS_MAX_DSI_PINS];
514 };
515
516 struct omap_dss_writeback_info {
517 u32 paddr;
518 u32 p_uv_addr;
519 u16 buf_width;
520 u16 width;
521 u16 height;
522 enum omap_color_mode color_mode;
523 u8 rotation;
524 enum omap_dss_rotation_type rotation_type;
525 bool mirror;
526 u8 pre_mult_alpha;
527 };
528
529 struct omapdss_dpi_ops {
530 int (*connect)(struct omap_dss_device *dssdev,
531 struct omap_dss_device *dst);
532 void (*disconnect)(struct omap_dss_device *dssdev,
533 struct omap_dss_device *dst);
534
535 int (*enable)(struct omap_dss_device *dssdev);
536 void (*disable)(struct omap_dss_device *dssdev);
537
538 int (*check_timings)(struct omap_dss_device *dssdev,
539 struct omap_video_timings *timings);
540 void (*set_timings)(struct omap_dss_device *dssdev,
541 struct omap_video_timings *timings);
542 void (*get_timings)(struct omap_dss_device *dssdev,
543 struct omap_video_timings *timings);
544
545 void (*set_data_lines)(struct omap_dss_device *dssdev, int data_lines);
546 };
547
548 struct omapdss_sdi_ops {
549 int (*connect)(struct omap_dss_device *dssdev,
550 struct omap_dss_device *dst);
551 void (*disconnect)(struct omap_dss_device *dssdev,
552 struct omap_dss_device *dst);
553
554 int (*enable)(struct omap_dss_device *dssdev);
555 void (*disable)(struct omap_dss_device *dssdev);
556
557 int (*check_timings)(struct omap_dss_device *dssdev,
558 struct omap_video_timings *timings);
559 void (*set_timings)(struct omap_dss_device *dssdev,
560 struct omap_video_timings *timings);
561 void (*get_timings)(struct omap_dss_device *dssdev,
562 struct omap_video_timings *timings);
563
564 void (*set_datapairs)(struct omap_dss_device *dssdev, int datapairs);
565 };
566
567 struct omapdss_dvi_ops {
568 int (*connect)(struct omap_dss_device *dssdev,
569 struct omap_dss_device *dst);
570 void (*disconnect)(struct omap_dss_device *dssdev,
571 struct omap_dss_device *dst);
572
573 int (*enable)(struct omap_dss_device *dssdev);
574 void (*disable)(struct omap_dss_device *dssdev);
575
576 int (*check_timings)(struct omap_dss_device *dssdev,
577 struct omap_video_timings *timings);
578 void (*set_timings)(struct omap_dss_device *dssdev,
579 struct omap_video_timings *timings);
580 void (*get_timings)(struct omap_dss_device *dssdev,
581 struct omap_video_timings *timings);
582 };
583
584 struct omapdss_atv_ops {
585 int (*connect)(struct omap_dss_device *dssdev,
586 struct omap_dss_device *dst);
587 void (*disconnect)(struct omap_dss_device *dssdev,
588 struct omap_dss_device *dst);
589
590 int (*enable)(struct omap_dss_device *dssdev);
591 void (*disable)(struct omap_dss_device *dssdev);
592
593 int (*check_timings)(struct omap_dss_device *dssdev,
594 struct omap_video_timings *timings);
595 void (*set_timings)(struct omap_dss_device *dssdev,
596 struct omap_video_timings *timings);
597 void (*get_timings)(struct omap_dss_device *dssdev,
598 struct omap_video_timings *timings);
599
600 void (*set_type)(struct omap_dss_device *dssdev,
601 enum omap_dss_venc_type type);
602 void (*invert_vid_out_polarity)(struct omap_dss_device *dssdev,
603 bool invert_polarity);
604
605 int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
606 u32 (*get_wss)(struct omap_dss_device *dssdev);
607 };
608
609 struct omapdss_hdmi_ops {
610 int (*connect)(struct omap_dss_device *dssdev,
611 struct omap_dss_device *dst);
612 void (*disconnect)(struct omap_dss_device *dssdev,
613 struct omap_dss_device *dst);
614
615 int (*enable)(struct omap_dss_device *dssdev);
616 void (*disable)(struct omap_dss_device *dssdev);
617
618 int (*check_timings)(struct omap_dss_device *dssdev,
619 struct omap_video_timings *timings);
620 void (*set_timings)(struct omap_dss_device *dssdev,
621 struct omap_video_timings *timings);
622 void (*get_timings)(struct omap_dss_device *dssdev,
623 struct omap_video_timings *timings);
624
625 int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
626 bool (*detect)(struct omap_dss_device *dssdev);
627
628 int (*set_hdmi_mode)(struct omap_dss_device *dssdev, bool hdmi_mode);
629 int (*set_infoframe)(struct omap_dss_device *dssdev,
630 const struct hdmi_avi_infoframe *avi);
631 };
632
633 struct omapdss_dsi_ops {
634 int (*connect)(struct omap_dss_device *dssdev,
635 struct omap_dss_device *dst);
636 void (*disconnect)(struct omap_dss_device *dssdev,
637 struct omap_dss_device *dst);
638
639 int (*enable)(struct omap_dss_device *dssdev);
640 void (*disable)(struct omap_dss_device *dssdev, bool disconnect_lanes,
641 bool enter_ulps);
642
643 /* bus configuration */
644 int (*set_config)(struct omap_dss_device *dssdev,
645 const struct omap_dss_dsi_config *cfg);
646 int (*configure_pins)(struct omap_dss_device *dssdev,
647 const struct omap_dsi_pin_config *pin_cfg);
648
649 void (*enable_hs)(struct omap_dss_device *dssdev, int channel,
650 bool enable);
651 int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
652
653 int (*update)(struct omap_dss_device *dssdev, int channel,
654 void (*callback)(int, void *), void *data);
655
656 void (*bus_lock)(struct omap_dss_device *dssdev);
657 void (*bus_unlock)(struct omap_dss_device *dssdev);
658
659 int (*enable_video_output)(struct omap_dss_device *dssdev, int channel);
660 void (*disable_video_output)(struct omap_dss_device *dssdev,
661 int channel);
662
663 int (*request_vc)(struct omap_dss_device *dssdev, int *channel);
664 int (*set_vc_id)(struct omap_dss_device *dssdev, int channel,
665 int vc_id);
666 void (*release_vc)(struct omap_dss_device *dssdev, int channel);
667
668 /* data transfer */
669 int (*dcs_write)(struct omap_dss_device *dssdev, int channel,
670 u8 *data, int len);
671 int (*dcs_write_nosync)(struct omap_dss_device *dssdev, int channel,
672 u8 *data, int len);
673 int (*dcs_read)(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
674 u8 *data, int len);
675
676 int (*gen_write)(struct omap_dss_device *dssdev, int channel,
677 u8 *data, int len);
678 int (*gen_write_nosync)(struct omap_dss_device *dssdev, int channel,
679 u8 *data, int len);
680 int (*gen_read)(struct omap_dss_device *dssdev, int channel,
681 u8 *reqdata, int reqlen,
682 u8 *data, int len);
683
684 int (*bta_sync)(struct omap_dss_device *dssdev, int channel);
685
686 int (*set_max_rx_packet_size)(struct omap_dss_device *dssdev,
687 int channel, u16 plen);
688 };
689
690 struct omap_dss_device {
691 struct kobject kobj;
692 struct device *dev;
693
694 struct module *owner;
695
696 struct list_head panel_list;
697
698 /* alias in the form of "display%d" */
699 char alias[16];
700
701 enum omap_display_type type;
702 enum omap_display_type output_type;
703
704 union {
705 struct {
706 u8 data_lines;
707 } dpi;
708
709 struct {
710 u8 channel;
711 u8 data_lines;
712 } rfbi;
713
714 struct {
715 u8 datapairs;
716 } sdi;
717
718 struct {
719 int module;
720 } dsi;
721
722 struct {
723 enum omap_dss_venc_type type;
724 bool invert_polarity;
725 } venc;
726 } phy;
727
728 struct {
729 struct omap_video_timings timings;
730
731 enum omap_dss_dsi_pixel_format dsi_pix_fmt;
732 enum omap_dss_dsi_mode dsi_mode;
733 } panel;
734
735 struct {
736 u8 pixel_size;
737 struct rfbi_timings rfbi_timings;
738 } ctrl;
739
740 const char *name;
741
742 /* used to match device to driver */
743 const char *driver_name;
744
745 void *data;
746
747 struct omap_dss_driver *driver;
748
749 union {
750 const struct omapdss_dpi_ops *dpi;
751 const struct omapdss_sdi_ops *sdi;
752 const struct omapdss_dvi_ops *dvi;
753 const struct omapdss_hdmi_ops *hdmi;
754 const struct omapdss_atv_ops *atv;
755 const struct omapdss_dsi_ops *dsi;
756 } ops;
757
758 /* helper variable for driver suspend/resume */
759 bool activate_after_resume;
760
761 enum omap_display_caps caps;
762
763 struct omap_dss_device *src;
764
765 enum omap_dss_display_state state;
766
767 /* OMAP DSS output specific fields */
768
769 struct list_head list;
770
771 /* DISPC channel for this output */
772 enum omap_channel dispc_channel;
773
774 /* output instance */
775 enum omap_dss_output_id id;
776
777 /* the port number in the DT node */
778 int port_num;
779
780 /* dynamic fields */
781 struct omap_overlay_manager *manager;
782
783 struct omap_dss_device *dst;
784 };
785
786 struct omap_dss_hdmi_data
787 {
788 int ct_cp_hpd_gpio;
789 int ls_oe_gpio;
790 int hpd_gpio;
791 };
792
793 struct omap_dss_driver {
794 int (*probe)(struct omap_dss_device *);
795 void (*remove)(struct omap_dss_device *);
796
797 int (*connect)(struct omap_dss_device *dssdev);
798 void (*disconnect)(struct omap_dss_device *dssdev);
799
800 int (*enable)(struct omap_dss_device *display);
801 void (*disable)(struct omap_dss_device *display);
802 int (*run_test)(struct omap_dss_device *display, int test);
803
804 int (*update)(struct omap_dss_device *dssdev,
805 u16 x, u16 y, u16 w, u16 h);
806 int (*sync)(struct omap_dss_device *dssdev);
807
808 int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
809 int (*get_te)(struct omap_dss_device *dssdev);
810
811 u8 (*get_rotate)(struct omap_dss_device *dssdev);
812 int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
813
814 bool (*get_mirror)(struct omap_dss_device *dssdev);
815 int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
816
817 int (*memory_read)(struct omap_dss_device *dssdev,
818 void *buf, size_t size,
819 u16 x, u16 y, u16 w, u16 h);
820
821 void (*get_resolution)(struct omap_dss_device *dssdev,
822 u16 *xres, u16 *yres);
823 void (*get_dimensions)(struct omap_dss_device *dssdev,
824 u32 *width, u32 *height);
825 int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
826
827 int (*check_timings)(struct omap_dss_device *dssdev,
828 struct omap_video_timings *timings);
829 void (*set_timings)(struct omap_dss_device *dssdev,
830 struct omap_video_timings *timings);
831 void (*get_timings)(struct omap_dss_device *dssdev,
832 struct omap_video_timings *timings);
833
834 int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
835 u32 (*get_wss)(struct omap_dss_device *dssdev);
836
837 int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
838 bool (*detect)(struct omap_dss_device *dssdev);
839
840 int (*set_hdmi_mode)(struct omap_dss_device *dssdev, bool hdmi_mode);
841 int (*set_hdmi_infoframe)(struct omap_dss_device *dssdev,
842 const struct hdmi_avi_infoframe *avi);
843 };
844
845 enum omapdss_version omapdss_get_version(void);
846 bool omapdss_is_initialized(void);
847
848 int omap_dss_register_driver(struct omap_dss_driver *);
849 void omap_dss_unregister_driver(struct omap_dss_driver *);
850
851 int omapdss_register_display(struct omap_dss_device *dssdev);
852 void omapdss_unregister_display(struct omap_dss_device *dssdev);
853
854 struct omap_dss_device *omap_dss_get_device(struct omap_dss_device *dssdev);
855 void omap_dss_put_device(struct omap_dss_device *dssdev);
856 #define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
857 struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
858 struct omap_dss_device *omap_dss_find_device(void *data,
859 int (*match)(struct omap_dss_device *dssdev, void *data));
860 const char *omapdss_get_default_display_name(void);
861
862 void videomode_to_omap_video_timings(const struct videomode *vm,
863 struct omap_video_timings *ovt);
864 void omap_video_timings_to_videomode(const struct omap_video_timings *ovt,
865 struct videomode *vm);
866
867 int dss_feat_get_num_mgrs(void);
868 int dss_feat_get_num_ovls(void);
869 enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel);
870 enum omap_dss_output_id dss_feat_get_supported_outputs(enum omap_channel channel);
871 enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane);
872
873
874
875 int omap_dss_get_num_overlay_managers(void);
876 struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
877
878 int omap_dss_get_num_overlays(void);
879 struct omap_overlay *omap_dss_get_overlay(int num);
880
881 int omapdss_register_output(struct omap_dss_device *output);
882 void omapdss_unregister_output(struct omap_dss_device *output);
883 struct omap_dss_device *omap_dss_get_output(enum omap_dss_output_id id);
884 struct omap_dss_device *omap_dss_find_output(const char *name);
885 struct omap_dss_device *omap_dss_find_output_by_port_node(struct device_node *port);
886 int omapdss_output_set_device(struct omap_dss_device *out,
887 struct omap_dss_device *dssdev);
888 int omapdss_output_unset_device(struct omap_dss_device *out);
889
890 struct omap_dss_device *omapdss_find_output_from_display(struct omap_dss_device *dssdev);
891 struct omap_overlay_manager *omapdss_find_mgr_from_display(struct omap_dss_device *dssdev);
892
893 void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
894 u16 *xres, u16 *yres);
895 int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);
896 void omapdss_default_get_timings(struct omap_dss_device *dssdev,
897 struct omap_video_timings *timings);
898
899 typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
900 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
901 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
902
903 u32 dispc_read_irqstatus(void);
904 void dispc_clear_irqstatus(u32 mask);
905 u32 dispc_read_irqenable(void);
906 void dispc_write_irqenable(u32 mask);
907
908 int dispc_request_irq(irq_handler_t handler, void *dev_id);
909 void dispc_free_irq(void *dev_id);
910
911 int dispc_runtime_get(void);
912 void dispc_runtime_put(void);
913
914 void dispc_mgr_enable(enum omap_channel channel, bool enable);
915 bool dispc_mgr_is_enabled(enum omap_channel channel);
916 u32 dispc_mgr_get_vsync_irq(enum omap_channel channel);
917 u32 dispc_mgr_get_framedone_irq(enum omap_channel channel);
918 u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel);
919 bool dispc_mgr_go_busy(enum omap_channel channel);
920 void dispc_mgr_go(enum omap_channel channel);
921 void dispc_mgr_set_lcd_config(enum omap_channel channel,
922 const struct dss_lcd_mgr_config *config);
923 void dispc_mgr_set_timings(enum omap_channel channel,
924 const struct omap_video_timings *timings);
925 void dispc_mgr_setup(enum omap_channel channel,
926 const struct omap_overlay_manager_info *info);
927
928 int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel,
929 const struct omap_overlay_info *oi,
930 const struct omap_video_timings *timings,
931 int *x_predecim, int *y_predecim);
932
933 int dispc_ovl_enable(enum omap_plane plane, bool enable);
934 bool dispc_ovl_enabled(enum omap_plane plane);
935 void dispc_ovl_set_channel_out(enum omap_plane plane,
936 enum omap_channel channel);
937 int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
938 bool replication, const struct omap_video_timings *mgr_timings,
939 bool mem_to_mem);
940
941 int omapdss_compat_init(void);
942 void omapdss_compat_uninit(void);
943
944 struct dss_mgr_ops {
945 int (*connect)(struct omap_overlay_manager *mgr,
946 struct omap_dss_device *dst);
947 void (*disconnect)(struct omap_overlay_manager *mgr,
948 struct omap_dss_device *dst);
949
950 void (*start_update)(struct omap_overlay_manager *mgr);
951 int (*enable)(struct omap_overlay_manager *mgr);
952 void (*disable)(struct omap_overlay_manager *mgr);
953 void (*set_timings)(struct omap_overlay_manager *mgr,
954 const struct omap_video_timings *timings);
955 void (*set_lcd_config)(struct omap_overlay_manager *mgr,
956 const struct dss_lcd_mgr_config *config);
957 int (*register_framedone_handler)(struct omap_overlay_manager *mgr,
958 void (*handler)(void *), void *data);
959 void (*unregister_framedone_handler)(struct omap_overlay_manager *mgr,
960 void (*handler)(void *), void *data);
961 };
962
963 int dss_install_mgr_ops(const struct dss_mgr_ops *mgr_ops);
964 void dss_uninstall_mgr_ops(void);
965
966 int dss_mgr_connect(struct omap_overlay_manager *mgr,
967 struct omap_dss_device *dst);
968 void dss_mgr_disconnect(struct omap_overlay_manager *mgr,
969 struct omap_dss_device *dst);
970 void dss_mgr_set_timings(struct omap_overlay_manager *mgr,
971 const struct omap_video_timings *timings);
972 void dss_mgr_set_lcd_config(struct omap_overlay_manager *mgr,
973 const struct dss_lcd_mgr_config *config);
974 int dss_mgr_enable(struct omap_overlay_manager *mgr);
975 void dss_mgr_disable(struct omap_overlay_manager *mgr);
976 void dss_mgr_start_update(struct omap_overlay_manager *mgr);
977 int dss_mgr_register_framedone_handler(struct omap_overlay_manager *mgr,
978 void (*handler)(void *), void *data);
979 void dss_mgr_unregister_framedone_handler(struct omap_overlay_manager *mgr,
980 void (*handler)(void *), void *data);
981
982 static inline bool omapdss_device_is_connected(struct omap_dss_device *dssdev)
983 {
984 return dssdev->src;
985 }
986
987 static inline bool omapdss_device_is_enabled(struct omap_dss_device *dssdev)
988 {
989 return dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
990 }
991
992 struct device_node *
993 omapdss_of_get_next_port(const struct device_node *parent,
994 struct device_node *prev);
995
996 struct device_node *
997 omapdss_of_get_next_endpoint(const struct device_node *parent,
998 struct device_node *prev);
999
1000 struct device_node *
1001 omapdss_of_get_first_endpoint(const struct device_node *parent);
1002
1003 struct omap_dss_device *
1004 omapdss_of_find_source_for_first_ep(struct device_node *node);
1005
1006 #endif
Linux with added FPC-III support