arch/arm/boot/dts/armada-xp-98dx3236.dtsi

   1 /*
   2  * Device Tree Include file for Marvell 98dx3236 family SoC
   3  *
   4  * Copyright (C) 2016 Allied Telesis Labs
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  *
  44  * Contains definitions specific to the 98dx3236 SoC that are not
  45  * common to all Armada XP SoCs.
  46  */
  47
  48 #include "armada-xp.dtsi"
  49
  50 / {
  51         model = "Marvell 98DX3236 SoC";
  52         compatible = "marvell,armadaxp-98dx3236", "marvell,armadaxp", "marvell,armada-370-xp";
  53
  54         aliases {
  55                 gpio0 = &gpio0;
  56                 gpio1 = &gpio1;
  57                 gpio2 = &gpio2;
  58         };
  59
  60         cpus {
  61                 #address-cells = <1>;
  62                 #size-cells = <0>;
  63                 enable-method = "marvell,98dx3236-smp";
  64
  65                 cpu@0 {
  66                         device_type = "cpu";
  67                         compatible = "marvell,sheeva-v7";
  68                         reg = <0>;
  69                         clocks = <&cpuclk 0>;
  70                         clock-latency = <1000000>;
  71                 };
  72         };
  73
  74         soc {
  75                 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
  76                           MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
  77                           MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
  78                           MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
  79                           MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
  80
  81                 /*
  82                  * 98DX3236 has 1 x1 PCIe unit Gen2.0
  83                  */
  84                 pciec: pcie-controller@82000000 {
  85                         compatible = "marvell,armada-xp-pcie";
  86                         status = "disabled";
  87                         device_type = "pci";
  88
  89                         #address-cells = <3>;
  90                         #size-cells = <2>;
  91
  92                         msi-parent = <&mpic>;
  93                         bus-range = <0x00 0xff>;
  94
  95                         ranges =
  96                                <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000   /* Port 0.0 registers */
  97                                 0x82000000 0x1 0       MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
  98                                 0x81000000 0x1 0       MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO  */
  99                                 0x82000000 0x2 0       MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */>;
 100
 101                         pcie1: pcie@1,0 {
 102                                 device_type = "pci";
 103                                 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
 104                                 reg = <0x0800 0 0 0 0>;
 105                                 #address-cells = <3>;
 106                                 #size-cells = <2>;
 107                                 #interrupt-cells = <1>;
 108                                 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
 109                                           0x81000000 0 0 0x81000000 0x1 0 1 0>;
 110                                 interrupt-map-mask = <0 0 0 0>;
 111                                 interrupt-map = <0 0 0 0 &mpic 58>;
 112                                 marvell,pcie-port = <0>;
 113                                 marvell,pcie-lane = <0>;
 114                                 clocks = <&gateclk 5>;
 115                                 status = "disabled";
 116                         };
 117                 };
 118
 119                 internal-regs {
 120                         coreclk: mvebu-sar@18230 {
 121                                 compatible = "marvell,mv98dx3236-core-clock";
 122                         };
 123
 124                         cpuclk: clock-complex@18700 {
 125                                 compatible = "marvell,mv98dx3236-cpu-clock";
 126                         };
 127
 128                         corediv-clock@18740 {
 129                                 status = "disabled";
 130                         };
 131
 132                         xor@60900 {
 133                                 status = "disabled";
 134                         };
 135
 136                         crypto@90000 {
 137                                 status = "disabled";
 138                         };
 139
 140                         xor@f0900 {
 141                                 status = "disabled";
 142                         };
 143
 144                         xor@f0800 {
 145                                 compatible = "marvell,orion-xor";
 146                                 reg = <0xf0800 0x100
 147                                        0xf0a00 0x100>;
 148                                 clocks = <&gateclk 22>;
 149                                 status = "okay";
 150
 151                                 xor10 {
 152                                         interrupts = <51>;
 153                                         dmacap,memcpy;
 154                                         dmacap,xor;
 155                                 };
 156                                 xor11 {
 157                                         interrupts = <52>;
 158                                         dmacap,memcpy;
 159                                         dmacap,xor;
 160                                         dmacap,memset;
 161                                 };
 162                         };
 163
 164                         gpio0: gpio@18100 {
 165                                 compatible = "marvell,orion-gpio";
 166                                 reg = <0x18100 0x40>;
 167                                 ngpios = <32>;
 168                                 gpio-controller;
 169                                 #gpio-cells = <2>;
 170                                 interrupt-controller;
 171                                 #interrupt-cells = <2>;
 172                                 interrupts = <82>, <83>, <84>, <85>;
 173                         };
 174
 175                         /* does not exist */
 176                         gpio1: gpio@18140 {
 177                                 compatible = "marvell,orion-gpio";
 178                                 reg = <0x18140 0x40>;
 179                                 status = "disabled";
 180                         };
 181
 182                         gpio2: gpio@18180 { /* rework some properties */
 183                                 compatible = "marvell,orion-gpio";
 184                                 reg = <0x18180 0x40>;
 185                                 ngpios = <1>; /* only gpio #32 */
 186                                 gpio-controller;
 187                                 #gpio-cells = <2>;
 188                                 interrupt-controller;
 189                                 #interrupt-cells = <2>;
 190                                 interrupts = <87>;
 191                         };
 192
 193                         nand: nand@d0000 {
 194                                 clocks = <&dfx_coredivclk 0>;
 195                         };
 196                 };
 197
 198                 dfxr: dfx-registers@ac000000 {
 199                         compatible = "simple-bus";
 200                         #address-cells = <1>;
 201                         #size-cells = <1>;
 202                         ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
 203
 204                         dfx_coredivclk: corediv-clock@f8268 {
 205                                 compatible = "marvell,mv98dx3236-corediv-clock";
 206                                 reg = <0xf8268 0xc>;
 207                                 #clock-cells = <1>;
 208                                 clocks = <&mainpll>;
 209                                 clock-output-names = "nand";
 210                         };
 211
 212                         dfx: dfx@0 {
 213                                 compatible = "marvell,dfx-server";
 214                                 reg = <0 0x100000>;
 215                         };
 216                 };
 217
 218                 switch: switch@a8000000 {
 219                         compatible = "simple-bus";
 220                         #address-cells = <1>;
 221                         #size-cells = <1>;
 222                         ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>;
 223
 224                         pp0: packet-processor@0 {
 225                                 compatible = "marvell,prestera-98dx3236";
 226                                 reg = <0 0x4000000>;
 227                                 interrupts = <33>, <34>, <35>;
 228                                 dfx = <&dfx>;
 229                         };
 230                 };
 231         };
 232 };
 233
 234 &pinctrl {
 235         compatible = "marvell,98dx3236-pinctrl";
 236
 237         spi0_pins: spi0-pins {
 238                 marvell,pins = "mpp0", "mpp1",
 239                                "mpp2", "mpp3";
 240                 marvell,function = "spi0";
 241         };
 242 };
 243
 244 &sdio {
 245         status = "disabled";
 246 };
 247
 248 &crypto_sram0 {
 249         status = "disabled";
 250 };
 251
 252 &crypto_sram1 {
 253         status = "disabled";
 254 };