| blob | d1383dde43eb91511a674f37024d7be07be92ac8 |
1 /*
2 * Device Tree Include file for Marvell Armada XP family SoC
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 *
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPL or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
11 * whole.
12 *
13 * a) This file is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
17 *
18 * This file is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * Or, alternatively,
24 *
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use,
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
32 * conditions:
33 *
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
36 *
37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
45 *
46 * Contains definitions specific to the Armada XP MV78460 SoC that are not
47 * common to all Armada XP SoCs.
48 */
50 #include "armada-xp.dtsi"
52 / {
53 model = "Marvell Armada XP MV78460 SoC";
54 compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
56 aliases {
57 gpio0 = &gpio0;
58 gpio1 = &gpio1;
59 gpio2 = &gpio2;
60 };
63 cpus {
64 #address-cells = <1>;
65 #size-cells = <0>;
66 enable-method = "marvell,armada-xp-smp";
68 cpu@0 {
69 device_type = "cpu";
70 compatible = "marvell,sheeva-v7";
71 reg = <0>;
72 clocks = <&cpuclk 0>;
73 clock-latency = <1000000>;
74 };
76 cpu@1 {
77 device_type = "cpu";
78 compatible = "marvell,sheeva-v7";
79 reg = <1>;
80 clocks = <&cpuclk 1>;
81 clock-latency = <1000000>;
82 };
84 cpu@2 {
85 device_type = "cpu";
86 compatible = "marvell,sheeva-v7";
87 reg = <2>;
88 clocks = <&cpuclk 2>;
89 clock-latency = <1000000>;
90 };
92 cpu@3 {
93 device_type = "cpu";
94 compatible = "marvell,sheeva-v7";
95 reg = <3>;
96 clocks = <&cpuclk 3>;
97 clock-latency = <1000000>;
98 };
99 };
101 soc {
102 /*
103 * MV78460 has 4 PCIe units Gen2.0: Two units can be
104 * configured as x4 or quad x1 lanes. Two units are
105 * x4/x1.
106 */
107 pciec: pcie-controller@82000000 {
108 compatible = "marvell,armada-xp-pcie";
109 status = "disabled";
110 device_type = "pci";
112 #address-cells = <3>;
113 #size-cells = <2>;
115 msi-parent = <&mpic>;
116 bus-range = <0x00 0xff>;
118 ranges =
119 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
120 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
121 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
122 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
123 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
124 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
125 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
126 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
127 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
128 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
129 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
130 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
131 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
132 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
133 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
134 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
135 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
136 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
138 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
139 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
140 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
141 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
142 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
143 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
144 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
145 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
147 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
148 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */
150 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
151 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
153 pcie1: pcie@1,0 {
154 device_type = "pci";
155 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
156 reg = <0x0800 0 0 0 0>;
157 #address-cells = <3>;
158 #size-cells = <2>;
159 #interrupt-cells = <1>;
160 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
161 0x81000000 0 0 0x81000000 0x1 0 1 0>;
162 interrupt-map-mask = <0 0 0 0>;
163 interrupt-map = <0 0 0 0 &mpic 58>;
164 marvell,pcie-port = <0>;
165 marvell,pcie-lane = <0>;
166 clocks = <&gateclk 5>;
167 status = "disabled";
168 };
170 pcie2: pcie@2,0 {
171 device_type = "pci";
172 assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
173 reg = <0x1000 0 0 0 0>;
174 #address-cells = <3>;
175 #size-cells = <2>;
176 #interrupt-cells = <1>;
177 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
178 0x81000000 0 0 0x81000000 0x2 0 1 0>;
179 interrupt-map-mask = <0 0 0 0>;
180 interrupt-map = <0 0 0 0 &mpic 59>;
181 marvell,pcie-port = <0>;
182 marvell,pcie-lane = <1>;
183 clocks = <&gateclk 6>;
184 status = "disabled";
185 };
187 pcie3: pcie@3,0 {
188 device_type = "pci";
189 assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
190 reg = <0x1800 0 0 0 0>;
191 #address-cells = <3>;
192 #size-cells = <2>;
193 #interrupt-cells = <1>;
194 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
195 0x81000000 0 0 0x81000000 0x3 0 1 0>;
196 interrupt-map-mask = <0 0 0 0>;
197 interrupt-map = <0 0 0 0 &mpic 60>;
198 marvell,pcie-port = <0>;
199 marvell,pcie-lane = <2>;
200 clocks = <&gateclk 7>;
201 status = "disabled";
202 };
204 pcie4: pcie@4,0 {
205 device_type = "pci";
206 assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
207 reg = <0x2000 0 0 0 0>;
208 #address-cells = <3>;
209 #size-cells = <2>;
210 #interrupt-cells = <1>;
211 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
212 0x81000000 0 0 0x81000000 0x4 0 1 0>;
213 interrupt-map-mask = <0 0 0 0>;
214 interrupt-map = <0 0 0 0 &mpic 61>;
215 marvell,pcie-port = <0>;
216 marvell,pcie-lane = <3>;
217 clocks = <&gateclk 8>;
218 status = "disabled";
219 };
221 pcie5: pcie@5,0 {
222 device_type = "pci";
223 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
224 reg = <0x2800 0 0 0 0>;
225 #address-cells = <3>;
226 #size-cells = <2>;
227 #interrupt-cells = <1>;
228 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
229 0x81000000 0 0 0x81000000 0x5 0 1 0>;
230 interrupt-map-mask = <0 0 0 0>;
231 interrupt-map = <0 0 0 0 &mpic 62>;
232 marvell,pcie-port = <1>;
233 marvell,pcie-lane = <0>;
234 clocks = <&gateclk 9>;
235 status = "disabled";
236 };
238 pcie6: pcie@6,0 {
239 device_type = "pci";
240 assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
241 reg = <0x3000 0 0 0 0>;
242 #address-cells = <3>;
243 #size-cells = <2>;
244 #interrupt-cells = <1>;
245 ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
246 0x81000000 0 0 0x81000000 0x6 0 1 0>;
247 interrupt-map-mask = <0 0 0 0>;
248 interrupt-map = <0 0 0 0 &mpic 63>;
249 marvell,pcie-port = <1>;
250 marvell,pcie-lane = <1>;
251 clocks = <&gateclk 10>;
252 status = "disabled";
253 };
255 pcie7: pcie@7,0 {
256 device_type = "pci";
257 assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
258 reg = <0x3800 0 0 0 0>;
259 #address-cells = <3>;
260 #size-cells = <2>;
261 #interrupt-cells = <1>;
262 ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
263 0x81000000 0 0 0x81000000 0x7 0 1 0>;
264 interrupt-map-mask = <0 0 0 0>;
265 interrupt-map = <0 0 0 0 &mpic 64>;
266 marvell,pcie-port = <1>;
267 marvell,pcie-lane = <2>;
268 clocks = <&gateclk 11>;
269 status = "disabled";
270 };
272 pcie8: pcie@8,0 {
273 device_type = "pci";
274 assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
275 reg = <0x4000 0 0 0 0>;
276 #address-cells = <3>;
277 #size-cells = <2>;
278 #interrupt-cells = <1>;
279 ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
280 0x81000000 0 0 0x81000000 0x8 0 1 0>;
281 interrupt-map-mask = <0 0 0 0>;
282 interrupt-map = <0 0 0 0 &mpic 65>;
283 marvell,pcie-port = <1>;
284 marvell,pcie-lane = <3>;
285 clocks = <&gateclk 12>;
286 status = "disabled";
287 };
289 pcie9: pcie@9,0 {
290 device_type = "pci";
291 assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
292 reg = <0x4800 0 0 0 0>;
293 #address-cells = <3>;
294 #size-cells = <2>;
295 #interrupt-cells = <1>;
296 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
297 0x81000000 0 0 0x81000000 0x9 0 1 0>;
298 interrupt-map-mask = <0 0 0 0>;
299 interrupt-map = <0 0 0 0 &mpic 99>;
300 marvell,pcie-port = <2>;
301 marvell,pcie-lane = <0>;
302 clocks = <&gateclk 26>;
303 status = "disabled";
304 };
306 pcie10: pcie@10,0 {
307 device_type = "pci";
308 assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
309 reg = <0x5000 0 0 0 0>;
310 #address-cells = <3>;
311 #size-cells = <2>;
312 #interrupt-cells = <1>;
313 ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
314 0x81000000 0 0 0x81000000 0xa 0 1 0>;
315 interrupt-map-mask = <0 0 0 0>;
316 interrupt-map = <0 0 0 0 &mpic 103>;
317 marvell,pcie-port = <3>;
318 marvell,pcie-lane = <0>;
319 clocks = <&gateclk 27>;
320 status = "disabled";
321 };
322 };
324 internal-regs {
325 gpio0: gpio@18100 {
326 compatible = "marvell,orion-gpio";
327 reg = <0x18100 0x40>;
328 ngpios = <32>;
329 gpio-controller;
330 #gpio-cells = <2>;
331 interrupt-controller;
332 #interrupt-cells = <2>;
333 interrupts = <82>, <83>, <84>, <85>;
334 };
336 gpio1: gpio@18140 {
337 compatible = "marvell,orion-gpio";
338 reg = <0x18140 0x40>;
339 ngpios = <32>;
340 gpio-controller;
341 #gpio-cells = <2>;
342 interrupt-controller;
343 #interrupt-cells = <2>;
344 interrupts = <87>, <88>, <89>, <90>;
345 };
347 gpio2: gpio@18180 {
348 compatible = "marvell,orion-gpio";
349 reg = <0x18180 0x40>;
350 ngpios = <3>;
351 gpio-controller;
352 #gpio-cells = <2>;
353 interrupt-controller;
354 #interrupt-cells = <2>;
355 interrupts = <91>;
356 };
358 eth3: ethernet@34000 {
359 compatible = "marvell,armada-xp-neta";
360 reg = <0x34000 0x4000>;
361 interrupts = <14>;
362 clocks = <&gateclk 1>;
363 status = "disabled";
364 };
365 };
366 };
367 };
369 &pinctrl {
370 compatible = "marvell,mv78460-pinctrl";
371 };