| blob | 18def1c774d5deb14e859c4d0c0e75439f6a9147 |
1 /*
2 * Samsung's Exynos4 SoC series common device tree source
3 *
4 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 * Copyright (c) 2010-2011 Linaro Ltd.
7 * www.linaro.org
8 *
9 * Samsung's Exynos4 SoC series device nodes are listed in this file. Particular
10 * SoCs from Exynos4 series can include this file and provide values for SoCs
11 * specfic bindings.
12 *
13 * Note: This file does not include device nodes for all the controllers in
14 * Exynos4 SoCs. As device tree coverage for Exynos4 increases, additional
15 * nodes can be added to this file.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 */
22 #include <dt-bindings/clock/exynos4.h>
23 #include <dt-bindings/clock/exynos-audss-clk.h>
24 #include <dt-bindings/interrupt-controller/arm-gic.h>
25 #include <dt-bindings/interrupt-controller/irq.h>
26 #include "exynos-syscon-restart.dtsi"
28 / {
29 interrupt-parent = <&gic>;
30 #address-cells = <1>;
31 #size-cells = <1>;
33 aliases {
34 spi0 = &spi_0;
35 spi1 = &spi_1;
36 spi2 = &spi_2;
37 i2c0 = &i2c_0;
38 i2c1 = &i2c_1;
39 i2c2 = &i2c_2;
40 i2c3 = &i2c_3;
41 i2c4 = &i2c_4;
42 i2c5 = &i2c_5;
43 i2c6 = &i2c_6;
44 i2c7 = &i2c_7;
45 i2c8 = &i2c_8;
46 csis0 = &csis_0;
47 csis1 = &csis_1;
48 fimc0 = &fimc_0;
49 fimc1 = &fimc_1;
50 fimc2 = &fimc_2;
51 fimc3 = &fimc_3;
52 serial0 = &serial_0;
53 serial1 = &serial_1;
54 serial2 = &serial_2;
55 serial3 = &serial_3;
56 };
58 clock_audss: clock-controller@03810000 {
59 compatible = "samsung,exynos4210-audss-clock";
60 reg = <0x03810000 0x0C>;
61 #clock-cells = <1>;
62 };
64 i2s0: i2s@03830000 {
65 compatible = "samsung,s5pv210-i2s";
66 reg = <0x03830000 0x100>;
67 clocks = <&clock_audss EXYNOS_I2S_BUS>,
68 <&clock_audss EXYNOS_DOUT_AUD_BUS>,
69 <&clock_audss EXYNOS_SCLK_I2S>;
70 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
71 #clock-cells = <1>;
72 clock-output-names = "i2s_cdclk0";
73 dmas = <&pdma0 12>, <&pdma0 11>, <&pdma0 10>;
74 dma-names = "tx", "rx", "tx-sec";
75 samsung,idma-addr = <0x03000000>;
76 #sound-dai-cells = <1>;
77 status = "disabled";
78 };
80 chipid@10000000 {
81 compatible = "samsung,exynos4210-chipid";
82 reg = <0x10000000 0x100>;
83 };
85 scu: snoop-control-unit@10500000 {
86 compatible = "arm,cortex-a9-scu";
87 reg = <0x10500000 0x2000>;
88 };
90 memory-controller@12570000 {
91 compatible = "samsung,exynos4210-srom";
92 reg = <0x12570000 0x14>;
93 };
95 mipi_phy: video-phy {
96 compatible = "samsung,s5pv210-mipi-video-phy";
97 #phy-cells = <1>;
98 syscon = <&pmu_system_controller>;
99 };
101 pd_mfc: mfc-power-domain@10023C40 {
102 compatible = "samsung,exynos4210-pd";
103 reg = <0x10023C40 0x20>;
104 #power-domain-cells = <0>;
105 label = "MFC";
106 };
108 pd_g3d: g3d-power-domain@10023C60 {
109 compatible = "samsung,exynos4210-pd";
110 reg = <0x10023C60 0x20>;
111 #power-domain-cells = <0>;
112 label = "G3D";
113 };
115 pd_lcd0: lcd0-power-domain@10023C80 {
116 compatible = "samsung,exynos4210-pd";
117 reg = <0x10023C80 0x20>;
118 #power-domain-cells = <0>;
119 label = "LCD0";
120 };
122 pd_tv: tv-power-domain@10023C20 {
123 compatible = "samsung,exynos4210-pd";
124 reg = <0x10023C20 0x20>;
125 #power-domain-cells = <0>;
126 power-domains = <&pd_lcd0>;
127 label = "TV";
128 };
130 pd_cam: cam-power-domain@10023C00 {
131 compatible = "samsung,exynos4210-pd";
132 reg = <0x10023C00 0x20>;
133 #power-domain-cells = <0>;
134 label = "CAM";
135 };
137 pd_gps: gps-power-domain@10023CE0 {
138 compatible = "samsung,exynos4210-pd";
139 reg = <0x10023CE0 0x20>;
140 #power-domain-cells = <0>;
141 label = "GPS";
142 };
144 pd_gps_alive: gps-alive-power-domain@10023D00 {
145 compatible = "samsung,exynos4210-pd";
146 reg = <0x10023D00 0x20>;
147 #power-domain-cells = <0>;
148 label = "GPS alive";
149 };
151 gic: interrupt-controller@10490000 {
152 compatible = "arm,cortex-a9-gic";
153 #interrupt-cells = <3>;
154 interrupt-controller;
155 reg = <0x10490000 0x10000>, <0x10480000 0x10000>;
156 };
158 combiner: interrupt-controller@10440000 {
159 compatible = "samsung,exynos4210-combiner";
160 #interrupt-cells = <2>;
161 interrupt-controller;
162 reg = <0x10440000 0x1000>;
163 };
165 pmu {
166 compatible = "arm,cortex-a9-pmu";
167 interrupt-parent = <&combiner>;
168 interrupts = <2 2>, <3 2>;
169 };
171 sys_reg: syscon@10010000 {
172 compatible = "samsung,exynos4-sysreg", "syscon";
173 reg = <0x10010000 0x400>;
174 };
176 pmu_system_controller: system-controller@10020000 {
177 compatible = "samsung,exynos4210-pmu", "syscon";
178 reg = <0x10020000 0x4000>;
179 interrupt-controller;
180 #interrupt-cells = <3>;
181 interrupt-parent = <&gic>;
182 };
184 dsi_0: dsi@11C80000 {
185 compatible = "samsung,exynos4210-mipi-dsi";
186 reg = <0x11C80000 0x10000>;
187 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
188 power-domains = <&pd_lcd0>;
189 phys = <&mipi_phy 1>;
190 phy-names = "dsim";
191 clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
192 clock-names = "bus_clk", "sclk_mipi";
193 status = "disabled";
194 #address-cells = <1>;
195 #size-cells = <0>;
196 };
198 camera {
199 compatible = "samsung,fimc", "simple-bus";
200 status = "disabled";
201 #address-cells = <1>;
202 #size-cells = <1>;
203 #clock-cells = <1>;
204 clock-output-names = "cam_a_clkout", "cam_b_clkout";
205 ranges;
207 fimc_0: fimc@11800000 {
208 compatible = "samsung,exynos4210-fimc";
209 reg = <0x11800000 0x1000>;
210 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
211 clocks = <&clock CLK_FIMC0>, <&clock CLK_SCLK_FIMC0>;
212 clock-names = "fimc", "sclk_fimc";
213 power-domains = <&pd_cam>;
214 samsung,sysreg = <&sys_reg>;
215 iommus = <&sysmmu_fimc0>;
216 status = "disabled";
217 };
219 fimc_1: fimc@11810000 {
220 compatible = "samsung,exynos4210-fimc";
221 reg = <0x11810000 0x1000>;
222 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
223 clocks = <&clock CLK_FIMC1>, <&clock CLK_SCLK_FIMC1>;
224 clock-names = "fimc", "sclk_fimc";
225 power-domains = <&pd_cam>;
226 samsung,sysreg = <&sys_reg>;
227 iommus = <&sysmmu_fimc1>;
228 status = "disabled";
229 };
231 fimc_2: fimc@11820000 {
232 compatible = "samsung,exynos4210-fimc";
233 reg = <0x11820000 0x1000>;
234 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
235 clocks = <&clock CLK_FIMC2>, <&clock CLK_SCLK_FIMC2>;
236 clock-names = "fimc", "sclk_fimc";
237 power-domains = <&pd_cam>;
238 samsung,sysreg = <&sys_reg>;
239 iommus = <&sysmmu_fimc2>;
240 status = "disabled";
241 };
243 fimc_3: fimc@11830000 {
244 compatible = "samsung,exynos4210-fimc";
245 reg = <0x11830000 0x1000>;
246 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
247 clocks = <&clock CLK_FIMC3>, <&clock CLK_SCLK_FIMC3>;
248 clock-names = "fimc", "sclk_fimc";
249 power-domains = <&pd_cam>;
250 samsung,sysreg = <&sys_reg>;
251 iommus = <&sysmmu_fimc3>;
252 status = "disabled";
253 };
255 csis_0: csis@11880000 {
256 compatible = "samsung,exynos4210-csis";
257 reg = <0x11880000 0x4000>;
258 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
259 clocks = <&clock CLK_CSIS0>, <&clock CLK_SCLK_CSIS0>;
260 clock-names = "csis", "sclk_csis";
261 bus-width = <4>;
262 power-domains = <&pd_cam>;
263 phys = <&mipi_phy 0>;
264 phy-names = "csis";
265 status = "disabled";
266 #address-cells = <1>;
267 #size-cells = <0>;
268 };
270 csis_1: csis@11890000 {
271 compatible = "samsung,exynos4210-csis";
272 reg = <0x11890000 0x4000>;
273 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
274 clocks = <&clock CLK_CSIS1>, <&clock CLK_SCLK_CSIS1>;
275 clock-names = "csis", "sclk_csis";
276 bus-width = <2>;
277 power-domains = <&pd_cam>;
278 phys = <&mipi_phy 2>;
279 phy-names = "csis";
280 status = "disabled";
281 #address-cells = <1>;
282 #size-cells = <0>;
283 };
284 };
286 watchdog: watchdog@10060000 {
287 compatible = "samsung,s3c2410-wdt";
288 reg = <0x10060000 0x100>;
289 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
290 clocks = <&clock CLK_WDT>;
291 clock-names = "watchdog";
292 status = "disabled";
293 };
295 rtc: rtc@10070000 {
296 compatible = "samsung,s3c6410-rtc";
297 reg = <0x10070000 0x100>;
298 interrupt-parent = <&pmu_system_controller>;
299 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
300 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
301 clocks = <&clock CLK_RTC>;
302 clock-names = "rtc";
303 status = "disabled";
304 };
306 keypad: keypad@100A0000 {
307 compatible = "samsung,s5pv210-keypad";
308 reg = <0x100A0000 0x100>;
309 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
310 clocks = <&clock CLK_KEYIF>;
311 clock-names = "keypad";
312 status = "disabled";
313 };
315 sdhci_0: sdhci@12510000 {
316 compatible = "samsung,exynos4210-sdhci";
317 reg = <0x12510000 0x100>;
318 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
319 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
320 clock-names = "hsmmc", "mmc_busclk.2";
321 status = "disabled";
322 };
324 sdhci_1: sdhci@12520000 {
325 compatible = "samsung,exynos4210-sdhci";
326 reg = <0x12520000 0x100>;
327 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
328 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
329 clock-names = "hsmmc", "mmc_busclk.2";
330 status = "disabled";
331 };
333 sdhci_2: sdhci@12530000 {
334 compatible = "samsung,exynos4210-sdhci";
335 reg = <0x12530000 0x100>;
336 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
337 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
338 clock-names = "hsmmc", "mmc_busclk.2";
339 status = "disabled";
340 };
342 sdhci_3: sdhci@12540000 {
343 compatible = "samsung,exynos4210-sdhci";
344 reg = <0x12540000 0x100>;
345 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
346 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
347 clock-names = "hsmmc", "mmc_busclk.2";
348 status = "disabled";
349 };
351 exynos_usbphy: exynos-usbphy@125B0000 {
352 compatible = "samsung,exynos4210-usb2-phy";
353 reg = <0x125B0000 0x100>;
354 samsung,pmureg-phandle = <&pmu_system_controller>;
355 clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>;
356 clock-names = "phy", "ref";
357 #phy-cells = <1>;
358 status = "disabled";
359 };
361 hsotg: hsotg@12480000 {
362 compatible = "samsung,s3c6400-hsotg";
363 reg = <0x12480000 0x20000>;
364 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
365 clocks = <&clock CLK_USB_DEVICE>;
366 clock-names = "otg";
367 phys = <&exynos_usbphy 0>;
368 phy-names = "usb2-phy";
369 status = "disabled";
370 };
372 ehci: ehci@12580000 {
373 compatible = "samsung,exynos4210-ehci";
374 reg = <0x12580000 0x100>;
375 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
376 clocks = <&clock CLK_USB_HOST>;
377 clock-names = "usbhost";
378 status = "disabled";
379 #address-cells = <1>;
380 #size-cells = <0>;
381 port@0 {
382 reg = <0>;
383 phys = <&exynos_usbphy 1>;
384 status = "disabled";
385 };
386 port@1 {
387 reg = <1>;
388 phys = <&exynos_usbphy 2>;
389 status = "disabled";
390 };
391 port@2 {
392 reg = <2>;
393 phys = <&exynos_usbphy 3>;
394 status = "disabled";
395 };
396 };
398 ohci: ohci@12590000 {
399 compatible = "samsung,exynos4210-ohci";
400 reg = <0x12590000 0x100>;
401 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
402 clocks = <&clock CLK_USB_HOST>;
403 clock-names = "usbhost";
404 status = "disabled";
405 #address-cells = <1>;
406 #size-cells = <0>;
407 port@0 {
408 reg = <0>;
409 phys = <&exynos_usbphy 1>;
410 status = "disabled";
411 };
412 };
414 i2s1: i2s@13960000 {
415 compatible = "samsung,s3c6410-i2s";
416 reg = <0x13960000 0x100>;
417 clocks = <&clock CLK_I2S1>;
418 clock-names = "iis";
419 #clock-cells = <1>;
420 clock-output-names = "i2s_cdclk1";
421 dmas = <&pdma1 12>, <&pdma1 11>;
422 dma-names = "tx", "rx";
423 #sound-dai-cells = <1>;
424 status = "disabled";
425 };
427 i2s2: i2s@13970000 {
428 compatible = "samsung,s3c6410-i2s";
429 reg = <0x13970000 0x100>;
430 clocks = <&clock CLK_I2S2>;
431 clock-names = "iis";
432 #clock-cells = <1>;
433 clock-output-names = "i2s_cdclk2";
434 dmas = <&pdma0 14>, <&pdma0 13>;
435 dma-names = "tx", "rx";
436 #sound-dai-cells = <1>;
437 status = "disabled";
438 };
440 mfc: codec@13400000 {
441 compatible = "samsung,mfc-v5";
442 reg = <0x13400000 0x10000>;
443 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
444 power-domains = <&pd_mfc>;
445 clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>;
446 clock-names = "mfc", "sclk_mfc";
447 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
448 iommu-names = "left", "right";
449 };
451 serial_0: serial@13800000 {
452 compatible = "samsung,exynos4210-uart";
453 reg = <0x13800000 0x100>;
454 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
455 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
456 clock-names = "uart", "clk_uart_baud0";
457 dmas = <&pdma0 15>, <&pdma0 16>;
458 dma-names = "rx", "tx";
459 status = "disabled";
460 };
462 serial_1: serial@13810000 {
463 compatible = "samsung,exynos4210-uart";
464 reg = <0x13810000 0x100>;
465 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
466 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
467 clock-names = "uart", "clk_uart_baud0";
468 dmas = <&pdma1 15>, <&pdma1 16>;
469 dma-names = "rx", "tx";
470 status = "disabled";
471 };
473 serial_2: serial@13820000 {
474 compatible = "samsung,exynos4210-uart";
475 reg = <0x13820000 0x100>;
476 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
477 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
478 clock-names = "uart", "clk_uart_baud0";
479 dmas = <&pdma0 17>, <&pdma0 18>;
480 dma-names = "rx", "tx";
481 status = "disabled";
482 };
484 serial_3: serial@13830000 {
485 compatible = "samsung,exynos4210-uart";
486 reg = <0x13830000 0x100>;
487 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
488 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
489 clock-names = "uart", "clk_uart_baud0";
490 dmas = <&pdma1 17>, <&pdma1 18>;
491 dma-names = "rx", "tx";
492 status = "disabled";
493 };
495 i2c_0: i2c@13860000 {
496 #address-cells = <1>;
497 #size-cells = <0>;
498 compatible = "samsung,s3c2440-i2c";
499 reg = <0x13860000 0x100>;
500 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
501 clocks = <&clock CLK_I2C0>;
502 clock-names = "i2c";
503 pinctrl-names = "default";
504 pinctrl-0 = <&i2c0_bus>;
505 status = "disabled";
506 };
508 i2c_1: i2c@13870000 {
509 #address-cells = <1>;
510 #size-cells = <0>;
511 compatible = "samsung,s3c2440-i2c";
512 reg = <0x13870000 0x100>;
513 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
514 clocks = <&clock CLK_I2C1>;
515 clock-names = "i2c";
516 pinctrl-names = "default";
517 pinctrl-0 = <&i2c1_bus>;
518 status = "disabled";
519 };
521 i2c_2: i2c@13880000 {
522 #address-cells = <1>;
523 #size-cells = <0>;
524 compatible = "samsung,s3c2440-i2c";
525 reg = <0x13880000 0x100>;
526 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
527 clocks = <&clock CLK_I2C2>;
528 clock-names = "i2c";
529 pinctrl-names = "default";
530 pinctrl-0 = <&i2c2_bus>;
531 status = "disabled";
532 };
534 i2c_3: i2c@13890000 {
535 #address-cells = <1>;
536 #size-cells = <0>;
537 compatible = "samsung,s3c2440-i2c";
538 reg = <0x13890000 0x100>;
539 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
540 clocks = <&clock CLK_I2C3>;
541 clock-names = "i2c";
542 pinctrl-names = "default";
543 pinctrl-0 = <&i2c3_bus>;
544 status = "disabled";
545 };
547 i2c_4: i2c@138A0000 {
548 #address-cells = <1>;
549 #size-cells = <0>;
550 compatible = "samsung,s3c2440-i2c";
551 reg = <0x138A0000 0x100>;
552 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
553 clocks = <&clock CLK_I2C4>;
554 clock-names = "i2c";
555 pinctrl-names = "default";
556 pinctrl-0 = <&i2c4_bus>;
557 status = "disabled";
558 };
560 i2c_5: i2c@138B0000 {
561 #address-cells = <1>;
562 #size-cells = <0>;
563 compatible = "samsung,s3c2440-i2c";
564 reg = <0x138B0000 0x100>;
565 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
566 clocks = <&clock CLK_I2C5>;
567 clock-names = "i2c";
568 pinctrl-names = "default";
569 pinctrl-0 = <&i2c5_bus>;
570 status = "disabled";
571 };
573 i2c_6: i2c@138C0000 {
574 #address-cells = <1>;
575 #size-cells = <0>;
576 compatible = "samsung,s3c2440-i2c";
577 reg = <0x138C0000 0x100>;
578 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
579 clocks = <&clock CLK_I2C6>;
580 clock-names = "i2c";
581 pinctrl-names = "default";
582 pinctrl-0 = <&i2c6_bus>;
583 status = "disabled";
584 };
586 i2c_7: i2c@138D0000 {
587 #address-cells = <1>;
588 #size-cells = <0>;
589 compatible = "samsung,s3c2440-i2c";
590 reg = <0x138D0000 0x100>;
591 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
592 clocks = <&clock CLK_I2C7>;
593 clock-names = "i2c";
594 pinctrl-names = "default";
595 pinctrl-0 = <&i2c7_bus>;
596 status = "disabled";
597 };
599 i2c_8: i2c@138E0000 {
600 #address-cells = <1>;
601 #size-cells = <0>;
602 compatible = "samsung,s3c2440-hdmiphy-i2c";
603 reg = <0x138E0000 0x100>;
604 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
605 clocks = <&clock CLK_I2C_HDMI>;
606 clock-names = "i2c";
607 status = "disabled";
609 hdmi_i2c_phy: hdmiphy@38 {
610 compatible = "exynos4210-hdmiphy";
611 reg = <0x38>;
612 };
613 };
615 spi_0: spi@13920000 {
616 compatible = "samsung,exynos4210-spi";
617 reg = <0x13920000 0x100>;
618 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
619 dmas = <&pdma0 7>, <&pdma0 6>;
620 dma-names = "tx", "rx";
621 #address-cells = <1>;
622 #size-cells = <0>;
623 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
624 clock-names = "spi", "spi_busclk0";
625 pinctrl-names = "default";
626 pinctrl-0 = <&spi0_bus>;
627 status = "disabled";
628 };
630 spi_1: spi@13930000 {
631 compatible = "samsung,exynos4210-spi";
632 reg = <0x13930000 0x100>;
633 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
634 dmas = <&pdma1 7>, <&pdma1 6>;
635 dma-names = "tx", "rx";
636 #address-cells = <1>;
637 #size-cells = <0>;
638 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
639 clock-names = "spi", "spi_busclk0";
640 pinctrl-names = "default";
641 pinctrl-0 = <&spi1_bus>;
642 status = "disabled";
643 };
645 spi_2: spi@13940000 {
646 compatible = "samsung,exynos4210-spi";
647 reg = <0x13940000 0x100>;
648 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
649 dmas = <&pdma0 9>, <&pdma0 8>;
650 dma-names = "tx", "rx";
651 #address-cells = <1>;
652 #size-cells = <0>;
653 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
654 clock-names = "spi", "spi_busclk0";
655 pinctrl-names = "default";
656 pinctrl-0 = <&spi2_bus>;
657 status = "disabled";
658 };
660 pwm: pwm@139D0000 {
661 compatible = "samsung,exynos4210-pwm";
662 reg = <0x139D0000 0x1000>;
663 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
664 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
665 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
666 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
667 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
668 clocks = <&clock CLK_PWM>;
669 clock-names = "timers";
670 #pwm-cells = <3>;
671 status = "disabled";
672 };
674 amba {
675 #address-cells = <1>;
676 #size-cells = <1>;
677 compatible = "simple-bus";
678 interrupt-parent = <&gic>;
679 ranges;
681 pdma0: pdma@12680000 {
682 compatible = "arm,pl330", "arm,primecell";
683 reg = <0x12680000 0x1000>;
684 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
685 clocks = <&clock CLK_PDMA0>;
686 clock-names = "apb_pclk";
687 #dma-cells = <1>;
688 #dma-channels = <8>;
689 #dma-requests = <32>;
690 };
692 pdma1: pdma@12690000 {
693 compatible = "arm,pl330", "arm,primecell";
694 reg = <0x12690000 0x1000>;
695 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
696 clocks = <&clock CLK_PDMA1>;
697 clock-names = "apb_pclk";
698 #dma-cells = <1>;
699 #dma-channels = <8>;
700 #dma-requests = <32>;
701 };
703 mdma1: mdma@12850000 {
704 compatible = "arm,pl330", "arm,primecell";
705 reg = <0x12850000 0x1000>;
706 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
707 clocks = <&clock CLK_MDMA>;
708 clock-names = "apb_pclk";
709 #dma-cells = <1>;
710 #dma-channels = <8>;
711 #dma-requests = <1>;
712 };
713 };
715 fimd: fimd@11c00000 {
716 compatible = "samsung,exynos4210-fimd";
717 interrupt-parent = <&combiner>;
718 reg = <0x11c00000 0x20000>;
719 interrupt-names = "fifo", "vsync", "lcd_sys";
720 interrupts = <11 0>, <11 1>, <11 2>;
721 clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;
722 clock-names = "sclk_fimd", "fimd";
723 power-domains = <&pd_lcd0>;
724 iommus = <&sysmmu_fimd0>;
725 samsung,sysreg = <&sys_reg>;
726 status = "disabled";
727 };
729 tmu: tmu@100C0000 {
730 #include "exynos4412-tmu-sensor-conf.dtsi"
731 };
733 jpeg_codec: jpeg-codec@11840000 {
734 compatible = "samsung,exynos4210-jpeg";
735 reg = <0x11840000 0x1000>;
736 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
737 clocks = <&clock CLK_JPEG>;
738 clock-names = "jpeg";
739 power-domains = <&pd_cam>;
740 iommus = <&sysmmu_jpeg>;
741 };
743 rotator: rotator@12810000 {
744 compatible = "samsung,exynos4210-rotator";
745 reg = <0x12810000 0x64>;
746 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
747 clocks = <&clock CLK_ROTATOR>;
748 clock-names = "rotator";
749 iommus = <&sysmmu_rotator>;
750 };
752 hdmi: hdmi@12D00000 {
753 compatible = "samsung,exynos4210-hdmi";
754 reg = <0x12D00000 0x70000>;
755 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
756 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy",
757 "mout_hdmi";
758 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
759 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
760 <&clock CLK_MOUT_HDMI>;
761 phy = <&hdmi_i2c_phy>;
762 power-domains = <&pd_tv>;
763 samsung,syscon-phandle = <&pmu_system_controller>;
764 status = "disabled";
765 };
767 hdmicec: cec@100B0000 {
768 compatible = "samsung,s5p-cec";
769 reg = <0x100B0000 0x200>;
770 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
771 clocks = <&clock CLK_HDMI_CEC>;
772 clock-names = "hdmicec";
773 samsung,syscon-phandle = <&pmu_system_controller>;
774 pinctrl-names = "default";
775 pinctrl-0 = <&hdmi_cec>;
776 status = "disabled";
777 };
779 mixer: mixer@12C10000 {
780 compatible = "samsung,exynos4210-mixer";
781 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
782 reg = <0x12C10000 0x2100>, <0x12c00000 0x300>;
783 power-domains = <&pd_tv>;
784 iommus = <&sysmmu_tv>;
785 status = "disabled";
786 };
788 ppmu_dmc0: ppmu_dmc0@106a0000 {
789 compatible = "samsung,exynos-ppmu";
790 reg = <0x106a0000 0x2000>;
791 clocks = <&clock CLK_PPMUDMC0>;
792 clock-names = "ppmu";
793 status = "disabled";
794 };
796 ppmu_dmc1: ppmu_dmc1@106b0000 {
797 compatible = "samsung,exynos-ppmu";
798 reg = <0x106b0000 0x2000>;
799 clocks = <&clock CLK_PPMUDMC1>;
800 clock-names = "ppmu";
801 status = "disabled";
802 };
804 ppmu_cpu: ppmu_cpu@106c0000 {
805 compatible = "samsung,exynos-ppmu";
806 reg = <0x106c0000 0x2000>;
807 clocks = <&clock CLK_PPMUCPU>;
808 clock-names = "ppmu";
809 status = "disabled";
810 };
812 ppmu_acp: ppmu_acp@10ae0000 {
813 compatible = "samsung,exynos-ppmu";
814 reg = <0x106e0000 0x2000>;
815 status = "disabled";
816 };
818 ppmu_rightbus: ppmu_rightbus@112a0000 {
819 compatible = "samsung,exynos-ppmu";
820 reg = <0x112a0000 0x2000>;
821 clocks = <&clock CLK_PPMURIGHT>;
822 clock-names = "ppmu";
823 status = "disabled";
824 };
826 ppmu_leftbus: ppmu_leftbus0@116a0000 {
827 compatible = "samsung,exynos-ppmu";
828 reg = <0x116a0000 0x2000>;
829 clocks = <&clock CLK_PPMULEFT>;
830 clock-names = "ppmu";
831 status = "disabled";
832 };
834 ppmu_camif: ppmu_camif@11ac0000 {
835 compatible = "samsung,exynos-ppmu";
836 reg = <0x11ac0000 0x2000>;
837 clocks = <&clock CLK_PPMUCAMIF>;
838 clock-names = "ppmu";
839 status = "disabled";
840 };
842 ppmu_lcd0: ppmu_lcd0@11e40000 {
843 compatible = "samsung,exynos-ppmu";
844 reg = <0x11e40000 0x2000>;
845 clocks = <&clock CLK_PPMULCD0>;
846 clock-names = "ppmu";
847 status = "disabled";
848 };
850 ppmu_fsys: ppmu_g3d@12630000 {
851 compatible = "samsung,exynos-ppmu";
852 reg = <0x12630000 0x2000>;
853 status = "disabled";
854 };
856 ppmu_image: ppmu_image@12aa0000 {
857 compatible = "samsung,exynos-ppmu";
858 reg = <0x12aa0000 0x2000>;
859 clocks = <&clock CLK_PPMUIMAGE>;
860 clock-names = "ppmu";
861 status = "disabled";
862 };
864 ppmu_tv: ppmu_tv@12e40000 {
865 compatible = "samsung,exynos-ppmu";
866 reg = <0x12e40000 0x2000>;
867 clocks = <&clock CLK_PPMUTV>;
868 clock-names = "ppmu";
869 status = "disabled";
870 };
872 ppmu_g3d: ppmu_g3d@13220000 {
873 compatible = "samsung,exynos-ppmu";
874 reg = <0x13220000 0x2000>;
875 clocks = <&clock CLK_PPMUG3D>;
876 clock-names = "ppmu";
877 status = "disabled";
878 };
880 ppmu_mfc_left: ppmu_mfc_left@13660000 {
881 compatible = "samsung,exynos-ppmu";
882 reg = <0x13660000 0x2000>;
883 clocks = <&clock CLK_PPMUMFC_L>;
884 clock-names = "ppmu";
885 status = "disabled";
886 };
888 ppmu_mfc_right: ppmu_mfc_right@13670000 {
889 compatible = "samsung,exynos-ppmu";
890 reg = <0x13670000 0x2000>;
891 clocks = <&clock CLK_PPMUMFC_R>;
892 clock-names = "ppmu";
893 status = "disabled";
894 };
896 sysmmu_mfc_l: sysmmu@13620000 {
897 compatible = "samsung,exynos-sysmmu";
898 reg = <0x13620000 0x1000>;
899 interrupt-parent = <&combiner>;
900 interrupts = <5 5>;
901 clock-names = "sysmmu", "master";
902 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
903 power-domains = <&pd_mfc>;
904 #iommu-cells = <0>;
905 };
907 sysmmu_mfc_r: sysmmu@13630000 {
908 compatible = "samsung,exynos-sysmmu";
909 reg = <0x13630000 0x1000>;
910 interrupt-parent = <&combiner>;
911 interrupts = <5 6>;
912 clock-names = "sysmmu", "master";
913 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
914 power-domains = <&pd_mfc>;
915 #iommu-cells = <0>;
916 };
918 sysmmu_tv: sysmmu@12E20000 {
919 compatible = "samsung,exynos-sysmmu";
920 reg = <0x12E20000 0x1000>;
921 interrupt-parent = <&combiner>;
922 interrupts = <5 4>;
923 clock-names = "sysmmu", "master";
924 clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
925 power-domains = <&pd_tv>;
926 #iommu-cells = <0>;
927 };
929 sysmmu_fimc0: sysmmu@11A20000 {
930 compatible = "samsung,exynos-sysmmu";
931 reg = <0x11A20000 0x1000>;
932 interrupt-parent = <&combiner>;
933 interrupts = <4 2>;
934 clock-names = "sysmmu", "master";
935 clocks = <&clock CLK_SMMU_FIMC0>, <&clock CLK_FIMC0>;
936 power-domains = <&pd_cam>;
937 #iommu-cells = <0>;
938 };
940 sysmmu_fimc1: sysmmu@11A30000 {
941 compatible = "samsung,exynos-sysmmu";
942 reg = <0x11A30000 0x1000>;
943 interrupt-parent = <&combiner>;
944 interrupts = <4 3>;
945 clock-names = "sysmmu", "master";
946 clocks = <&clock CLK_SMMU_FIMC1>, <&clock CLK_FIMC1>;
947 power-domains = <&pd_cam>;
948 #iommu-cells = <0>;
949 };
951 sysmmu_fimc2: sysmmu@11A40000 {
952 compatible = "samsung,exynos-sysmmu";
953 reg = <0x11A40000 0x1000>;
954 interrupt-parent = <&combiner>;
955 interrupts = <4 4>;
956 clock-names = "sysmmu", "master";
957 clocks = <&clock CLK_SMMU_FIMC2>, <&clock CLK_FIMC2>;
958 power-domains = <&pd_cam>;
959 #iommu-cells = <0>;
960 };
962 sysmmu_fimc3: sysmmu@11A50000 {
963 compatible = "samsung,exynos-sysmmu";
964 reg = <0x11A50000 0x1000>;
965 interrupt-parent = <&combiner>;
966 interrupts = <4 5>;
967 clock-names = "sysmmu", "master";
968 clocks = <&clock CLK_SMMU_FIMC3>, <&clock CLK_FIMC3>;
969 power-domains = <&pd_cam>;
970 #iommu-cells = <0>;
971 };
973 sysmmu_jpeg: sysmmu@11A60000 {
974 compatible = "samsung,exynos-sysmmu";
975 reg = <0x11A60000 0x1000>;
976 interrupt-parent = <&combiner>;
977 interrupts = <4 6>;
978 clock-names = "sysmmu", "master";
979 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
980 power-domains = <&pd_cam>;
981 #iommu-cells = <0>;
982 };
984 sysmmu_rotator: sysmmu@12A30000 {
985 compatible = "samsung,exynos-sysmmu";
986 reg = <0x12A30000 0x1000>;
987 interrupt-parent = <&combiner>;
988 interrupts = <5 0>;
989 clock-names = "sysmmu", "master";
990 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
991 #iommu-cells = <0>;
992 };
994 sysmmu_fimd0: sysmmu@11E20000 {
995 compatible = "samsung,exynos-sysmmu";
996 reg = <0x11E20000 0x1000>;
997 interrupt-parent = <&combiner>;
998 interrupts = <5 2>;
999 clock-names = "sysmmu", "master";
1000 clocks = <&clock CLK_SMMU_FIMD0>, <&clock CLK_FIMD0>;
1001 power-domains = <&pd_lcd0>;
1002 #iommu-cells = <0>;
1003 };
1005 sss: sss@10830000 {
1006 compatible = "samsung,exynos4210-secss";
1007 reg = <0x10830000 0x300>;
1008 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1009 clocks = <&clock CLK_SSS>;
1010 clock-names = "secss";
1011 };
1013 prng: rng@10830400 {
1014 compatible = "samsung,exynos4-rng";
1015 reg = <0x10830400 0x200>;
1016 clocks = <&clock CLK_SSS>;
1017 clock-names = "secss";
1018 };
1019 };