arch/arm/boot/dts/exynos5422-cpus.dtsi

   1 /*
   2  * SAMSUNG EXYNOS5422 SoC cpu device tree source
   3  *
   4  * Copyright (c) 2015 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * This file provides desired ordering for Exynos5422: CPU[0123] being the A7.
   8  *
   9  * The Exynos5420, 5422 and 5800 actually share the same CPU configuration
  10  * but particular boards choose different booting order.
  11  *
  12  * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
  13  * booting cluster (big or LITTLE) is chosen by IROM code by reading
  14  * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
  15  * from the LITTLE: Cortex-A7.
  16  *
  17  * This program is free software; you can redistribute it and/or modify
  18  * it under the terms of the GNU General Public License version 2 as
  19  * published by the Free Software Foundation.
  20  */
  21
  22 / {
  23         cpus {
  24                 #address-cells = <1>;
  25                 #size-cells = <0>;
  26
  27                 cpu0: cpu@100 {
  28                         device_type = "cpu";
  29                         compatible = "arm,cortex-a7";
  30                         reg = <0x100>;
  31                         clocks = <&clock CLK_KFC_CLK>;
  32                         clock-frequency = <1000000000>;
  33                         cci-control-port = <&cci_control0>;
  34                         operating-points-v2 = <&cluster_a7_opp_table>;
  35                         cooling-min-level = <0>;
  36                         cooling-max-level = <11>;
  37                         #cooling-cells = <2>; /* min followed by max */
  38                 };
  39
  40                 cpu1: cpu@101 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a7";
  43                         reg = <0x101>;
  44                         clock-frequency = <1000000000>;
  45                         cci-control-port = <&cci_control0>;
  46                         operating-points-v2 = <&cluster_a7_opp_table>;
  47                         cooling-min-level = <0>;
  48                         cooling-max-level = <11>;
  49                         #cooling-cells = <2>; /* min followed by max */
  50                 };
  51
  52                 cpu2: cpu@102 {
  53                         device_type = "cpu";
  54                         compatible = "arm,cortex-a7";
  55                         reg = <0x102>;
  56                         clock-frequency = <1000000000>;
  57                         cci-control-port = <&cci_control0>;
  58                         operating-points-v2 = <&cluster_a7_opp_table>;
  59                         cooling-min-level = <0>;
  60                         cooling-max-level = <11>;
  61                         #cooling-cells = <2>; /* min followed by max */
  62                 };
  63
  64                 cpu3: cpu@103 {
  65                         device_type = "cpu";
  66                         compatible = "arm,cortex-a7";
  67                         reg = <0x103>;
  68                         clock-frequency = <1000000000>;
  69                         cci-control-port = <&cci_control0>;
  70                         operating-points-v2 = <&cluster_a7_opp_table>;
  71                         cooling-min-level = <0>;
  72                         cooling-max-level = <11>;
  73                         #cooling-cells = <2>; /* min followed by max */
  74                 };
  75
  76                 cpu4: cpu@0 {
  77                         device_type = "cpu";
  78                         compatible = "arm,cortex-a15";
  79                         clocks = <&clock CLK_ARM_CLK>;
  80                         reg = <0x0>;
  81                         clock-frequency = <1800000000>;
  82                         cci-control-port = <&cci_control1>;
  83                         operating-points-v2 = <&cluster_a15_opp_table>;
  84                         cooling-min-level = <0>;
  85                         cooling-max-level = <15>;
  86                         #cooling-cells = <2>; /* min followed by max */
  87                 };
  88
  89                 cpu5: cpu@1 {
  90                         device_type = "cpu";
  91                         compatible = "arm,cortex-a15";
  92                         reg = <0x1>;
  93                         clock-frequency = <1800000000>;
  94                         cci-control-port = <&cci_control1>;
  95                         operating-points-v2 = <&cluster_a15_opp_table>;
  96                         cooling-min-level = <0>;
  97                         cooling-max-level = <15>;
  98                         #cooling-cells = <2>; /* min followed by max */
  99                 };
 100
 101                 cpu6: cpu@2 {
 102                         device_type = "cpu";
 103                         compatible = "arm,cortex-a15";
 104                         reg = <0x2>;
 105                         clock-frequency = <1800000000>;
 106                         cci-control-port = <&cci_control1>;
 107                         operating-points-v2 = <&cluster_a15_opp_table>;
 108                         cooling-min-level = <0>;
 109                         cooling-max-level = <15>;
 110                         #cooling-cells = <2>; /* min followed by max */
 111                 };
 112
 113                 cpu7: cpu@3 {
 114                         device_type = "cpu";
 115                         compatible = "arm,cortex-a15";
 116                         reg = <0x3>;
 117                         clock-frequency = <1800000000>;
 118                         cci-control-port = <&cci_control1>;
 119                         operating-points-v2 = <&cluster_a15_opp_table>;
 120                         cooling-min-level = <0>;
 121                         cooling-max-level = <15>;
 122                         #cooling-cells = <2>; /* min followed by max */
 123                 };
 124         };
 125 };