| blob | 6c712a97e1fef042b00c8fe55d406e78285b973e |
1 /*
2 * Copyright (c) 2013-2014 Linaro Ltd.
3 * Copyright (c) 2013-2014 Hisilicon Limited.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
10 #include <dt-bindings/clock/hix5hd2-clock.h>
12 / {
13 #address-cells = <1>;
14 #size-cells = <1>;
16 aliases {
17 serial0 = &uart0;
18 };
20 gic: interrupt-controller@f8a01000 {
21 compatible = "arm,cortex-a9-gic";
22 #interrupt-cells = <3>;
23 #address-cells = <0>;
24 interrupt-controller;
25 /* gic dist base, gic cpu base */
26 reg = <0xf8a01000 0x1000>, <0xf8a00100 0x100>;
27 };
29 soc {
30 #address-cells = <1>;
31 #size-cells = <1>;
32 compatible = "simple-bus";
33 interrupt-parent = <&gic>;
34 ranges = <0 0xf8000000 0x8000000>;
36 amba {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "simple-bus";
40 ranges;
42 timer0: timer@00002000 {
43 compatible = "arm,sp804", "arm,primecell";
44 reg = <0x00002000 0x1000>;
45 /* timer00 & timer01 */
46 interrupts = <0 24 4>;
47 clocks = <&clock HIX5HD2_FIXED_24M>;
48 status = "disabled";
49 };
51 timer1: timer@00a29000 {
52 /*
53 * Only used in NORMAL state, not available ins
54 * SLOW or DOZE state.
55 * The rate is fixed in 24MHz.
56 */
57 compatible = "arm,sp804", "arm,primecell";
58 reg = <0x00a29000 0x1000>;
59 /* timer10 & timer11 */
60 interrupts = <0 25 4>;
61 clocks = <&clock HIX5HD2_FIXED_24M>;
62 status = "disabled";
63 };
65 timer2: timer@00a2a000 {
66 compatible = "arm,sp804", "arm,primecell";
67 reg = <0x00a2a000 0x1000>;
68 /* timer20 & timer21 */
69 interrupts = <0 26 4>;
70 clocks = <&clock HIX5HD2_FIXED_24M>;
71 status = "disabled";
72 };
74 timer3: timer@00a2b000 {
75 compatible = "arm,sp804", "arm,primecell";
76 reg = <0x00a2b000 0x1000>;
77 /* timer30 & timer31 */
78 interrupts = <0 27 4>;
79 clocks = <&clock HIX5HD2_FIXED_24M>;
80 status = "disabled";
81 };
83 timer4: timer@00a81000 {
84 compatible = "arm,sp804", "arm,primecell";
85 reg = <0x00a81000 0x1000>;
86 /* timer30 & timer31 */
87 interrupts = <0 28 4>;
88 clocks = <&clock HIX5HD2_FIXED_24M>;
89 status = "disabled";
90 };
92 uart0: uart@00b00000 {
93 compatible = "arm,pl011", "arm,primecell";
94 reg = <0x00b00000 0x1000>;
95 interrupts = <0 49 4>;
96 clocks = <&clock HIX5HD2_FIXED_83M>;
97 clock-names = "apb_pclk";
98 status = "disabled";
99 };
101 uart1: uart@00006000 {
102 compatible = "arm,pl011", "arm,primecell";
103 reg = <0x00006000 0x1000>;
104 interrupts = <0 50 4>;
105 clocks = <&clock HIX5HD2_FIXED_83M>;
106 clock-names = "apb_pclk";
107 status = "disabled";
108 };
110 uart2: uart@00b02000 {
111 compatible = "arm,pl011", "arm,primecell";
112 reg = <0x00b02000 0x1000>;
113 interrupts = <0 51 4>;
114 clocks = <&clock HIX5HD2_FIXED_83M>;
115 clock-names = "apb_pclk";
116 status = "disabled";
117 };
119 uart3: uart@00b03000 {
120 compatible = "arm,pl011", "arm,primecell";
121 reg = <0x00b03000 0x1000>;
122 interrupts = <0 52 4>;
123 clocks = <&clock HIX5HD2_FIXED_83M>;
124 clock-names = "apb_pclk";
125 status = "disabled";
126 };
128 uart4: uart@00b04000 {
129 compatible = "arm,pl011", "arm,primecell";
130 reg = <0xb04000 0x1000>;
131 interrupts = <0 53 4>;
132 clocks = <&clock HIX5HD2_FIXED_83M>;
133 clock-names = "apb_pclk";
134 status = "disabled";
135 };
137 gpio0: gpio@b20000 {
138 compatible = "arm,pl061", "arm,primecell";
139 reg = <0xb20000 0x1000>;
140 interrupts = <0 108 0x4>;
141 gpio-controller;
142 #gpio-cells = <2>;
143 clocks = <&clock HIX5HD2_FIXED_100M>;
144 clock-names = "apb_pclk";
145 interrupt-controller;
146 #interrupt-cells = <2>;
147 status = "disabled";
148 };
150 gpio1: gpio@b21000 {
151 compatible = "arm,pl061", "arm,primecell";
152 reg = <0xb21000 0x1000>;
153 interrupts = <0 109 0x4>;
154 gpio-controller;
155 #gpio-cells = <2>;
156 clocks = <&clock HIX5HD2_FIXED_100M>;
157 clock-names = "apb_pclk";
158 interrupt-controller;
159 #interrupt-cells = <2>;
160 status = "disabled";
161 };
163 gpio2: gpio@b22000 {
164 compatible = "arm,pl061", "arm,primecell";
165 reg = <0xb22000 0x1000>;
166 interrupts = <0 110 0x4>;
167 gpio-controller;
168 #gpio-cells = <2>;
169 clocks = <&clock HIX5HD2_FIXED_100M>;
170 clock-names = "apb_pclk";
171 interrupt-controller;
172 #interrupt-cells = <2>;
173 status = "disabled";
174 };
176 gpio3: gpio@b23000 {
177 compatible = "arm,pl061", "arm,primecell";
178 reg = <0xb23000 0x1000>;
179 interrupts = <0 111 0x4>;
180 gpio-controller;
181 #gpio-cells = <2>;
182 clocks = <&clock HIX5HD2_FIXED_100M>;
183 clock-names = "apb_pclk";
184 interrupt-controller;
185 #interrupt-cells = <2>;
186 status = "disabled";
187 };
189 gpio4: gpio@b24000 {
190 compatible = "arm,pl061", "arm,primecell";
191 reg = <0xb24000 0x1000>;
192 interrupts = <0 112 0x4>;
193 gpio-controller;
194 #gpio-cells = <2>;
195 clocks = <&clock HIX5HD2_FIXED_100M>;
196 clock-names = "apb_pclk";
197 interrupt-controller;
198 #interrupt-cells = <2>;
199 status = "disabled";
200 };
202 gpio5: gpio@004000 {
203 compatible = "arm,pl061", "arm,primecell";
204 reg = <0x004000 0x1000>;
205 interrupts = <0 113 0x4>;
206 gpio-controller;
207 #gpio-cells = <2>;
208 clocks = <&clock HIX5HD2_FIXED_100M>;
209 clock-names = "apb_pclk";
210 interrupt-controller;
211 #interrupt-cells = <2>;
212 status = "disabled";
213 };
215 gpio6: gpio@b26000 {
216 compatible = "arm,pl061", "arm,primecell";
217 reg = <0xb26000 0x1000>;
218 interrupts = <0 114 0x4>;
219 gpio-controller;
220 #gpio-cells = <2>;
221 clocks = <&clock HIX5HD2_FIXED_100M>;
222 clock-names = "apb_pclk";
223 interrupt-controller;
224 #interrupt-cells = <2>;
225 status = "disabled";
226 };
228 gpio7: gpio@b27000 {
229 compatible = "arm,pl061", "arm,primecell";
230 reg = <0xb27000 0x1000>;
231 interrupts = <0 115 0x4>;
232 gpio-controller;
233 #gpio-cells = <2>;
234 clocks = <&clock HIX5HD2_FIXED_100M>;
235 clock-names = "apb_pclk";
236 interrupt-controller;
237 #interrupt-cells = <2>;
238 status = "disabled";
239 };
241 gpio8: gpio@b28000 {
242 compatible = "arm,pl061", "arm,primecell";
243 reg = <0xb28000 0x1000>;
244 interrupts = <0 116 0x4>;
245 gpio-controller;
246 #gpio-cells = <2>;
247 clocks = <&clock HIX5HD2_FIXED_100M>;
248 clock-names = "apb_pclk";
249 interrupt-controller;
250 #interrupt-cells = <2>;
251 status = "disabled";
252 };
254 gpio9: gpio@b29000 {
255 compatible = "arm,pl061", "arm,primecell";
256 reg = <0xb29000 0x1000>;
257 interrupts = <0 117 0x4>;
258 gpio-controller;
259 #gpio-cells = <2>;
260 clocks = <&clock HIX5HD2_FIXED_100M>;
261 clock-names = "apb_pclk";
262 interrupt-controller;
263 #interrupt-cells = <2>;
264 status = "disabled";
265 };
267 gpio10: gpio@b2a000 {
268 compatible = "arm,pl061", "arm,primecell";
269 reg = <0xb2a000 0x1000>;
270 interrupts = <0 118 0x4>;
271 gpio-controller;
272 #gpio-cells = <2>;
273 clocks = <&clock HIX5HD2_FIXED_100M>;
274 clock-names = "apb_pclk";
275 interrupt-controller;
276 #interrupt-cells = <2>;
277 status = "disabled";
278 };
280 gpio11: gpio@b2b000 {
281 compatible = "arm,pl061", "arm,primecell";
282 reg = <0xb2b000 0x1000>;
283 interrupts = <0 119 0x4>;
284 gpio-controller;
285 #gpio-cells = <2>;
286 clocks = <&clock HIX5HD2_FIXED_100M>;
287 clock-names = "apb_pclk";
288 interrupt-controller;
289 #interrupt-cells = <2>;
290 status = "disabled";
291 };
293 gpio12: gpio@b2c000 {
294 compatible = "arm,pl061", "arm,primecell";
295 reg = <0xb2c000 0x1000>;
296 interrupts = <0 120 0x4>;
297 gpio-controller;
298 #gpio-cells = <2>;
299 clocks = <&clock HIX5HD2_FIXED_100M>;
300 clock-names = "apb_pclk";
301 interrupt-controller;
302 #interrupt-cells = <2>;
303 status = "disabled";
304 };
306 gpio13: gpio@b2d000 {
307 compatible = "arm,pl061", "arm,primecell";
308 reg = <0xb2d000 0x1000>;
309 interrupts = <0 121 0x4>;
310 gpio-controller;
311 #gpio-cells = <2>;
312 clocks = <&clock HIX5HD2_FIXED_100M>;
313 clock-names = "apb_pclk";
314 interrupt-controller;
315 #interrupt-cells = <2>;
316 status = "disabled";
317 };
319 gpio14: gpio@b2e000 {
320 compatible = "arm,pl061", "arm,primecell";
321 reg = <0xb2e000 0x1000>;
322 interrupts = <0 122 0x4>;
323 gpio-controller;
324 #gpio-cells = <2>;
325 clocks = <&clock HIX5HD2_FIXED_100M>;
326 clock-names = "apb_pclk";
327 interrupt-controller;
328 #interrupt-cells = <2>;
329 status = "disabled";
330 };
332 gpio15: gpio@b2f000 {
333 compatible = "arm,pl061", "arm,primecell";
334 reg = <0xb2f000 0x1000>;
335 interrupts = <0 123 0x4>;
336 gpio-controller;
337 #gpio-cells = <2>;
338 clocks = <&clock HIX5HD2_FIXED_100M>;
339 clock-names = "apb_pclk";
340 interrupt-controller;
341 #interrupt-cells = <2>;
342 status = "disabled";
343 };
345 gpio16: gpio@b30000 {
346 compatible = "arm,pl061", "arm,primecell";
347 reg = <0xb30000 0x1000>;
348 interrupts = <0 124 0x4>;
349 gpio-controller;
350 #gpio-cells = <2>;
351 clocks = <&clock HIX5HD2_FIXED_100M>;
352 clock-names = "apb_pclk";
353 interrupt-controller;
354 #interrupt-cells = <2>;
355 status = "disabled";
356 };
358 gpio17: gpio@b31000 {
359 compatible = "arm,pl061", "arm,primecell";
360 reg = <0xb31000 0x1000>;
361 interrupts = <0 125 0x4>;
362 gpio-controller;
363 #gpio-cells = <2>;
364 clocks = <&clock HIX5HD2_FIXED_100M>;
365 clock-names = "apb_pclk";
366 interrupt-controller;
367 #interrupt-cells = <2>;
368 status = "disabled";
369 };
371 wdt0: watchdog@a2c000 {
372 compatible = "arm,sp805", "arm,primecell";
373 arm,primecell-periphid = <0x00141805>;
374 reg = <0xa2c000 0x1000>;
375 interrupts = <0 29 4>;
376 clocks = <&clock HIX5HD2_WDG0_RST>;
377 clock-names = "apb_pclk";
378 };
379 };
381 local_timer@00a00600 {
382 compatible = "arm,cortex-a9-twd-timer";
383 reg = <0x00a00600 0x20>;
384 interrupts = <1 13 0xf01>;
385 };
387 l2: l2-cache {
388 compatible = "arm,pl310-cache";
389 reg = <0x00a10000 0x100000>;
390 interrupts = <0 15 4>;
391 cache-unified;
392 cache-level = <2>;
393 };
395 sysctrl: system-controller@00000000 {
396 compatible = "hisilicon,sysctrl", "syscon";
397 reg = <0x00000000 0x1000>;
398 };
400 reboot {
401 compatible = "syscon-reboot";
402 regmap = <&sysctrl>;
403 offset = <0x4>;
404 mask = <0xdeadbeef>;
405 };
407 cpuctrl@00a22000 {
408 compatible = "hisilicon,cpuctrl";
409 #address-cells = <1>;
410 #size-cells = <1>;
411 reg = <0x00a22000 0x2000>;
412 ranges = <0 0x00a22000 0x2000>;
414 clock: clock@0 {
415 compatible = "hisilicon,hix5hd2-clock";
416 reg = <0 0x2000>;
417 #clock-cells = <1>;
418 };
419 };
421 /* unremovable emmc as mmcblk0 */
422 mmc: mmc@1830000 {
423 compatible = "snps,dw-mshc";
424 reg = <0x1830000 0x1000>;
425 interrupts = <0 35 4>;
426 clocks = <&clock HIX5HD2_MMC_CIU_RST>,
427 <&clock HIX5HD2_MMC_BIU_CLK>;
428 clock-names = "ciu", "biu";
429 };
431 sd: mmc@1820000 {
432 compatible = "snps,dw-mshc";
433 reg = <0x1820000 0x1000>;
434 interrupts = <0 34 4>;
435 clocks = <&clock HIX5HD2_SD_CIU_RST>,
436 <&clock HIX5HD2_SD_BIU_CLK>;
437 clock-names = "ciu","biu";
438 };
440 gmac0: ethernet@1840000 {
441 compatible = "hisilicon,hix5hd2-gmac", "hisilicon,hisi-gmac-v1";
442 reg = <0x1840000 0x1000>,<0x184300c 0x4>;
443 interrupts = <0 71 4>;
444 clocks = <&clock HIX5HD2_MAC0_CLK>;
445 clock-names = "mac_core";
446 status = "disabled";
447 };
449 gmac1: ethernet@1841000 {
450 compatible = "hisilicon,hix5hd2-gmac", "hisilicon,hisi-gmac-v1";
451 reg = <0x1841000 0x1000>,<0x1843010 0x4>;
452 interrupts = <0 72 4>;
453 clocks = <&clock HIX5HD2_MAC1_CLK>;
454 clock-names = "mac_core";
455 status = "disabled";
456 };
458 usb0: ehci@1890000 {
459 compatible = "generic-ehci";
460 reg = <0x1890000 0x1000>;
461 interrupts = <0 66 4>;
462 clocks = <&clock HIX5HD2_USB_CLK>;
463 };
465 usb1: ohci@1880000 {
466 compatible = "generic-ohci";
467 reg = <0x1880000 0x1000>;
468 interrupts = <0 67 4>;
469 clocks = <&clock HIX5HD2_USB_CLK>;
470 };
472 peripheral_ctrl: syscon@a20000 {
473 compatible = "syscon";
474 reg = <0xa20000 0x1000>;
475 };
477 sata_phy: phy@1900000 {
478 compatible = "hisilicon,hix5hd2-sata-phy";
479 reg = <0x1900000 0x10000>;
480 #phy-cells = <0>;
481 hisilicon,peripheral-syscon = <&peripheral_ctrl>;
482 hisilicon,power-reg = <0x8 10>;
483 };
485 ahci: sata@1900000 {
486 compatible = "hisilicon,hisi-ahci";
487 reg = <0x1900000 0x10000>;
488 interrupts = <0 70 4>;
489 clocks = <&clock HIX5HD2_SATA_CLK>;
490 };
492 ir: ir@001000 {
493 compatible = "hisilicon,hix5hd2-ir";
494 reg = <0x001000 0x1000>;
495 interrupts = <0 47 4>;
496 clocks = <&clock HIX5HD2_FIXED_24M>;
497 hisilicon,power-syscon = <&sysctrl>;
498 };
500 i2c0: i2c@b10000 {
501 compatible = "hisilicon,hix5hd2-i2c";
502 reg = <0xb10000 0x1000>;
503 interrupts = <0 38 4>;
504 clocks = <&clock HIX5HD2_I2C0_RST>;
505 #address-cells = <1>;
506 #size-cells = <0>;
507 status = "disabled";
508 };
510 i2c1: i2c@b11000 {
511 compatible = "hisilicon,hix5hd2-i2c";
512 reg = <0xb11000 0x1000>;
513 interrupts = <0 39 4>;
514 clocks = <&clock HIX5HD2_I2C1_RST>;
515 #address-cells = <1>;
516 #size-cells = <0>;
517 status = "disabled";
518 };
520 i2c2: i2c@b12000 {
521 compatible = "hisilicon,hix5hd2-i2c";
522 reg = <0xb12000 0x1000>;
523 interrupts = <0 40 4>;
524 clocks = <&clock HIX5HD2_I2C2_RST>;
525 #address-cells = <1>;
526 #size-cells = <0>;
527 status = "disabled";
528 };
530 i2c3: i2c@b13000 {
531 compatible = "hisilicon,hix5hd2-i2c";
532 reg = <0xb13000 0x1000>;
533 interrupts = <0 41 4>;
534 clocks = <&clock HIX5HD2_I2C3_RST>;
535 #address-cells = <1>;
536 #size-cells = <0>;
537 status = "disabled";
538 };
540 i2c4: i2c@b16000 {
541 compatible = "hisilicon,hix5hd2-i2c";
542 reg = <0xb16000 0x1000>;
543 interrupts = <0 43 4>;
544 clocks = <&clock HIX5HD2_I2C4_RST>;
545 #address-cells = <1>;
546 #size-cells = <0>;
547 status = "disabled";
548 };
550 i2c5: i2c@b17000 {
551 compatible = "hisilicon,hix5hd2-i2c";
552 reg = <0xb17000 0x1000>;
553 interrupts = <0 44 4>;
554 clocks = <&clock HIX5HD2_I2C5_RST>;
555 #address-cells = <1>;
556 #size-cells = <0>;
557 status = "disabled";
558 };
559 };
560 };