x86/mm/pat: Don't report PAT on CPUs that don't support it
[linux/fpc-iii.git] / arch / arm / boot / dts / imx25-eukrea-cpuimx25.dtsi
blobd6f27641c0ef290685ef4a9a72454cc3f1255c13
1 /*
2  * Copyright 2013 EukrĂ©a Electromatique <denis@eukrea.com>
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License
6  * as published by the Free Software Foundation; either version 2
7  * of the License, or (at your option) any later version.
8  * This program is distributed in the hope that it will be useful,
9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11  * GNU General Public License for more details.
12  */
14 #include "imx25.dtsi"
16 / {
17         model = "Eukrea CPUIMX25";
18         compatible = "eukrea,cpuimx25", "fsl,imx25";
20         memory {
21                 reg = <0x80000000 0x4000000>; /* 64M */
22         };
25 &fec {
26         phy-mode = "rmii";
27         pinctrl-names = "default";
28         pinctrl-0 = <&pinctrl_fec>;
29         status = "okay";
32 &i2c1 {
33         pinctrl-names = "default";
34         pinctrl-0 = <&pinctrl_i2c1>;
35         status = "okay";
37         pcf8563@51 {
38                 compatible = "nxp,pcf8563";
39                 reg = <0x51>;
40         };
43 &iomuxc {
44         imx25-eukrea-cpuimx25 {
45                 pinctrl_fec: fecgrp {
46                         fsl,pins = <
47                                 MX25_PAD_FEC_MDC__FEC_MDC               0x80000000
48                                 MX25_PAD_FEC_MDIO__FEC_MDIO             0x400001e0
49                                 MX25_PAD_FEC_TDATA0__FEC_TDATA0         0x80000000
50                                 MX25_PAD_FEC_TDATA1__FEC_TDATA1         0x80000000
51                                 MX25_PAD_FEC_TX_EN__FEC_TX_EN           0x80000000
52                                 MX25_PAD_FEC_RDATA0__FEC_RDATA0         0x80000000
53                                 MX25_PAD_FEC_RDATA1__FEC_RDATA1         0x80000000
54                                 MX25_PAD_FEC_RX_DV__FEC_RX_DV           0x80000000
55                                 MX25_PAD_FEC_TX_CLK__FEC_TX_CLK         0x1c0
56                         >;
57                 };
59                 pinctrl_i2c1: i2c1grp {
60                         fsl,pins = <
61                                 MX25_PAD_I2C1_CLK__I2C1_CLK             0x80000000
62                                 MX25_PAD_I2C1_DAT__I2C1_DAT             0x80000000
63                         >;
64                 };
65         };
68 &nfc {
69         nand-bus-width = <8>;
70         nand-ecc-mode = "hw";
71         nand-on-flash-bbt;
72         status = "okay";