arch/arm/boot/dts/imx6q-cm-fx6.dts

   1 /*
   2  * Copyright 2013 CompuLab Ltd.
   3  *
   4  * Author: Valentin Raevsky <valentin@compulab.co.il>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License
  13  *     version 2 as published by the Free Software Foundation.
  14  *
  15  *     This file is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 /dts-v1/;
  45 #include <dt-bindings/gpio/gpio.h>
  46 #include "imx6q.dtsi"
  47
  48 / {
  49         model = "CompuLab CM-FX6";
  50         compatible = "compulab,cm-fx6", "fsl,imx6q";
  51
  52         memory {
  53                 reg = <0x10000000 0x80000000>;
  54         };
  55
  56         leds {
  57                 compatible = "gpio-leds";
  58
  59                 heartbeat-led {
  60                         label = "Heartbeat";
  61                         gpios = <&gpio2 31 0>;
  62                         linux,default-trigger = "heartbeat";
  63                 };
  64         };
  65
  66         reg_pcie_power_on_gpio: regulator-pcie-power-on-gpio {
  67                 compatible = "regulator-fixed";
  68                 regulator-name = "regulator-pcie-power-on-gpio";
  69                 regulator-min-microvolt = <3300000>;
  70                 regulator-max-microvolt = <3300000>;
  71                 gpio = <&gpio2 24 GPIO_ACTIVE_HIGH>;
  72                 enable-active-high;
  73         };
  74
  75         reg_usb_h1_vbus: usb_h1_vbus {
  76                 compatible = "regulator-fixed";
  77                 regulator-name = "usb_h1_vbus";
  78                 regulator-min-microvolt = <5000000>;
  79                 regulator-max-microvolt = <5000000>;
  80                 gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
  81                 enable-active-high;
  82         };
  83
  84         reg_usb_otg_vbus: usb_otg_vbus {
  85                 compatible = "regulator-fixed";
  86                 regulator-name = "usb_otg_vbus";
  87                 regulator-min-microvolt = <5000000>;
  88                 regulator-max-microvolt = <5000000>;
  89                 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
  90                 enable-active-high;
  91         };
  92
  93         sound-spdif {
  94                 compatible = "fsl,imx-audio-spdif";
  95                 model = "imx-spdif";
  96                 spdif-controller = <&spdif>;
  97                 spdif-out;
  98                 spdif-in;
  99         };
 100 };
 101
 102 &cpu0 {
 103         /*
 104          * Although the imx6q fuse indicates that 1.2GHz operation is possible,
 105          * the module behaves unstable at this frequency. Hence, remove the
 106          * 1.2GHz operation point here.
 107          */
 108         operating-points = <
 109                 /* kHz  uV */
 110                 996000  1250000
 111                 852000  1250000
 112                 792000  1175000
 113                 396000  975000
 114         >;
 115         fsl,soc-operating-points = <
 116                 /* ARM kHz      SOC-PU uV */
 117                 996000          1250000
 118                 852000          1250000
 119                 792000          1175000
 120                 396000          1175000
 121         >;
 122 };
 123
 124 &ecspi1 {
 125         cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>, <&gpio3 19 GPIO_ACTIVE_HIGH>;
 126         pinctrl-names = "default";
 127         pinctrl-0 = <&pinctrl_ecspi1>;
 128         status = "okay";
 129
 130         m25p80@0 {
 131                 #address-cells = <1>;
 132                 #size-cells = <1>;
 133                 compatible = "st,m25p", "jedec,spi-nor";
 134                 spi-max-frequency = <20000000>;
 135                 reg = <0>;
 136         };
 137 };
 138
 139 &fec {
 140         pinctrl-names = "default";
 141         pinctrl-0 = <&pinctrl_enet>;
 142         phy-mode = "rgmii";
 143         status = "okay";
 144 };
 145
 146 &gpmi {
 147         pinctrl-names = "default";
 148         pinctrl-0 = <&pinctrl_gpmi_nand>;
 149         status = "okay";
 150 };
 151
 152 &i2c3 {
 153         pinctrl-names = "default";
 154         pinctrl-0 = <&pinctrl_i2c3>;
 155         status = "okay";
 156         clock-frequency = <100000>;
 157
 158         eeprom@50 {
 159                 compatible = "at24,24c02";
 160                 reg = <0x50>;
 161                 pagesize = <16>;
 162         };
 163 };
 164
 165 &iomuxc {
 166         pinctrl_ecspi1: ecspi1grp {
 167                 fsl,pins = <
 168                         MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
 169                         MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
 170                         MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
 171                         MX6QDL_PAD_EIM_EB2__GPIO2_IO30  0x100b1
 172                         MX6QDL_PAD_EIM_D19__GPIO3_IO19  0x100b1
 173                 >;
 174         };
 175
 176         pinctrl_enet: enetgrp {
 177                 fsl,pins = <
 178                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 179                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 180                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 181                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 182                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 183                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 184                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
 185                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
 186                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
 187                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
 188                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
 189                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
 190                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 191                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 192                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 193                 >;
 194         };
 195
 196         pinctrl_gpmi_nand: gpminandgrp {
 197                 fsl,pins = <
 198                         MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 199                         MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 200                         MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 201                         MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 202                         MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 203                         MX6QDL_PAD_NANDF_CS1__NAND_CE1_B        0xb0b1
 204                         MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 205                         MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 206                         MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 207                         MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 208                         MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 209                         MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 210                         MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 211                         MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 212                         MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 213                         MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 214                         MX6QDL_PAD_SD4_DAT0__NAND_DQS           0x00b1
 215                 >;
 216         };
 217
 218         pinctrl_i2c3: i2c3grp {
 219                 fsl,pins = <
 220                         MX6QDL_PAD_GPIO_3__I2C3_SCL     0x4001b8b1
 221                         MX6QDL_PAD_GPIO_6__I2C3_SDA     0x4001b8b1
 222                 >;
 223         };
 224
 225         pinctrl_pcie: pciegrp {
 226                 fsl,pins = <
 227                         MX6QDL_PAD_ENET_RXD1__GPIO1_IO26        0x1b0b1
 228                         MX6QDL_PAD_EIM_CS1__GPIO2_IO24  0x1b0b1
 229                 >;
 230         };
 231
 232         pinctrl_spdif: spdifgrp {
 233                 fsl,pins = <
 234                         MX6QDL_PAD_GPIO_16__SPDIF_IN  0x1b0b0
 235                         MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x1b0b0
 236                 >;
 237         };
 238
 239         pinctrl_uart4: uart4grp {
 240                 fsl,pins = <
 241                         MX6QDL_PAD_KEY_COL0__UART4_TX_DATA      0x1b0b1
 242                         MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA      0x1b0b1
 243                 >;
 244         };
 245
 246         pinctrl_usbh1: usbh1grp {
 247                 fsl,pins = <
 248                         MX6QDL_PAD_SD3_RST__GPIO7_IO08  0x1b0b1
 249                 >;
 250         };
 251
 252         pinctrl_usbotg: usbotggrp {
 253                 fsl,pins = <
 254                         MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID       0x17059
 255                         MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x130b0
 256                 >;
 257         };
 258 };
 259
 260 &pcie {
 261         pinctrl-names = "default";
 262         pinctrl-0 = <&pinctrl_pcie>;
 263         reset-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>;
 264         vdd-supply = <&reg_pcie_power_on_gpio>;
 265         status = "okay";
 266 };
 267
 268 &sata {
 269         status = "okay";
 270 };
 271
 272 &snvs_poweroff {
 273         status = "okay";
 274 };
 275
 276 &spdif {
 277         pinctrl-names = "default";
 278         pinctrl-0 = <&pinctrl_spdif>;
 279         status = "okay";
 280 };
 281
 282 &uart4 {
 283         pinctrl-names = "default";
 284         pinctrl-0 = <&pinctrl_uart4>;
 285         status = "okay";
 286 };
 287
 288 &usbh1 {
 289         vbus-supply = <&reg_usb_h1_vbus>;
 290         pinctrl-names = "default";
 291         pinctrl-0 = <&pinctrl_usbh1>;
 292         status = "okay";
 293 };
 294
 295 &usbotg {
 296         vbus-supply = <&reg_usb_otg_vbus>;
 297         pinctrl-names = "default";
 298         pinctrl-0 = <&pinctrl_usbotg>;
 299         dr_mode = "otg";
 300         status = "okay";
 301 };