arch/arm/boot/dts/imx6qdl-gw54xx.dtsi

   1 /*
   2  * Copyright 2013 Gateworks Corporation
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  */
  11
  12 #include <dt-bindings/gpio/gpio.h>
  13
  14 / {
  15         /* these are used by bootloader for disabling nodes */
  16         aliases {
  17                 ethernet1 = &eth1;
  18                 led0 = &led0;
  19                 led1 = &led1;
  20                 led2 = &led2;
  21                 nand = &gpmi;
  22                 ssi0 = &ssi1;
  23                 usb0 = &usbh1;
  24                 usb1 = &usbotg;
  25         };
  26
  27         chosen {
  28                 bootargs = "console=ttymxc1,115200";
  29         };
  30
  31         backlight {
  32                 compatible = "pwm-backlight";
  33                 pwms = <&pwm4 0 5000000>;
  34                 brightness-levels = <0 4 8 16 32 64 128 255>;
  35                 default-brightness-level = <7>;
  36         };
  37
  38         leds {
  39                 compatible = "gpio-leds";
  40                 pinctrl-names = "default";
  41                 pinctrl-0 = <&pinctrl_gpio_leds>;
  42
  43                 led0: user1 {
  44                         label = "user1";
  45                         gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
  46                         default-state = "on";
  47                         linux,default-trigger = "heartbeat";
  48                 };
  49
  50                 led1: user2 {
  51                         label = "user2";
  52                         gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
  53                         default-state = "off";
  54                 };
  55
  56                 led2: user3 {
  57                         label = "user3";
  58                         gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
  59                         default-state = "off";
  60                 };
  61         };
  62
  63         memory {
  64                 reg = <0x10000000 0x40000000>;
  65         };
  66
  67         pps {
  68                 compatible = "pps-gpio";
  69                 pinctrl-names = "default";
  70                 pinctrl-0 = <&pinctrl_pps>;
  71                 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
  72                 status = "okay";
  73         };
  74
  75         regulators {
  76                 compatible = "simple-bus";
  77                 #address-cells = <1>;
  78                 #size-cells = <0>;
  79
  80                 reg_1p0v: regulator@0 {
  81                         compatible = "regulator-fixed";
  82                         reg = <0>;
  83                         regulator-name = "1P0V";
  84                         regulator-min-microvolt = <1000000>;
  85                         regulator-max-microvolt = <1000000>;
  86                         regulator-always-on;
  87                 };
  88
  89                 reg_3p3v: regulator@1 {
  90                         compatible = "regulator-fixed";
  91                         reg = <1>;
  92                         regulator-name = "3P3V";
  93                         regulator-min-microvolt = <3300000>;
  94                         regulator-max-microvolt = <3300000>;
  95                         regulator-always-on;
  96                 };
  97
  98                 reg_usb_h1_vbus: regulator@2 {
  99                         compatible = "regulator-fixed";
 100                         reg = <2>;
 101                         regulator-name = "usb_h1_vbus";
 102                         regulator-min-microvolt = <5000000>;
 103                         regulator-max-microvolt = <5000000>;
 104                         regulator-always-on;
 105                 };
 106
 107                 reg_usb_otg_vbus: regulator@3 {
 108                         compatible = "regulator-fixed";
 109                         reg = <3>;
 110                         regulator-name = "usb_otg_vbus";
 111                         regulator-min-microvolt = <5000000>;
 112                         regulator-max-microvolt = <5000000>;
 113                         gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
 114                         enable-active-high;
 115                 };
 116         };
 117
 118         sound {
 119                 compatible = "fsl,imx6q-ventana-sgtl5000",
 120                              "fsl,imx-audio-sgtl5000";
 121                 model = "sgtl5000-audio";
 122                 ssi-controller = <&ssi1>;
 123                 audio-codec = <&codec>;
 124                 audio-routing =
 125                         "MIC_IN", "Mic Jack",
 126                         "Mic Jack", "Mic Bias",
 127                         "Headphone Jack", "HP_OUT";
 128                 mux-int-port = <1>;
 129                 mux-ext-port = <4>;
 130         };
 131 };
 132
 133 &audmux {
 134         pinctrl-names = "default";
 135         pinctrl-0 = <&pinctrl_audmux>; /* AUD4<->sgtl5000 */
 136         status = "okay";
 137 };
 138
 139 &can1 {
 140         pinctrl-names = "default";
 141         pinctrl-0 = <&pinctrl_flexcan1>;
 142         status = "okay";
 143 };
 144
 145 &clks {
 146         assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
 147                           <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
 148         assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
 149                                  <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
 150 };
 151
 152 &ecspi2 {
 153         cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
 154         pinctrl-names = "default";
 155         pinctrl-0 = <&pinctrl_ecspi2>;
 156         status = "okay";
 157 };
 158
 159 &fec {
 160         pinctrl-names = "default";
 161         pinctrl-0 = <&pinctrl_enet>;
 162         phy-mode = "rgmii-id";
 163         phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
 164         status = "okay";
 165 };
 166
 167 &gpmi {
 168         pinctrl-names = "default";
 169         pinctrl-0 = <&pinctrl_gpmi_nand>;
 170         status = "okay";
 171 };
 172
 173 &hdmi {
 174         ddc-i2c-bus = <&i2c3>;
 175         status = "okay";
 176 };
 177
 178 &i2c1 {
 179         clock-frequency = <100000>;
 180         pinctrl-names = "default";
 181         pinctrl-0 = <&pinctrl_i2c1>;
 182         status = "okay";
 183
 184         eeprom1: eeprom@50 {
 185                 compatible = "atmel,24c02";
 186                 reg = <0x50>;
 187                 pagesize = <16>;
 188         };
 189
 190         eeprom2: eeprom@51 {
 191                 compatible = "atmel,24c02";
 192                 reg = <0x51>;
 193                 pagesize = <16>;
 194         };
 195
 196         eeprom3: eeprom@52 {
 197                 compatible = "atmel,24c02";
 198                 reg = <0x52>;
 199                 pagesize = <16>;
 200         };
 201
 202         eeprom4: eeprom@53 {
 203                 compatible = "atmel,24c02";
 204                 reg = <0x53>;
 205                 pagesize = <16>;
 206         };
 207
 208         gpio: pca9555@23 {
 209                 compatible = "nxp,pca9555";
 210                 reg = <0x23>;
 211                 gpio-controller;
 212                 #gpio-cells = <2>;
 213         };
 214
 215         rtc: ds1672@68 {
 216                 compatible = "dallas,ds1672";
 217                 reg = <0x68>;
 218         };
 219 };
 220
 221 &i2c2 {
 222         clock-frequency = <100000>;
 223         pinctrl-names = "default";
 224         pinctrl-0 = <&pinctrl_i2c2>;
 225         status = "okay";
 226
 227         pmic: pfuze100@08 {
 228                 compatible = "fsl,pfuze100";
 229                 reg = <0x08>;
 230
 231                 regulators {
 232                         sw1a_reg: sw1ab {
 233                                 regulator-min-microvolt = <300000>;
 234                                 regulator-max-microvolt = <1875000>;
 235                                 regulator-boot-on;
 236                                 regulator-always-on;
 237                                 regulator-ramp-delay = <6250>;
 238                         };
 239
 240                         sw1c_reg: sw1c {
 241                                 regulator-min-microvolt = <300000>;
 242                                 regulator-max-microvolt = <1875000>;
 243                                 regulator-boot-on;
 244                                 regulator-always-on;
 245                                 regulator-ramp-delay = <6250>;
 246                         };
 247
 248                         sw2_reg: sw2 {
 249                                 regulator-min-microvolt = <800000>;
 250                                 regulator-max-microvolt = <3950000>;
 251                                 regulator-boot-on;
 252                                 regulator-always-on;
 253                         };
 254
 255                         sw3a_reg: sw3a {
 256                                 regulator-min-microvolt = <400000>;
 257                                 regulator-max-microvolt = <1975000>;
 258                                 regulator-boot-on;
 259                                 regulator-always-on;
 260                         };
 261
 262                         sw3b_reg: sw3b {
 263                                 regulator-min-microvolt = <400000>;
 264                                 regulator-max-microvolt = <1975000>;
 265                                 regulator-boot-on;
 266                                 regulator-always-on;
 267                         };
 268
 269                         sw4_reg: sw4 {
 270                                 regulator-min-microvolt = <800000>;
 271                                 regulator-max-microvolt = <3300000>;
 272                         };
 273
 274                         swbst_reg: swbst {
 275                                 regulator-min-microvolt = <5000000>;
 276                                 regulator-max-microvolt = <5150000>;
 277                                 regulator-boot-on;
 278                                 regulator-always-on;
 279                         };
 280
 281                         snvs_reg: vsnvs {
 282                                 regulator-min-microvolt = <1000000>;
 283                                 regulator-max-microvolt = <3000000>;
 284                                 regulator-boot-on;
 285                                 regulator-always-on;
 286                         };
 287
 288                         vref_reg: vrefddr {
 289                                 regulator-boot-on;
 290                                 regulator-always-on;
 291                         };
 292
 293                         vgen1_reg: vgen1 {
 294                                 regulator-min-microvolt = <800000>;
 295                                 regulator-max-microvolt = <1550000>;
 296                         };
 297
 298                         vgen2_reg: vgen2 {
 299                                 regulator-min-microvolt = <800000>;
 300                                 regulator-max-microvolt = <1550000>;
 301                         };
 302
 303                         vgen3_reg: vgen3 {
 304                                 regulator-min-microvolt = <1800000>;
 305                                 regulator-max-microvolt = <3300000>;
 306                         };
 307
 308                         vgen4_reg: vgen4 {
 309                                 regulator-min-microvolt = <1800000>;
 310                                 regulator-max-microvolt = <3300000>;
 311                                 regulator-always-on;
 312                         };
 313
 314                         vgen5_reg: vgen5 {
 315                                 regulator-min-microvolt = <1800000>;
 316                                 regulator-max-microvolt = <3300000>;
 317                                 regulator-always-on;
 318                         };
 319
 320                         vgen6_reg: vgen6 {
 321                                 regulator-min-microvolt = <1800000>;
 322                                 regulator-max-microvolt = <3300000>;
 323                                 regulator-always-on;
 324                         };
 325                 };
 326         };
 327 };
 328
 329 &i2c3 {
 330         clock-frequency = <100000>;
 331         pinctrl-names = "default";
 332         pinctrl-0 = <&pinctrl_i2c3>;
 333         status = "okay";
 334
 335         codec: sgtl5000@0a {
 336                 compatible = "fsl,sgtl5000";
 337                 reg = <0x0a>;
 338                 clocks = <&clks IMX6QDL_CLK_CKO>;
 339                 VDDA-supply = <&sw4_reg>;
 340                 VDDIO-supply = <&reg_3p3v>;
 341         };
 342
 343         touchscreen: egalax_ts@04 {
 344                 compatible = "eeti,egalax_ts";
 345                 reg = <0x04>;
 346                 interrupt-parent = <&gpio7>;
 347                 interrupts = <12 2>;
 348                 wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
 349         };
 350 };
 351
 352 &ldb {
 353         status = "okay";
 354
 355         lvds-channel@0 {
 356                 fsl,data-mapping = "spwg";
 357                 fsl,data-width = <18>;
 358                 status = "okay";
 359
 360                 display-timings {
 361                         native-mode = <&timing0>;
 362                         timing0: hsd100pxn1 {
 363                                 clock-frequency = <65000000>;
 364                                 hactive = <1024>;
 365                                 vactive = <768>;
 366                                 hback-porch = <220>;
 367                                 hfront-porch = <40>;
 368                                 vback-porch = <21>;
 369                                 vfront-porch = <7>;
 370                                 hsync-len = <60>;
 371                                 vsync-len = <10>;
 372                         };
 373                 };
 374         };
 375 };
 376
 377 &pcie {
 378         pinctrl-names = "default";
 379         pinctrl-0 = <&pinctrl_pcie>;
 380         reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
 381         status = "okay";
 382
 383         eth1: sky2@8 { /* MAC/PHY on bus 8 */
 384                 compatible = "marvell,sky2";
 385         };
 386 };
 387
 388 &pwm1 {
 389         pinctrl-names = "default";
 390         pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */
 391         status = "disabled";
 392 };
 393
 394 &pwm2 {
 395         pinctrl-names = "default";
 396         pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
 397         status = "disabled";
 398 };
 399
 400 &pwm3 {
 401         pinctrl-names = "default";
 402         pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
 403         status = "disabled";
 404 };
 405
 406 &pwm4 {
 407         pinctrl-names = "default", "state_dio";
 408         pinctrl-0 = <&pinctrl_pwm4_backlight>;
 409         pinctrl-1 = <&pinctrl_pwm4_dio>;
 410         status = "okay";
 411 };
 412
 413 &ssi1 {
 414         status = "okay";
 415 };
 416
 417 &ssi2 {
 418         status = "okay";
 419 };
 420
 421 &uart1 {
 422         pinctrl-names = "default";
 423         pinctrl-0 = <&pinctrl_uart1>;
 424         uart-has-rtscts;
 425         rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
 426         status = "okay";
 427 };
 428
 429 &uart2 {
 430         pinctrl-names = "default";
 431         pinctrl-0 = <&pinctrl_uart2>;
 432         status = "okay";
 433 };
 434
 435 &uart5 {
 436         pinctrl-names = "default";
 437         pinctrl-0 = <&pinctrl_uart5>;
 438         status = "okay";
 439 };
 440
 441 &usbotg {
 442         vbus-supply = <&reg_usb_otg_vbus>;
 443         pinctrl-names = "default";
 444         pinctrl-0 = <&pinctrl_usbotg>;
 445         disable-over-current;
 446         status = "okay";
 447 };
 448
 449 &usbh1 {
 450         vbus-supply = <&reg_usb_h1_vbus>;
 451         status = "okay";
 452 };
 453
 454 &usdhc3 {
 455         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 456         pinctrl-0 = <&pinctrl_usdhc3>;
 457         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 458         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 459         cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
 460         vmmc-supply = <&reg_3p3v>;
 461         no-1-8-v; /* firmware will remove if board revision supports */
 462         status = "okay";
 463 };
 464
 465 &wdog1 {
 466         status = "disabled";
 467 };
 468
 469 &wdog2 {
 470         pinctrl-names = "default";
 471         pinctrl-0 = <&pinctrl_wdog>;
 472         fsl,ext-reset-output;
 473         status = "okay";
 474 };
 475
 476 &iomuxc {
 477         imx6qdl-gw54xx {
 478                 pinctrl_audmux: audmuxgrp {
 479                         fsl,pins = <
 480                                 MX6QDL_PAD_SD2_DAT0__AUD4_RXD           0x130b0
 481                                 MX6QDL_PAD_SD2_DAT3__AUD4_TXC           0x130b0
 482                                 MX6QDL_PAD_SD2_DAT2__AUD4_TXD           0x110b0
 483                                 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS          0x130b0
 484                                 MX6QDL_PAD_GPIO_0__CCM_CLKO1            0x130b0 /* AUD4_MCK */
 485                         >;
 486                 };
 487
 488                 pinctrl_enet: enetgrp {
 489                         fsl,pins = <
 490                                 MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 491                                 MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 492                                 MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 493                                 MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 494                                 MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 495                                 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 496                                 MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
 497                                 MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
 498                                 MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
 499                                 MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
 500                                 MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
 501                                 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
 502                                 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 503                                 MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 504                                 MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 505                                 MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
 506                         >;
 507                 };
 508
 509                 pinctrl_ecspi2: escpi2grp {
 510                         fsl,pins = <
 511                                 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
 512                                 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
 513                                 MX6QDL_PAD_EIM_OE__ECSPI2_MISO  0x100b1
 514                                 MX6QDL_PAD_EIM_RW__GPIO2_IO26   0x100b1
 515                         >;
 516                 };
 517
 518                 pinctrl_flexcan1: flexcan1grp {
 519                         fsl,pins = <
 520                                 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX        0x1b0b1
 521                                 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX        0x1b0b1
 522                                 MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x4001b0b0 /* CAN_STBY */
 523                         >;
 524                 };
 525
 526                 pinctrl_gpio_leds: gpioledsgrp {
 527                         fsl,pins = <
 528                                 MX6QDL_PAD_KEY_COL0__GPIO4_IO06         0x1b0b0
 529                                 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07         0x1b0b0
 530                                 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15         0x1b0b0
 531                         >;
 532                 };
 533
 534                 pinctrl_gpmi_nand: gpminandgrp {
 535                         fsl,pins = <
 536                                 MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 537                                 MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 538                                 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 539                                 MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 540                                 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 541                                 MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 542                                 MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 543                                 MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 544                                 MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 545                                 MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 546                                 MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 547                                 MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 548                                 MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 549                                 MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 550                                 MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 551                         >;
 552                 };
 553
 554                 pinctrl_i2c1: i2c1grp {
 555                         fsl,pins = <
 556                                 MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 557                                 MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 558                         >;
 559                 };
 560
 561                 pinctrl_i2c2: i2c2grp {
 562                         fsl,pins = <
 563                                 MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 564                                 MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 565                         >;
 566                 };
 567
 568                 pinctrl_i2c3: i2c3grp {
 569                         fsl,pins = <
 570                                 MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 571                                 MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 572                         >;
 573                 };
 574
 575                 pinctrl_pcie: pciegrp {
 576                         fsl,pins = <
 577                                 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28       0x1b0b0 /* PCIE IRQ */
 578                                 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29        0x1b0b0 /* PCIE RST */
 579                         >;
 580                 };
 581
 582                 pinctrl_pps: ppsgrp {
 583                         fsl,pins = <
 584                                 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26        0x1b0b1
 585                         >;
 586                 };
 587
 588                 pinctrl_pwm1: pwm1grp {
 589                         fsl,pins = <
 590                                 MX6QDL_PAD_GPIO_9__PWM1_OUT             0x1b0b1
 591                         >;
 592                 };
 593
 594                 pinctrl_pwm2: pwm2grp {
 595                         fsl,pins = <
 596                                 MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
 597                         >;
 598                 };
 599
 600                 pinctrl_pwm3: pwm3grp {
 601                         fsl,pins = <
 602                                 MX6QDL_PAD_SD4_DAT1__PWM3_OUT           0x1b0b1
 603                         >;
 604                 };
 605
 606                 pinctrl_pwm4_backlight: pwm4grpbacklight {
 607                         fsl,pins = <
 608                                 /* LVDS_PWM J6.5 */
 609                                 MX6QDL_PAD_SD1_CMD__PWM4_OUT            0x1b0b1
 610                         >;
 611                 };
 612
 613                 pinctrl_pwm4_dio: pwm4grpdio {
 614                         fsl,pins = <
 615                                 /* DIO3 J16.4 */
 616                                 MX6QDL_PAD_SD4_DAT2__PWM4_OUT           0x1b0b1
 617                         >;
 618                 };
 619
 620                 pinctrl_uart1: uart1grp {
 621                         fsl,pins = <
 622                                 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
 623                                 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA      0x1b0b1
 624                                 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01         0x4001b0b1 /* TEN */
 625                         >;
 626                 };
 627
 628                 pinctrl_uart2: uart2grp {
 629                         fsl,pins = <
 630                                 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 631                                 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 632                         >;
 633                 };
 634
 635                 pinctrl_uart5: uart5grp {
 636                         fsl,pins = <
 637                                 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
 638                                 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
 639                         >;
 640                 };
 641
 642                 pinctrl_usbotg: usbotggrp {
 643                         fsl,pins = <
 644                                 MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
 645                                 MX6QDL_PAD_EIM_D22__GPIO3_IO22          0x1b0b0 /* PWR_EN */
 646                         >;
 647                 };
 648
 649                 pinctrl_usdhc3: usdhc3grp {
 650                         fsl,pins = <
 651                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 652                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 653                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 654                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 655                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 656                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 657                                 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x17059 /* CD */
 658                                 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x17059
 659                         >;
 660                 };
 661
 662                 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
 663                         fsl,pins = <
 664                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170b9
 665                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100b9
 666                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170b9
 667                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170b9
 668                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170b9
 669                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170b9
 670                                 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x170b9 /* CD */
 671                                 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x170b9
 672                         >;
 673                 };
 674
 675                 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
 676                         fsl,pins = <
 677                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170f9
 678                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100f9
 679                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170f9
 680                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170f9
 681                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170f9
 682                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170f9
 683                                 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x170f9 /* CD */
 684                                 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x170f9
 685                         >;
 686                 };
 687
 688                 pinctrl_wdog: wdoggrp {
 689                         fsl,pins = <
 690                                 MX6QDL_PAD_SD1_DAT3__WDOG2_B            0x1b0b0
 691                         >;
 692                 };
 693         };
 694 };