arch/arm/boot/dts/imx6qdl-gw553x.dtsi

   1 /*
   2  * Copyright 2016 Gateworks Corporation
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of
  12  *     the License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  *     You should have received a copy of the GNU General Public
  20  *     License along with this file; if not, write to the Free
  21  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  22  *     MA 02110-1301 USA
  23  *
  24  * Or, alternatively,
  25  *
  26  *  b) Permission is hereby granted, free of charge, to any person
  27  *     obtaining a copy of this software and associated documentation
  28  *     files (the "Software"), to deal in the Software without
  29  *     restriction, including without limitation the rights to use,
  30  *     copy, modify, merge, publish, distribute, sublicense, and/or
  31  *     sell copies of the Software, and to permit persons to whom the
  32  *     Software is furnished to do so, subject to the following
  33  *     conditions:
  34  *
  35  *     The above copyright notice and this permission notice shall be
  36  *     included in all copies or substantial portions of the Software.
  37  *
  38  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  39  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  40  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  41  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  42  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  43  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  44  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  45  *     OTHER DEALINGS IN THE SOFTWARE.
  46  */
  47
  48 #include <dt-bindings/gpio/gpio.h>
  49
  50 / {
  51         /* these are used by bootloader for disabling nodes */
  52         aliases {
  53                 led0 = &led0;
  54                 led1 = &led1;
  55                 nand = &gpmi;
  56                 usb0 = &usbh1;
  57                 usb1 = &usbotg;
  58         };
  59
  60         chosen {
  61                 stdout-path = &uart2;
  62         };
  63
  64         leds {
  65                 compatible = "gpio-leds";
  66                 pinctrl-names = "default";
  67                 pinctrl-0 = <&pinctrl_gpio_leds>;
  68
  69                 led0: user1 {
  70                         label = "user1";
  71                         gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
  72                         default-state = "on";
  73                         linux,default-trigger = "heartbeat";
  74                 };
  75
  76                 led1: user2 {
  77                         label = "user2";
  78                         gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
  79                         default-state = "off";
  80                 };
  81         };
  82
  83         memory {
  84                 reg = <0x10000000 0x20000000>;
  85         };
  86
  87         pps {
  88                 compatible = "pps-gpio";
  89                 pinctrl-names = "default";
  90                 pinctrl-0 = <&pinctrl_pps>;
  91                 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
  92                 status = "okay";
  93         };
  94
  95         reg_5p0v: regulator-5p0v {
  96                 compatible = "regulator-fixed";
  97                 regulator-name = "5P0V";
  98                 regulator-min-microvolt = <5000000>;
  99                 regulator-max-microvolt = <5000000>;
 100                 regulator-always-on;
 101         };
 102
 103         reg_usb_otg_vbus: regulator-usb-otg-vbus {
 104                 compatible = "regulator-fixed";
 105                 regulator-name = "usb_otg_vbus";
 106                 regulator-min-microvolt = <5000000>;
 107                 regulator-max-microvolt = <5000000>;
 108                 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
 109                 enable-active-high;
 110         };
 111 };
 112
 113 &gpmi {
 114         pinctrl-names = "default";
 115         pinctrl-0 = <&pinctrl_gpmi_nand>;
 116         status = "okay";
 117 };
 118
 119 &hdmi {
 120         pinctrl-names = "default";
 121         pinctrl-0 = <&pinctrl_hdmi>;
 122         ddc-i2c-bus = <&i2c3>;
 123         status = "okay";
 124 };
 125
 126 &i2c1 {
 127         clock-frequency = <100000>;
 128         pinctrl-names = "default";
 129         pinctrl-0 = <&pinctrl_i2c1>;
 130         status = "okay";
 131
 132         gpio: pca9555@23 {
 133                 compatible = "nxp,pca9555";
 134                 reg = <0x23>;
 135                 gpio-controller;
 136                 #gpio-cells = <2>;
 137         };
 138
 139         eeprom1: eeprom@50 {
 140                 compatible = "atmel,24c02";
 141                 reg = <0x50>;
 142                 pagesize = <16>;
 143         };
 144
 145         eeprom2: eeprom@51 {
 146                 compatible = "atmel,24c02";
 147                 reg = <0x51>;
 148                 pagesize = <16>;
 149         };
 150
 151         eeprom3: eeprom@52 {
 152                 compatible = "atmel,24c02";
 153                 reg = <0x52>;
 154                 pagesize = <16>;
 155         };
 156
 157         eeprom4: eeprom@53 {
 158                 compatible = "atmel,24c02";
 159                 reg = <0x53>;
 160                 pagesize = <16>;
 161         };
 162
 163         rtc: ds1672@68 {
 164                 compatible = "dallas,ds1672";
 165                 reg = <0x68>;
 166         };
 167 };
 168
 169 &i2c2 {
 170         clock-frequency = <100000>;
 171         pinctrl-names = "default";
 172         pinctrl-0 = <&pinctrl_i2c2>;
 173         status = "okay";
 174
 175         ltc3676: pmic@3c {
 176                 compatible = "lltc,ltc3676";
 177                 reg = <0x3c>;
 178                 pinctrl-names = "default";
 179                 pinctrl-0 = <&pinctrl_pmic>;
 180                 interrupt-parent = <&gpio1>;
 181                 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
 182
 183                 regulators {
 184                         /* VDD_SOC (1+R1/R2 = 1.635) */
 185                         reg_vdd_soc: sw1 {
 186                                 regulator-name = "vddsoc";
 187                                 regulator-min-microvolt = <674400>;
 188                                 regulator-max-microvolt = <1308000>;
 189                                 lltc,fb-voltage-divider = <127000 200000>;
 190                                 regulator-ramp-delay = <7000>;
 191                                 regulator-boot-on;
 192                                 regulator-always-on;
 193                         };
 194
 195                         /* VDD_DDR (1+R1/R2 = 2.105) */
 196                         reg_vdd_ddr: sw2 {
 197                                 regulator-name = "vddddr";
 198                                 regulator-min-microvolt = <868310>;
 199                                 regulator-max-microvolt = <1684000>;
 200                                 lltc,fb-voltage-divider = <221000 200000>;
 201                                 regulator-ramp-delay = <7000>;
 202                                 regulator-boot-on;
 203                                 regulator-always-on;
 204                         };
 205
 206                         /* VDD_ARM (1+R1/R2 = 1.635) */
 207                         reg_vdd_arm: sw3 {
 208                                 regulator-name = "vddarm";
 209                                 regulator-min-microvolt = <674400>;
 210                                 regulator-max-microvolt = <1308000>;
 211                                 lltc,fb-voltage-divider = <127000 200000>;
 212                                 regulator-ramp-delay = <7000>;
 213                                 regulator-boot-on;
 214                                 regulator-always-on;
 215                         };
 216
 217                         /* VDD_3P3 (1+R1/R2 = 1.281) */
 218                         reg_3p3v: sw4 {
 219                                 regulator-name = "vdd3p3";
 220                                 regulator-min-microvolt = <1880000>;
 221                                 regulator-max-microvolt = <3647000>;
 222                                 lltc,fb-voltage-divider = <200000 56200>;
 223                                 regulator-ramp-delay = <7000>;
 224                                 regulator-boot-on;
 225                                 regulator-always-on;
 226                         };
 227
 228                         /* VDD_1P8a (1+R1/R2 = 2.505): Analog Video Decoder */
 229                         reg_1p8a: ldo2 {
 230                                 regulator-name = "vdd1p8a";
 231                                 regulator-min-microvolt = <1816125>;
 232                                 regulator-max-microvolt = <1816125>;
 233                                 lltc,fb-voltage-divider = <301000 200000>;
 234                                 regulator-boot-on;
 235                                 regulator-always-on;
 236                         };
 237
 238                         /* VDD_1P8b: microSD VDD_1P8 */
 239                         reg_1p8b: ldo3 {
 240                                 regulator-name = "vdd1p8b";
 241                                 regulator-min-microvolt = <1800000>;
 242                                 regulator-max-microvolt = <1800000>;
 243                                 regulator-boot-on;
 244                         };
 245
 246                         /* VDD_HIGH (1+R1/R2 = 4.17) */
 247                         reg_3p0v: ldo4 {
 248                                 regulator-name = "vdd3p0";
 249                                 regulator-min-microvolt = <3023250>;
 250                                 regulator-max-microvolt = <3023250>;
 251                                 lltc,fb-voltage-divider = <634000 200000>;
 252                                 regulator-boot-on;
 253                                 regulator-always-on;
 254                         };
 255                 };
 256         };
 257 };
 258
 259 &i2c3 {
 260         clock-frequency = <100000>;
 261         pinctrl-names = "default";
 262         pinctrl-0 = <&pinctrl_i2c3>;
 263         status = "okay";
 264 };
 265
 266 &pcie {
 267         pinctrl-names = "default";
 268         pinctrl-0 = <&pinctrl_pcie>;
 269         reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
 270         status = "okay";
 271 };
 272
 273 &pwm2 {
 274         pinctrl-names = "default";
 275         pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
 276         status = "disabled";
 277 };
 278
 279 &pwm3 {
 280         pinctrl-names = "default";
 281         pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
 282         status = "disabled";
 283 };
 284
 285 &pwm4 {
 286         pinctrl-names = "default";
 287         pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
 288         status = "disabled";
 289 };
 290
 291 &uart2 {
 292         pinctrl-names = "default";
 293         pinctrl-0 = <&pinctrl_uart2>;
 294         status = "okay";
 295 };
 296
 297 &uart3 {
 298         pinctrl-names = "default";
 299         pinctrl-0 = <&pinctrl_uart3>;
 300         status = "okay";
 301 };
 302
 303 &uart4 {
 304         pinctrl-names = "default";
 305         pinctrl-0 = <&pinctrl_uart4>;
 306         status = "okay";
 307 };
 308
 309 &uart5 {
 310         pinctrl-names = "default";
 311         pinctrl-0 = <&pinctrl_uart5>;
 312         status = "okay";
 313 };
 314
 315 &usbh1 {
 316         status = "okay";
 317 };
 318
 319 &usbotg {
 320         vbus-supply = <&reg_usb_otg_vbus>;
 321         pinctrl-names = "default";
 322         pinctrl-0 = <&pinctrl_usbotg>;
 323         disable-over-current;
 324         status = "okay";
 325 };
 326
 327 &usdhc3 {
 328         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 329         pinctrl-0 = <&pinctrl_usdhc3>;
 330         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 331         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 332         cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
 333         status = "okay";
 334 };
 335
 336 &wdog1 {
 337         pinctrl-names = "default";
 338         pinctrl-0 = <&pinctrl_wdog>;
 339         fsl,ext-reset-output;
 340 };
 341
 342 &iomuxc {
 343         pinctrl_gpmi_nand: gpminandgrp {
 344                 fsl,pins = <
 345                         MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 346                         MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 347                         MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 348                         MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 349                         MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 350                         MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 351                         MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 352                         MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 353                         MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 354                         MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 355                         MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 356                         MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 357                         MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 358                         MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 359                         MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 360                 >;
 361         };
 362
 363         pinctrl_hdmi: hdmigrp {
 364                 fsl,pins = <
 365                         MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE    0x1f8b0
 366                 >;
 367         };
 368
 369         pinctrl_i2c1: i2c1grp {
 370                 fsl,pins = <
 371                         MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 372                         MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 373                 >;
 374         };
 375
 376         pinctrl_i2c2: i2c2grp {
 377                 fsl,pins = <
 378                         MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 379                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 380                 >;
 381         };
 382
 383         pinctrl_i2c3: i2c3grp {
 384                 fsl,pins = <
 385                         MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 386                         MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 387                 >;
 388         };
 389
 390         pinctrl_gpio_leds: gpioledsgrp {
 391                 fsl,pins = <
 392                         MX6QDL_PAD_KEY_COL2__GPIO4_IO10         0x1b0b0
 393                         MX6QDL_PAD_KEY_ROW2__GPIO4_IO11         0x1b0b0
 394                 >;
 395         };
 396
 397         pinctrl_pcie: pciegrp {
 398                 fsl,pins = <
 399                         MX6QDL_PAD_GPIO_0__GPIO1_IO00           0x1b0b0
 400                         MX6QDL_PAD_GPIO_17__GPIO7_IO12          0x4001b0b0 /* PCIESKT_WDIS# */
 401                 >;
 402         };
 403
 404         pinctrl_pmic: pmicgrp {
 405                 fsl,pins = <
 406                         MX6QDL_PAD_GPIO_8__GPIO1_IO08           0x0001b0b0 /* PMIC_IRQ# */
 407                 >;
 408         };
 409
 410         pinctrl_pps: ppsgrp {
 411                 fsl,pins = <
 412                         MX6QDL_PAD_ENET_RXD1__GPIO1_IO26        0x1b0b1
 413                 >;
 414         };
 415
 416         pinctrl_pwm2: pwm2grp {
 417                 fsl,pins = <
 418                         MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
 419                 >;
 420         };
 421
 422         pinctrl_pwm3: pwm3grp {
 423                 fsl,pins = <
 424                         MX6QDL_PAD_SD4_DAT1__PWM3_OUT           0x1b0b1
 425                 >;
 426         };
 427
 428         pinctrl_pwm4: pwm4grp {
 429                 fsl,pins = <
 430                         MX6QDL_PAD_SD1_CMD__PWM4_OUT            0x1b0b1
 431                 >;
 432         };
 433
 434         pinctrl_uart2: uart2grp {
 435                 fsl,pins = <
 436                         MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 437                         MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 438                 >;
 439         };
 440
 441         pinctrl_uart3: uart3grp {
 442                 fsl,pins = <
 443                         MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
 444                         MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
 445                 >;
 446         };
 447
 448         pinctrl_uart4: uart4grp {
 449                 fsl,pins = <
 450                         MX6QDL_PAD_KEY_COL0__UART4_TX_DATA      0x1b0b1
 451                         MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA      0x1b0b1
 452                 >;
 453         };
 454
 455         pinctrl_uart5: uart5grp {
 456                 fsl,pins = <
 457                         MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
 458                         MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
 459                 >;
 460         };
 461
 462         pinctrl_usbotg: usbotggrp {
 463                 fsl,pins = <
 464                         MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
 465                         MX6QDL_PAD_EIM_D22__GPIO3_IO22          0x1b0b0 /* OTG_PWR_EN */
 466                 >;
 467         };
 468
 469         pinctrl_usdhc3: usdhc3grp {
 470                 fsl,pins = <
 471                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 472                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 473                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 474                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 475                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 476                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 477                         MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x17059 /* CD */
 478                         MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x17059
 479                 >;
 480         };
 481
 482         pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
 483                 fsl,pins = <
 484                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170b9
 485                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100b9
 486                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170b9
 487                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170b9
 488                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170b9
 489                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170b9
 490                         MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x170b9 /* CD */
 491                         MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x170b9
 492                 >;
 493         };
 494
 495         pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
 496                 fsl,pins = <
 497                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170f9
 498                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100f9
 499                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170f9
 500                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170f9
 501                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170f9
 502                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170f9
 503                         MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x170f9 /* CD */
 504                         MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x170f9
 505                 >;
 506         };
 507
 508         pinctrl_wdog: wdoggrp {
 509                 fsl,pins = <
 510                         MX6QDL_PAD_DISP0_DAT8__WDOG1_B          0x1b0b0
 511                 >;
 512         };
 513 };