arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi

   1 /*
   2  * Copyright 2016 Boundary Devices, Inc.
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License
  11  *     version 2 as published by the Free Software Foundation.
  12  *
  13  *     This file is distributed in the hope that it will be useful,
  14  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *     GNU General Public License for more details.
  17  *
  18  * Or, alternatively,
  19  *
  20  *  b) Permission is hereby granted, free of charge, to any person
  21  *     obtaining a copy of this software and associated documentation
  22  *     files (the "Software"), to deal in the Software without
  23  *     restriction, including without limitation the rights to use,
  24  *     copy, modify, merge, publish, distribute, sublicense, and/or
  25  *     sell copies of the Software, and to permit persons to whom the
  26  *     Software is furnished to do so, subject to the following
  27  *     conditions:
  28  *
  29  *     The above copyright notice and this permission notice shall be
  30  *     included in all copies or substantial portions of the Software.
  31  *
  32  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  33  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  34  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  35  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  36  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  37  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  38  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  39  *     OTHER DEALINGS IN THE SOFTWARE.
  40  */
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/input/input.h>
  43
  44 / {
  45         chosen {
  46                 stdout-path = &uart2;
  47         };
  48
  49         memory {
  50                 reg = <0x10000000 0x40000000>;
  51         };
  52
  53         backlight_lcd: backlight-lcd {
  54                 compatible = "pwm-backlight";
  55                 pwms = <&pwm1 0 5000000>;
  56                 brightness-levels = <0 4 8 16 32 64 128 255>;
  57                 default-brightness-level = <7>;
  58                 power-supply = <&reg_3p3v>;
  59                 status = "okay";
  60         };
  61
  62         backlight_lvds0: backlight-lvds0 {
  63                 compatible = "pwm-backlight";
  64                 pwms = <&pwm4 0 5000000>;
  65                 brightness-levels = <0 4 8 16 32 64 128 255>;
  66                 default-brightness-level = <7>;
  67                 power-supply = <&reg_3p3v>;
  68                 status = "okay";
  69         };
  70
  71         backlight_lvds1: backlight-lvds1 {
  72                 compatible = "gpio-backlight";
  73                 pinctrl-names = "default";
  74                 pinctrl-0 = <&pinctrl_backlight_lvds1>;
  75                 gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>;
  76                 default-on;
  77                 status = "okay";
  78         };
  79
  80         gpio-keys {
  81                 compatible = "gpio-keys";
  82                 pinctrl-names = "default";
  83                 pinctrl-0 = <&pinctrl_gpio_keys>;
  84
  85                 power {
  86                         label = "Power Button";
  87                         gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
  88                         linux,code = <KEY_POWER>;
  89                         wakeup-source;
  90                 };
  91
  92                 menu {
  93                         label = "Menu";
  94                         gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
  95                         linux,code = <KEY_MENU>;
  96                 };
  97
  98                 home {
  99                         label = "Home";
 100                         gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
 101                         linux,code = <KEY_HOME>;
 102                 };
 103
 104                 back {
 105                         label = "Back";
 106                         gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
 107                         linux,code = <KEY_BACK>;
 108                 };
 109
 110                 volume-up {
 111                         label = "Volume Up";
 112                         gpios = <&gpio7 13 GPIO_ACTIVE_LOW>;
 113                         linux,code = <KEY_VOLUMEUP>;
 114                 };
 115
 116                 volume-down {
 117                         label = "Volume Down";
 118                         gpios = <&gpio7 1 GPIO_ACTIVE_LOW>;
 119                         linux,code = <KEY_VOLUMEDOWN>;
 120                 };
 121         };
 122
 123         lcd_display: display@di0 {
 124                 compatible = "fsl,imx-parallel-display";
 125                 #address-cells = <1>;
 126                 #size-cells = <0>;
 127                 interface-pix-fmt = "bgr666";
 128                 pinctrl-names = "default";
 129                 pinctrl-0 = <&pinctrl_j15>;
 130                 status = "okay";
 131
 132                 port@0 {
 133                         reg = <0>;
 134
 135                         lcd_display_in: endpoint {
 136                                 remote-endpoint = <&ipu1_di0_disp0>;
 137                         };
 138                 };
 139
 140                 port@1 {
 141                         reg = <1>;
 142
 143                         lcd_display_out: endpoint {
 144                                 remote-endpoint = <&lcd_panel_in>;
 145                         };
 146                 };
 147         };
 148
 149         panel-lcd {
 150                 compatible = "okaya,rs800480t-7x0gp";
 151                 backlight = <&backlight_lcd>;
 152
 153                 port {
 154                         lcd_panel_in: endpoint {
 155                                 remote-endpoint = <&lcd_display_out>;
 156                         };
 157                 };
 158         };
 159
 160         panel-lvds0 {
 161                 compatible = "hannstar,hsd100pxn1";
 162                 backlight = <&backlight_lvds0>;
 163
 164                 port {
 165                         panel_in_lvds0: endpoint {
 166                                 remote-endpoint = <&lvds0_out>;
 167                         };
 168                 };
 169         };
 170
 171         panel-lvds1 {
 172                 compatible = "hannstar,hsd100pxn1";
 173                 backlight = <&backlight_lvds1>;
 174
 175                 port {
 176                         panel_in_lvds1: endpoint {
 177                                 remote-endpoint = <&lvds1_out>;
 178                         };
 179                 };
 180         };
 181
 182         reg_1p8v: regulator-1v8 {
 183                 compatible = "regulator-fixed";
 184                 regulator-name = "1P8V";
 185                 regulator-min-microvolt = <1800000>;
 186                 regulator-max-microvolt = <1800000>;
 187                 regulator-always-on;
 188         };
 189
 190         reg_2p5v: regulator-2v5 {
 191                 compatible = "regulator-fixed";
 192                 regulator-name = "2P5V";
 193                 regulator-min-microvolt = <2500000>;
 194                 regulator-max-microvolt = <2500000>;
 195                 regulator-always-on;
 196         };
 197
 198         reg_3p3v: regulator-3v3 {
 199                 compatible = "regulator-fixed";
 200                 regulator-name = "3P3V";
 201                 regulator-min-microvolt = <3300000>;
 202                 regulator-max-microvolt = <3300000>;
 203                 regulator-always-on;
 204         };
 205
 206         reg_can_xcvr: regulator-can-xcvr {
 207                 compatible = "regulator-fixed";
 208                 regulator-name = "CAN XCVR";
 209                 regulator-min-microvolt = <3300000>;
 210                 regulator-max-microvolt = <3300000>;
 211                 pinctrl-names = "default";
 212                 pinctrl-0 = <&pinctrl_can_xcvr>;
 213                 gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
 214         };
 215
 216         reg_usb_h1_vbus: regulator-usb-h1-vbus {
 217                 compatible = "regulator-fixed";
 218                 pinctrl-names = "default";
 219                 pinctrl-0 = <&pinctrl_usbh1>;
 220                 regulator-name = "usb_h1_vbus";
 221                 regulator-min-microvolt = <3300000>;
 222                 regulator-max-microvolt = <3300000>;
 223                 gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
 224                 enable-active-high;
 225                 regulator-always-on;
 226         };
 227
 228         reg_usb_otg_vbus: regulator-usb-otg-vbus {
 229                 compatible = "regulator-fixed";
 230                 regulator-name = "usb_otg_vbus";
 231                 regulator-min-microvolt = <5000000>;
 232                 regulator-max-microvolt = <5000000>;
 233                 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
 234                 enable-active-high;
 235         };
 236
 237         reg_wlan_vmmc: regulator-wlan-vmmc {
 238                 compatible = "regulator-fixed";
 239                 pinctrl-names = "default";
 240                 pinctrl-0 = <&pinctrl_wlan_vmmc>;
 241                 regulator-name = "reg_wlan_vmmc";
 242                 regulator-min-microvolt = <3300000>;
 243                 regulator-max-microvolt = <3300000>;
 244                 gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>;
 245                 startup-delay-us = <70000>;
 246                 enable-active-high;
 247         };
 248
 249         sound {
 250                 compatible = "fsl,imx6q-nitrogen6_som2-sgtl5000",
 251                              "fsl,imx-audio-sgtl5000";
 252                 model = "imx6q-nitrogen6_som2-sgtl5000";
 253                 ssi-controller = <&ssi1>;
 254                 audio-codec = <&codec>;
 255                 audio-routing =
 256                         "MIC_IN", "Mic Jack",
 257                         "Mic Jack", "Mic Bias",
 258                         "Headphone Jack", "HP_OUT";
 259                 mux-int-port = <1>;
 260                 mux-ext-port = <3>;
 261         };
 262 };
 263
 264 &audmux {
 265         pinctrl-names = "default";
 266         pinctrl-0 = <&pinctrl_audmux>;
 267         status = "okay";
 268 };
 269
 270 &can1 {
 271         pinctrl-names = "default";
 272         pinctrl-0 = <&pinctrl_can1>;
 273         xceiver-supply = <&reg_can_xcvr>;
 274         status = "okay";
 275 };
 276
 277 &clks {
 278         assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
 279                           <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
 280         assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
 281                                  <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
 282 };
 283
 284 &ecspi1 {
 285         cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
 286         pinctrl-names = "default";
 287         pinctrl-0 = <&pinctrl_ecspi1>;
 288         status = "okay";
 289
 290         flash: m25p80@0 {
 291                 compatible = "microchip,sst25vf016b";
 292                 spi-max-frequency = <20000000>;
 293                 reg = <0>;
 294         };
 295 };
 296
 297 &fec {
 298         pinctrl-names = "default";
 299         pinctrl-0 = <&pinctrl_enet>;
 300         phy-mode = "rgmii";
 301         interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
 302                               <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
 303         fsl,err006687-workaround-present;
 304         status = "okay";
 305 };
 306
 307 &hdmi {
 308         ddc-i2c-bus = <&i2c2>;
 309         status = "okay";
 310 };
 311
 312 &i2c1 {
 313         clock-frequency = <100000>;
 314         pinctrl-names = "default";
 315         pinctrl-0 = <&pinctrl_i2c1>;
 316         status = "okay";
 317
 318         codec: sgtl5000@0a {
 319                 compatible = "fsl,sgtl5000";
 320                 pinctrl-names = "default";
 321                 pinctrl-0 = <&pinctrl_sgtl5000>;
 322                 reg = <0x0a>;
 323                 clocks = <&clks IMX6QDL_CLK_CKO>;
 324                 VDDA-supply = <&reg_2p5v>;
 325                 VDDIO-supply = <&reg_3p3v>;
 326         };
 327
 328         rtc@68 {
 329                 compatible = "st,rv4162";
 330                 pinctrl-names = "default";
 331                 pinctrl-0 = <&pinctrl_rv4162>;
 332                 reg = <0x68>;
 333                 interrupts-extended = <&gpio6 7 IRQ_TYPE_LEVEL_LOW>;
 334         };
 335 };
 336
 337 &i2c2 {
 338         clock-frequency = <100000>;
 339         pinctrl-names = "default";
 340         pinctrl-0 = <&pinctrl_i2c2>;
 341         status = "okay";
 342 };
 343
 344 &i2c3 {
 345         clock-frequency = <100000>;
 346         pinctrl-names = "default";
 347         pinctrl-0 = <&pinctrl_i2c3>;
 348         status = "okay";
 349
 350         touchscreen@04 {
 351                 compatible = "eeti,egalax_ts";
 352                 reg = <0x04>;
 353                 interrupt-parent = <&gpio1>;
 354                 interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
 355                 wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
 356         };
 357
 358         touchscreen@38 {
 359                 compatible = "edt,edt-ft5x06";
 360                 reg = <0x38>;
 361                 interrupt-parent = <&gpio1>;
 362                 interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
 363         };
 364 };
 365
 366 &iomuxc {
 367         pinctrl_audmux: audmuxgrp {
 368                 fsl,pins = <
 369                         MX6QDL_PAD_CSI0_DAT7__AUD3_RXD          0x130b0
 370                         MX6QDL_PAD_CSI0_DAT4__AUD3_TXC          0x130b0
 371                         MX6QDL_PAD_CSI0_DAT5__AUD3_TXD          0x110b0
 372                         MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS         0x130b0
 373                 >;
 374         };
 375
 376         pinctrl_backlight_lvds1: backlight-lvds1grp {
 377                 fsl,pins = <
 378                         MX6QDL_PAD_EIM_EB3__GPIO2_IO31          0x0b0b0
 379                 >;
 380         };
 381
 382         pinctrl_can1: can1grp {
 383                 fsl,pins = <
 384                         MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX        0x1b0b0
 385                         MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX        0x1b0b0
 386                 >;
 387         };
 388
 389         pinctrl_can_xcvr: can-xcvrgrp {
 390                 fsl,pins = <
 391                         /* Flexcan XCVR enable */
 392                         MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x0b0b0
 393                 >;
 394         };
 395
 396         pinctrl_ecspi1: ecspi1grp {
 397                 fsl,pins = <
 398                         MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x100b1
 399                         MX6QDL_PAD_EIM_D18__ECSPI1_MOSI         0x100b1
 400                         MX6QDL_PAD_EIM_D16__ECSPI1_SCLK         0x100b1
 401                         MX6QDL_PAD_EIM_D19__GPIO3_IO19          0x000b1
 402                 >;
 403         };
 404
 405         pinctrl_enet: enetgrp {
 406                 fsl,pins = <
 407                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 408                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 409                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x100b0
 410                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x100b0
 411                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x100b0
 412                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x100b0
 413                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x100b0
 414                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x100b0
 415                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x100b0
 416                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
 417                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x130b0
 418                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
 419                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x130b0
 420                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
 421                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x130b0
 422                         MX6QDL_PAD_ENET_RXD0__GPIO1_IO27        0x030b0
 423                         MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28       0x1b0b0
 424                         MX6QDL_PAD_GPIO_6__ENET_IRQ             0x000b1
 425                 >;
 426         };
 427
 428         pinctrl_gpio_keys: gpio-keysgrp {
 429                 fsl,pins = <
 430                         /* Power Button */
 431                         MX6QDL_PAD_NANDF_D3__GPIO2_IO03         0x1b0b0
 432                         /* Menu Button */
 433                         MX6QDL_PAD_NANDF_D1__GPIO2_IO01         0x1b0b0
 434                         /* Home Button */
 435                         MX6QDL_PAD_NANDF_D4__GPIO2_IO04         0x1b0b0
 436                         /* Back Button */
 437                         MX6QDL_PAD_NANDF_D2__GPIO2_IO02         0x1b0b0
 438                         /* Volume Up Button */
 439                         MX6QDL_PAD_GPIO_18__GPIO7_IO13          0x1b0b0
 440                         /* Volume Down Button */
 441                         MX6QDL_PAD_SD3_DAT4__GPIO7_IO01         0x1b0b0
 442                 >;
 443         };
 444
 445         pinctrl_i2c1: i2c1grp {
 446                 fsl,pins = <
 447                         MX6QDL_PAD_EIM_D21__I2C1_SCL    0x4001b8b1
 448                         MX6QDL_PAD_EIM_D28__I2C1_SDA    0x4001b8b1
 449                 >;
 450         };
 451
 452         pinctrl_i2c2: i2c2grp {
 453                 fsl,pins = <
 454                         MX6QDL_PAD_KEY_COL3__I2C2_SCL   0x4001b8b1
 455                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA   0x4001b8b1
 456                 >;
 457         };
 458
 459         pinctrl_i2c3: i2c3grp {
 460                 fsl,pins = <
 461                         MX6QDL_PAD_GPIO_5__I2C3_SCL     0x4001b8b1
 462                         MX6QDL_PAD_GPIO_16__I2C3_SDA    0x4001b8b1
 463                         MX6QDL_PAD_GPIO_9__GPIO1_IO09   0x1b0b0
 464                 >;
 465         };
 466
 467         pinctrl_i2c3mux: i2c3muxgrp {
 468                 fsl,pins = <
 469                         /* PCIe I2C enable */
 470                         MX6QDL_PAD_EIM_OE__GPIO2_IO25   0x000b0
 471                 >;
 472         };
 473
 474         pinctrl_j15: j15grp {
 475                 fsl,pins = <
 476                         MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
 477                         MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
 478                         MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
 479                         MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
 480                         MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x10
 481                         MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
 482                         MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
 483                         MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
 484                         MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
 485                         MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
 486                         MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
 487                         MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
 488                         MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
 489                         MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
 490                         MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
 491                         MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
 492                         MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
 493                         MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
 494                         MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
 495                         MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
 496                         MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
 497                         MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
 498                         MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
 499                         MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
 500                         MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
 501                         MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
 502                         MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
 503                         MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
 504                 >;
 505         };
 506
 507         pinctrl_pcie: pciegrp {
 508                 fsl,pins = <
 509                         /* PCIe reset */
 510                         MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x030b0
 511                         MX6QDL_PAD_EIM_DA4__GPIO3_IO04  0x030b0
 512                 >;
 513         };
 514
 515         pinctrl_pwm1: pwm1grp {
 516                 fsl,pins = <
 517                         MX6QDL_PAD_SD1_DAT3__PWM1_OUT   0x030b1
 518                 >;
 519         };
 520
 521         pinctrl_pwm3: pwm3grp {
 522                 fsl,pins = <
 523                         MX6QDL_PAD_SD1_DAT1__PWM3_OUT   0x030b1
 524                 >;
 525         };
 526
 527         pinctrl_pwm4: pwm4grp {
 528                 fsl,pins = <
 529                         MX6QDL_PAD_SD1_CMD__PWM4_OUT    0x030b1
 530                 >;
 531         };
 532
 533         pinctrl_rv4162: rv4162grp {
 534                 fsl,pins = <
 535                         MX6QDL_PAD_NANDF_CLE__GPIO6_IO07        0x1b0b0
 536                 >;
 537         };
 538
 539         pinctrl_sgtl5000: sgtl5000grp {
 540                 fsl,pins = <
 541                         MX6QDL_PAD_GPIO_0__CCM_CLKO1            0x000b0
 542                         MX6QDL_PAD_EIM_D29__GPIO3_IO29          0x130b0
 543                         MX6QDL_PAD_EIM_DA2__GPIO3_IO02          0x130b0
 544                         MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24       0x130b0
 545                 >;
 546         };
 547
 548         pinctrl_uart1: uart1grp {
 549                 fsl,pins = <
 550                         MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
 551                         MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA      0x1b0b1
 552                 >;
 553         };
 554
 555         pinctrl_uart2: uart2grp {
 556                 fsl,pins = <
 557                         MX6QDL_PAD_EIM_D26__UART2_TX_DATA       0x1b0b1
 558                         MX6QDL_PAD_EIM_D27__UART2_RX_DATA       0x1b0b1
 559                 >;
 560         };
 561
 562         pinctrl_uart3: uart3grp {
 563                 fsl,pins = <
 564                         MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
 565                         MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
 566                         MX6QDL_PAD_EIM_D23__UART3_CTS_B         0x1b0b1
 567                         MX6QDL_PAD_EIM_D31__UART3_RTS_B         0x1b0b1
 568                 >;
 569         };
 570
 571         pinctrl_usbh1: usbh1grp {
 572                 fsl,pins = <
 573                         MX6QDL_PAD_GPIO_17__GPIO7_IO12          0x030b0
 574                 >;
 575         };
 576
 577         pinctrl_usbotg: usbotggrp {
 578                 fsl,pins = <
 579                         MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
 580                         MX6QDL_PAD_KEY_COL4__USB_OTG_OC         0x1b0b0
 581                         /* power enable, high active */
 582                         MX6QDL_PAD_EIM_D22__GPIO3_IO22          0x030b0
 583                 >;
 584         };
 585
 586         pinctrl_usdhc2: usdhc2grp {
 587                 fsl,pins = <
 588                         MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10071
 589                         MX6QDL_PAD_SD2_CMD__SD2_CMD             0x17071
 590                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17071
 591                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17071
 592                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17071
 593                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17071
 594                 >;
 595         };
 596
 597         pinctrl_usdhc3: usdhc3grp {
 598                 fsl,pins = <
 599                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10071
 600                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17071
 601                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17071
 602                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17071
 603                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17071
 604                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17071
 605                         MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x1b0b0
 606                 >;
 607         };
 608
 609         pinctrl_usdhc4: usdhc4grp {
 610                 fsl,pins = <
 611                         MX6QDL_PAD_SD4_CMD__SD4_CMD             0x17059
 612                         MX6QDL_PAD_SD4_CLK__SD4_CLK             0x10059
 613                         MX6QDL_PAD_SD4_DAT0__SD4_DATA0          0x17059
 614                         MX6QDL_PAD_SD4_DAT1__SD4_DATA1          0x17059
 615                         MX6QDL_PAD_SD4_DAT2__SD4_DATA2          0x17059
 616                         MX6QDL_PAD_SD4_DAT3__SD4_DATA3          0x17059
 617                         MX6QDL_PAD_SD4_DAT4__SD4_DATA4          0x17059
 618                         MX6QDL_PAD_SD4_DAT5__SD4_DATA5          0x17059
 619                         MX6QDL_PAD_SD4_DAT6__SD4_DATA6          0x17059
 620                         MX6QDL_PAD_SD4_DAT7__SD4_DATA7          0x17059
 621                 >;
 622         };
 623
 624         pinctrl_wlan_vmmc: wlan-vmmcgrp {
 625                 fsl,pins = <
 626                         MX6QDL_PAD_NANDF_CS1__GPIO6_IO14        0x100b0
 627                         MX6QDL_PAD_NANDF_CS2__GPIO6_IO15        0x030b0
 628                         MX6QDL_PAD_NANDF_CS3__GPIO6_IO16        0x030b0
 629                         MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT      0x000b0
 630                 >;
 631         };
 632 };
 633
 634 &ipu1_di0_disp0 {
 635         remote-endpoint = <&lcd_display_in>;
 636 };
 637
 638 &ldb {
 639         status = "okay";
 640
 641         lvds-channel@0 {
 642                 status = "okay";
 643
 644                 port@4 {
 645                         reg = <4>;
 646
 647                         lvds0_out: endpoint {
 648                                 remote-endpoint = <&panel_in_lvds0>;
 649                         };
 650                 };
 651         };
 652
 653         lvds-channel@1 {
 654                 fsl,data-mapping = "spwg";
 655                 fsl,data-width = <18>;
 656                 status = "okay";
 657
 658                 port@4 {
 659                         reg = <4>;
 660
 661                         lvds1_out: endpoint {
 662                                 remote-endpoint = <&panel_in_lvds1>;
 663                         };
 664                 };
 665         };
 666 };
 667
 668 &pcie {
 669         pinctrl-names = "default";
 670         pinctrl-0 = <&pinctrl_pcie>;
 671         reset-gpio = <&gpio6 31 GPIO_ACTIVE_LOW>;
 672         status = "okay";
 673 };
 674
 675 &pwm1 {
 676         pinctrl-names = "default";
 677         pinctrl-0 = <&pinctrl_pwm1>;
 678         status = "okay";
 679 };
 680
 681 &pwm3 {
 682         pinctrl-names = "default";
 683         pinctrl-0 = <&pinctrl_pwm3>;
 684         status = "okay";
 685 };
 686
 687 &pwm4 {
 688         pinctrl-names = "default";
 689         pinctrl-0 = <&pinctrl_pwm4>;
 690         status = "okay";
 691 };
 692
 693 &ssi1 {
 694         status = "okay";
 695 };
 696
 697 &uart1 {
 698         pinctrl-names = "default";
 699         pinctrl-0 = <&pinctrl_uart1>;
 700         status = "okay";
 701 };
 702
 703 &uart2 {
 704         pinctrl-names = "default";
 705         pinctrl-0 = <&pinctrl_uart2>;
 706         status = "okay";
 707 };
 708
 709 &uart3 {
 710         pinctrl-names = "default";
 711         pinctrl-0 = <&pinctrl_uart3>;
 712         uart-has-rtscts;
 713         status = "okay";
 714 };
 715
 716 &usbh1 {
 717         vbus-supply = <&reg_usb_h1_vbus>;
 718         status = "okay";
 719 };
 720
 721 &usbotg {
 722         vbus-supply = <&reg_usb_otg_vbus>;
 723         pinctrl-names = "default";
 724         pinctrl-0 = <&pinctrl_usbotg>;
 725         disable-over-current;
 726         status = "okay";
 727 };
 728
 729 &usdhc2 {
 730         pinctrl-names = "default";
 731         pinctrl-0 = <&pinctrl_usdhc2>;
 732         bus-width = <4>;
 733         non-removable;
 734         vmmc-supply = <&reg_wlan_vmmc>;
 735         cap-power-off-card;
 736         keep-power-in-suspend;
 737         status = "okay";
 738
 739         #address-cells = <1>;
 740         #size-cells = <0>;
 741         wlcore: wlcore@2 {
 742                 compatible = "ti,wl1271";
 743                 reg = <2>;
 744                 interrupt-parent = <&gpio6>;
 745                 interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
 746                 ref-clock-frequency = <38400000>;
 747         };
 748 };
 749
 750 &usdhc3 {
 751         pinctrl-names = "default";
 752         pinctrl-0 = <&pinctrl_usdhc3>;
 753         cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
 754         bus-width = <4>;
 755         vmmc-supply = <&reg_3p3v>;
 756         status = "okay";
 757 };
 758
 759 &usdhc4 {
 760         pinctrl-names = "default";
 761         pinctrl-0 = <&pinctrl_usdhc4>;
 762         bus-width = <8>;
 763         non-removable;
 764         vmmc-supply = <&reg_1p8v>;
 765         keep-power-in-suspend;
 766         status = "okay";
 767 };