| blob | 6d7bf64961170f5e2e23b989e06f5894dfb1b59e |
1 /*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
13 #include <dt-bindings/clock/imx6qdl-clock.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 / {
17 #address-cells = <1>;
18 #size-cells = <1>;
19 /*
20 * The decompressor and also some bootloaders rely on a
21 * pre-existing /chosen node to be available to insert the
22 * command line and merge other ATAGS info.
23 * Also for U-Boot there must be a pre-existing /memory node.
24 */
25 chosen {};
26 memory { device_type = "memory"; reg = <0 0>; };
28 aliases {
29 ethernet0 = &fec;
30 can0 = &can1;
31 can1 = &can2;
32 gpio0 = &gpio1;
33 gpio1 = &gpio2;
34 gpio2 = &gpio3;
35 gpio3 = &gpio4;
36 gpio4 = &gpio5;
37 gpio5 = &gpio6;
38 gpio6 = &gpio7;
39 i2c0 = &i2c1;
40 i2c1 = &i2c2;
41 i2c2 = &i2c3;
42 ipu0 = &ipu1;
43 mmc0 = &usdhc1;
44 mmc1 = &usdhc2;
45 mmc2 = &usdhc3;
46 mmc3 = &usdhc4;
47 serial0 = &uart1;
48 serial1 = &uart2;
49 serial2 = &uart3;
50 serial3 = &uart4;
51 serial4 = &uart5;
52 spi0 = &ecspi1;
53 spi1 = &ecspi2;
54 spi2 = &ecspi3;
55 spi3 = &ecspi4;
56 usbphy0 = &usbphy1;
57 usbphy1 = &usbphy2;
58 };
60 clocks {
61 #address-cells = <1>;
62 #size-cells = <0>;
64 ckil {
65 compatible = "fsl,imx-ckil", "fixed-clock";
66 #clock-cells = <0>;
67 clock-frequency = <32768>;
68 };
70 ckih1 {
71 compatible = "fsl,imx-ckih1", "fixed-clock";
72 #clock-cells = <0>;
73 clock-frequency = <0>;
74 };
76 osc {
77 compatible = "fsl,imx-osc", "fixed-clock";
78 #clock-cells = <0>;
79 clock-frequency = <24000000>;
80 };
81 };
83 soc {
84 #address-cells = <1>;
85 #size-cells = <1>;
86 compatible = "simple-bus";
87 interrupt-parent = <&gpc>;
88 ranges;
90 dma_apbh: dma-apbh@00110000 {
91 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
92 reg = <0x00110000 0x2000>;
93 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
94 <0 13 IRQ_TYPE_LEVEL_HIGH>,
95 <0 13 IRQ_TYPE_LEVEL_HIGH>,
96 <0 13 IRQ_TYPE_LEVEL_HIGH>;
97 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
98 #dma-cells = <1>;
99 dma-channels = <4>;
100 clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
101 };
103 gpmi: gpmi-nand@00112000 {
104 compatible = "fsl,imx6q-gpmi-nand";
105 #address-cells = <1>;
106 #size-cells = <1>;
107 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
108 reg-names = "gpmi-nand", "bch";
109 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
110 interrupt-names = "bch";
111 clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
112 <&clks IMX6QDL_CLK_GPMI_APB>,
113 <&clks IMX6QDL_CLK_GPMI_BCH>,
114 <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
115 <&clks IMX6QDL_CLK_PER1_BCH>;
116 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
117 "gpmi_bch_apb", "per1_bch";
118 dmas = <&dma_apbh 0>;
119 dma-names = "rx-tx";
120 status = "disabled";
121 };
123 hdmi: hdmi@0120000 {
124 #address-cells = <1>;
125 #size-cells = <0>;
126 reg = <0x00120000 0x9000>;
127 interrupts = <0 115 0x04>;
128 gpr = <&gpr>;
129 clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
130 <&clks IMX6QDL_CLK_HDMI_ISFR>;
131 clock-names = "iahb", "isfr";
132 status = "disabled";
134 port@0 {
135 reg = <0>;
137 hdmi_mux_0: endpoint {
138 remote-endpoint = <&ipu1_di0_hdmi>;
139 };
140 };
142 port@1 {
143 reg = <1>;
145 hdmi_mux_1: endpoint {
146 remote-endpoint = <&ipu1_di1_hdmi>;
147 };
148 };
149 };
151 gpu_3d: gpu@00130000 {
152 compatible = "vivante,gc";
153 reg = <0x00130000 0x4000>;
154 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
155 clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,
156 <&clks IMX6QDL_CLK_GPU3D_CORE>,
157 <&clks IMX6QDL_CLK_GPU3D_SHADER>;
158 clock-names = "bus", "core", "shader";
159 power-domains = <&gpc 1>;
160 };
162 gpu_2d: gpu@00134000 {
163 compatible = "vivante,gc";
164 reg = <0x00134000 0x4000>;
165 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
166 clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>,
167 <&clks IMX6QDL_CLK_GPU2D_CORE>;
168 clock-names = "bus", "core";
169 power-domains = <&gpc 1>;
170 };
172 timer@00a00600 {
173 compatible = "arm,cortex-a9-twd-timer";
174 reg = <0x00a00600 0x20>;
175 interrupts = <1 13 0xf01>;
176 interrupt-parent = <&intc>;
177 clocks = <&clks IMX6QDL_CLK_TWD>;
178 };
180 intc: interrupt-controller@00a01000 {
181 compatible = "arm,cortex-a9-gic";
182 #interrupt-cells = <3>;
183 interrupt-controller;
184 reg = <0x00a01000 0x1000>,
185 <0x00a00100 0x100>;
186 interrupt-parent = <&intc>;
187 };
189 L2: l2-cache@00a02000 {
190 compatible = "arm,pl310-cache";
191 reg = <0x00a02000 0x1000>;
192 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
193 cache-unified;
194 cache-level = <2>;
195 arm,tag-latency = <4 2 3>;
196 arm,data-latency = <4 2 3>;
197 arm,shared-override;
198 };
200 pcie: pcie@0x01000000 {
201 compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
202 reg = <0x01ffc000 0x04000>,
203 <0x01f00000 0x80000>;
204 reg-names = "dbi", "config";
205 #address-cells = <3>;
206 #size-cells = <2>;
207 device_type = "pci";
208 ranges = <0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
209 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
210 num-lanes = <1>;
211 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
212 interrupt-names = "msi";
213 #interrupt-cells = <1>;
214 interrupt-map-mask = <0 0 0 0x7>;
215 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
216 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
217 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
218 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
220 <&clks IMX6QDL_CLK_LVDS1_GATE>,
221 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
222 clock-names = "pcie", "pcie_bus", "pcie_phy";
223 status = "disabled";
224 };
226 pmu {
227 compatible = "arm,cortex-a9-pmu";
228 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
229 };
231 aips-bus@02000000 { /* AIPS1 */
232 compatible = "fsl,aips-bus", "simple-bus";
233 #address-cells = <1>;
234 #size-cells = <1>;
235 reg = <0x02000000 0x100000>;
236 ranges;
238 spba-bus@02000000 {
239 compatible = "fsl,spba-bus", "simple-bus";
240 #address-cells = <1>;
241 #size-cells = <1>;
242 reg = <0x02000000 0x40000>;
243 ranges;
245 spdif: spdif@02004000 {
246 compatible = "fsl,imx35-spdif";
247 reg = <0x02004000 0x4000>;
248 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
249 dmas = <&sdma 14 18 0>,
250 <&sdma 15 18 0>;
251 dma-names = "rx", "tx";
252 clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>,
253 <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>,
254 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>,
255 <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>,
256 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>;
257 clock-names = "core", "rxtx0",
258 "rxtx1", "rxtx2",
259 "rxtx3", "rxtx4",
260 "rxtx5", "rxtx6",
261 "rxtx7", "spba";
262 status = "disabled";
263 };
265 ecspi1: ecspi@02008000 {
266 #address-cells = <1>;
267 #size-cells = <0>;
268 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
269 reg = <0x02008000 0x4000>;
270 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
271 clocks = <&clks IMX6QDL_CLK_ECSPI1>,
272 <&clks IMX6QDL_CLK_ECSPI1>;
273 clock-names = "ipg", "per";
274 dmas = <&sdma 3 8 1>, <&sdma 4 8 2>;
275 dma-names = "rx", "tx";
276 status = "disabled";
277 };
279 ecspi2: ecspi@0200c000 {
280 #address-cells = <1>;
281 #size-cells = <0>;
282 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
283 reg = <0x0200c000 0x4000>;
284 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
285 clocks = <&clks IMX6QDL_CLK_ECSPI2>,
286 <&clks IMX6QDL_CLK_ECSPI2>;
287 clock-names = "ipg", "per";
288 dmas = <&sdma 5 8 1>, <&sdma 6 8 2>;
289 dma-names = "rx", "tx";
290 status = "disabled";
291 };
293 ecspi3: ecspi@02010000 {
294 #address-cells = <1>;
295 #size-cells = <0>;
296 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
297 reg = <0x02010000 0x4000>;
298 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
299 clocks = <&clks IMX6QDL_CLK_ECSPI3>,
300 <&clks IMX6QDL_CLK_ECSPI3>;
301 clock-names = "ipg", "per";
302 dmas = <&sdma 7 8 1>, <&sdma 8 8 2>;
303 dma-names = "rx", "tx";
304 status = "disabled";
305 };
307 ecspi4: ecspi@02014000 {
308 #address-cells = <1>;
309 #size-cells = <0>;
310 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
311 reg = <0x02014000 0x4000>;
312 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
313 clocks = <&clks IMX6QDL_CLK_ECSPI4>,
314 <&clks IMX6QDL_CLK_ECSPI4>;
315 clock-names = "ipg", "per";
316 dmas = <&sdma 9 8 1>, <&sdma 10 8 2>;
317 dma-names = "rx", "tx";
318 status = "disabled";
319 };
321 uart1: serial@02020000 {
322 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
323 reg = <0x02020000 0x4000>;
324 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
325 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
326 <&clks IMX6QDL_CLK_UART_SERIAL>;
327 clock-names = "ipg", "per";
328 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
329 dma-names = "rx", "tx";
330 status = "disabled";
331 };
333 esai: esai@02024000 {
334 #sound-dai-cells = <0>;
335 compatible = "fsl,imx35-esai";
336 reg = <0x02024000 0x4000>;
337 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
338 clocks = <&clks IMX6QDL_CLK_ESAI_IPG>,
339 <&clks IMX6QDL_CLK_ESAI_MEM>,
340 <&clks IMX6QDL_CLK_ESAI_EXTAL>,
341 <&clks IMX6QDL_CLK_ESAI_IPG>,
342 <&clks IMX6QDL_CLK_SPBA>;
343 clock-names = "core", "mem", "extal", "fsys", "spba";
344 dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;
345 dma-names = "rx", "tx";
346 status = "disabled";
347 };
349 ssi1: ssi@02028000 {
350 #sound-dai-cells = <0>;
351 compatible = "fsl,imx6q-ssi",
352 "fsl,imx51-ssi";
353 reg = <0x02028000 0x4000>;
354 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
355 clocks = <&clks IMX6QDL_CLK_SSI1_IPG>,
356 <&clks IMX6QDL_CLK_SSI1>;
357 clock-names = "ipg", "baud";
358 dmas = <&sdma 37 1 0>,
359 <&sdma 38 1 0>;
360 dma-names = "rx", "tx";
361 fsl,fifo-depth = <15>;
362 status = "disabled";
363 };
365 ssi2: ssi@0202c000 {
366 #sound-dai-cells = <0>;
367 compatible = "fsl,imx6q-ssi",
368 "fsl,imx51-ssi";
369 reg = <0x0202c000 0x4000>;
370 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
371 clocks = <&clks IMX6QDL_CLK_SSI2_IPG>,
372 <&clks IMX6QDL_CLK_SSI2>;
373 clock-names = "ipg", "baud";
374 dmas = <&sdma 41 1 0>,
375 <&sdma 42 1 0>;
376 dma-names = "rx", "tx";
377 fsl,fifo-depth = <15>;
378 status = "disabled";
379 };
381 ssi3: ssi@02030000 {
382 #sound-dai-cells = <0>;
383 compatible = "fsl,imx6q-ssi",
384 "fsl,imx51-ssi";
385 reg = <0x02030000 0x4000>;
386 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&clks IMX6QDL_CLK_SSI3_IPG>,
388 <&clks IMX6QDL_CLK_SSI3>;
389 clock-names = "ipg", "baud";
390 dmas = <&sdma 45 1 0>,
391 <&sdma 46 1 0>;
392 dma-names = "rx", "tx";
393 fsl,fifo-depth = <15>;
394 status = "disabled";
395 };
397 asrc: asrc@02034000 {
398 compatible = "fsl,imx53-asrc";
399 reg = <0x02034000 0x4000>;
400 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
401 clocks = <&clks IMX6QDL_CLK_ASRC_IPG>,
402 <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>,
403 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
404 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
405 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
406 <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>,
407 <&clks IMX6QDL_CLK_SPBA>;
408 clock-names = "mem", "ipg", "asrck_0",
409 "asrck_1", "asrck_2", "asrck_3", "asrck_4",
410 "asrck_5", "asrck_6", "asrck_7", "asrck_8",
411 "asrck_9", "asrck_a", "asrck_b", "asrck_c",
412 "asrck_d", "asrck_e", "asrck_f", "spba";
413 dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
414 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
415 dma-names = "rxa", "rxb", "rxc",
416 "txa", "txb", "txc";
417 fsl,asrc-rate = <48000>;
418 fsl,asrc-width = <16>;
419 status = "okay";
420 };
422 spba@0203c000 {
423 reg = <0x0203c000 0x4000>;
424 };
425 };
427 vpu: vpu@02040000 {
428 compatible = "cnm,coda960";
429 reg = <0x02040000 0x3c000>;
430 interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
431 <0 3 IRQ_TYPE_LEVEL_HIGH>;
432 interrupt-names = "bit", "jpeg";
433 clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
434 <&clks IMX6QDL_CLK_MMDC_CH0_AXI>;
435 clock-names = "per", "ahb";
436 power-domains = <&gpc 1>;
437 resets = <&src 1>;
438 iram = <&ocram>;
439 };
441 aipstz@0207c000 { /* AIPSTZ1 */
442 reg = <0x0207c000 0x4000>;
443 };
445 pwm1: pwm@02080000 {
446 #pwm-cells = <2>;
447 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
448 reg = <0x02080000 0x4000>;
449 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
450 clocks = <&clks IMX6QDL_CLK_IPG>,
451 <&clks IMX6QDL_CLK_PWM1>;
452 clock-names = "ipg", "per";
453 status = "disabled";
454 };
456 pwm2: pwm@02084000 {
457 #pwm-cells = <2>;
458 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
459 reg = <0x02084000 0x4000>;
460 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
461 clocks = <&clks IMX6QDL_CLK_IPG>,
462 <&clks IMX6QDL_CLK_PWM2>;
463 clock-names = "ipg", "per";
464 status = "disabled";
465 };
467 pwm3: pwm@02088000 {
468 #pwm-cells = <2>;
469 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
470 reg = <0x02088000 0x4000>;
471 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
472 clocks = <&clks IMX6QDL_CLK_IPG>,
473 <&clks IMX6QDL_CLK_PWM3>;
474 clock-names = "ipg", "per";
475 status = "disabled";
476 };
478 pwm4: pwm@0208c000 {
479 #pwm-cells = <2>;
480 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
481 reg = <0x0208c000 0x4000>;
482 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
483 clocks = <&clks IMX6QDL_CLK_IPG>,
484 <&clks IMX6QDL_CLK_PWM4>;
485 clock-names = "ipg", "per";
486 status = "disabled";
487 };
489 can1: flexcan@02090000 {
490 compatible = "fsl,imx6q-flexcan";
491 reg = <0x02090000 0x4000>;
492 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
493 clocks = <&clks IMX6QDL_CLK_CAN1_IPG>,
494 <&clks IMX6QDL_CLK_CAN1_SERIAL>;
495 clock-names = "ipg", "per";
496 status = "disabled";
497 };
499 can2: flexcan@02094000 {
500 compatible = "fsl,imx6q-flexcan";
501 reg = <0x02094000 0x4000>;
502 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
503 clocks = <&clks IMX6QDL_CLK_CAN2_IPG>,
504 <&clks IMX6QDL_CLK_CAN2_SERIAL>;
505 clock-names = "ipg", "per";
506 status = "disabled";
507 };
509 gpt: gpt@02098000 {
510 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
511 reg = <0x02098000 0x4000>;
512 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
513 clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
514 <&clks IMX6QDL_CLK_GPT_IPG_PER>,
515 <&clks IMX6QDL_CLK_GPT_3M>;
516 clock-names = "ipg", "per", "osc_per";
517 };
519 gpio1: gpio@0209c000 {
520 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
521 reg = <0x0209c000 0x4000>;
522 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
523 <0 67 IRQ_TYPE_LEVEL_HIGH>;
524 gpio-controller;
525 #gpio-cells = <2>;
526 interrupt-controller;
527 #interrupt-cells = <2>;
528 };
530 gpio2: gpio@020a0000 {
531 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
532 reg = <0x020a0000 0x4000>;
533 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
534 <0 69 IRQ_TYPE_LEVEL_HIGH>;
535 gpio-controller;
536 #gpio-cells = <2>;
537 interrupt-controller;
538 #interrupt-cells = <2>;
539 };
541 gpio3: gpio@020a4000 {
542 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
543 reg = <0x020a4000 0x4000>;
544 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
545 <0 71 IRQ_TYPE_LEVEL_HIGH>;
546 gpio-controller;
547 #gpio-cells = <2>;
548 interrupt-controller;
549 #interrupt-cells = <2>;
550 };
552 gpio4: gpio@020a8000 {
553 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
554 reg = <0x020a8000 0x4000>;
555 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
556 <0 73 IRQ_TYPE_LEVEL_HIGH>;
557 gpio-controller;
558 #gpio-cells = <2>;
559 interrupt-controller;
560 #interrupt-cells = <2>;
561 };
563 gpio5: gpio@020ac000 {
564 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
565 reg = <0x020ac000 0x4000>;
566 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
567 <0 75 IRQ_TYPE_LEVEL_HIGH>;
568 gpio-controller;
569 #gpio-cells = <2>;
570 interrupt-controller;
571 #interrupt-cells = <2>;
572 };
574 gpio6: gpio@020b0000 {
575 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
576 reg = <0x020b0000 0x4000>;
577 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
578 <0 77 IRQ_TYPE_LEVEL_HIGH>;
579 gpio-controller;
580 #gpio-cells = <2>;
581 interrupt-controller;
582 #interrupt-cells = <2>;
583 };
585 gpio7: gpio@020b4000 {
586 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
587 reg = <0x020b4000 0x4000>;
588 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
589 <0 79 IRQ_TYPE_LEVEL_HIGH>;
590 gpio-controller;
591 #gpio-cells = <2>;
592 interrupt-controller;
593 #interrupt-cells = <2>;
594 };
596 kpp: kpp@020b8000 {
597 compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
598 reg = <0x020b8000 0x4000>;
599 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
600 clocks = <&clks IMX6QDL_CLK_IPG>;
601 status = "disabled";
602 };
604 wdog1: wdog@020bc000 {
605 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
606 reg = <0x020bc000 0x4000>;
607 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
608 clocks = <&clks IMX6QDL_CLK_DUMMY>;
609 };
611 wdog2: wdog@020c0000 {
612 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
613 reg = <0x020c0000 0x4000>;
614 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
615 clocks = <&clks IMX6QDL_CLK_DUMMY>;
616 status = "disabled";
617 };
619 clks: ccm@020c4000 {
620 compatible = "fsl,imx6q-ccm";
621 reg = <0x020c4000 0x4000>;
622 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
623 <0 88 IRQ_TYPE_LEVEL_HIGH>;
624 #clock-cells = <1>;
625 };
627 anatop: anatop@020c8000 {
628 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
629 reg = <0x020c8000 0x1000>;
630 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
631 <0 54 IRQ_TYPE_LEVEL_HIGH>,
632 <0 127 IRQ_TYPE_LEVEL_HIGH>;
634 regulator-1p1 {
635 compatible = "fsl,anatop-regulator";
636 regulator-name = "vdd1p1";
637 regulator-min-microvolt = <1000000>;
638 regulator-max-microvolt = <1200000>;
639 regulator-always-on;
640 anatop-reg-offset = <0x110>;
641 anatop-vol-bit-shift = <8>;
642 anatop-vol-bit-width = <5>;
643 anatop-min-bit-val = <4>;
644 anatop-min-voltage = <800000>;
645 anatop-max-voltage = <1375000>;
646 };
648 regulator-3p0 {
649 compatible = "fsl,anatop-regulator";
650 regulator-name = "vdd3p0";
651 regulator-min-microvolt = <2800000>;
652 regulator-max-microvolt = <3150000>;
653 regulator-always-on;
654 anatop-reg-offset = <0x120>;
655 anatop-vol-bit-shift = <8>;
656 anatop-vol-bit-width = <5>;
657 anatop-min-bit-val = <0>;
658 anatop-min-voltage = <2625000>;
659 anatop-max-voltage = <3400000>;
660 };
662 regulator-2p5 {
663 compatible = "fsl,anatop-regulator";
664 regulator-name = "vdd2p5";
665 regulator-min-microvolt = <2250000>;
666 regulator-max-microvolt = <2750000>;
667 regulator-always-on;
668 anatop-reg-offset = <0x130>;
669 anatop-vol-bit-shift = <8>;
670 anatop-vol-bit-width = <5>;
671 anatop-min-bit-val = <0>;
672 anatop-min-voltage = <2100000>;
673 anatop-max-voltage = <2875000>;
674 };
676 reg_arm: regulator-vddcore {
677 compatible = "fsl,anatop-regulator";
678 regulator-name = "vddarm";
679 regulator-min-microvolt = <725000>;
680 regulator-max-microvolt = <1450000>;
681 regulator-always-on;
682 anatop-reg-offset = <0x140>;
683 anatop-vol-bit-shift = <0>;
684 anatop-vol-bit-width = <5>;
685 anatop-delay-reg-offset = <0x170>;
686 anatop-delay-bit-shift = <24>;
687 anatop-delay-bit-width = <2>;
688 anatop-min-bit-val = <1>;
689 anatop-min-voltage = <725000>;
690 anatop-max-voltage = <1450000>;
691 };
693 reg_pu: regulator-vddpu {
694 compatible = "fsl,anatop-regulator";
695 regulator-name = "vddpu";
696 regulator-min-microvolt = <725000>;
697 regulator-max-microvolt = <1450000>;
698 regulator-enable-ramp-delay = <150>;
699 anatop-reg-offset = <0x140>;
700 anatop-vol-bit-shift = <9>;
701 anatop-vol-bit-width = <5>;
702 anatop-delay-reg-offset = <0x170>;
703 anatop-delay-bit-shift = <26>;
704 anatop-delay-bit-width = <2>;
705 anatop-min-bit-val = <1>;
706 anatop-min-voltage = <725000>;
707 anatop-max-voltage = <1450000>;
708 };
710 reg_soc: regulator-vddsoc {
711 compatible = "fsl,anatop-regulator";
712 regulator-name = "vddsoc";
713 regulator-min-microvolt = <725000>;
714 regulator-max-microvolt = <1450000>;
715 regulator-always-on;
716 anatop-reg-offset = <0x140>;
717 anatop-vol-bit-shift = <18>;
718 anatop-vol-bit-width = <5>;
719 anatop-delay-reg-offset = <0x170>;
720 anatop-delay-bit-shift = <28>;
721 anatop-delay-bit-width = <2>;
722 anatop-min-bit-val = <1>;
723 anatop-min-voltage = <725000>;
724 anatop-max-voltage = <1450000>;
725 };
726 };
728 tempmon: tempmon {
729 compatible = "fsl,imx6q-tempmon";
730 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
731 fsl,tempmon = <&anatop>;
732 fsl,tempmon-data = <&ocotp>;
733 clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
734 };
736 usbphy1: usbphy@020c9000 {
737 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
738 reg = <0x020c9000 0x1000>;
739 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
740 clocks = <&clks IMX6QDL_CLK_USBPHY1>;
741 fsl,anatop = <&anatop>;
742 };
744 usbphy2: usbphy@020ca000 {
745 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
746 reg = <0x020ca000 0x1000>;
747 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
748 clocks = <&clks IMX6QDL_CLK_USBPHY2>;
749 fsl,anatop = <&anatop>;
750 };
752 snvs: snvs@020cc000 {
753 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
754 reg = <0x020cc000 0x4000>;
756 snvs_rtc: snvs-rtc-lp {
757 compatible = "fsl,sec-v4.0-mon-rtc-lp";
758 regmap = <&snvs>;
759 offset = <0x34>;
760 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
761 <0 20 IRQ_TYPE_LEVEL_HIGH>;
762 };
764 snvs_poweroff: snvs-poweroff {
765 compatible = "syscon-poweroff";
766 regmap = <&snvs>;
767 offset = <0x38>;
768 mask = <0x60>;
769 status = "disabled";
770 };
771 };
773 epit1: epit@020d0000 { /* EPIT1 */
774 reg = <0x020d0000 0x4000>;
775 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
776 };
778 epit2: epit@020d4000 { /* EPIT2 */
779 reg = <0x020d4000 0x4000>;
780 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
781 };
783 src: src@020d8000 {
784 compatible = "fsl,imx6q-src", "fsl,imx51-src";
785 reg = <0x020d8000 0x4000>;
786 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
787 <0 96 IRQ_TYPE_LEVEL_HIGH>;
788 #reset-cells = <1>;
789 };
791 gpc: gpc@020dc000 {
792 compatible = "fsl,imx6q-gpc";
793 reg = <0x020dc000 0x4000>;
794 interrupt-controller;
795 #interrupt-cells = <3>;
796 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
797 <0 90 IRQ_TYPE_LEVEL_HIGH>;
798 interrupt-parent = <&intc>;
799 pu-supply = <®_pu>;
800 clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
801 <&clks IMX6QDL_CLK_GPU3D_SHADER>,
802 <&clks IMX6QDL_CLK_GPU2D_CORE>,
803 <&clks IMX6QDL_CLK_GPU2D_AXI>,
804 <&clks IMX6QDL_CLK_OPENVG_AXI>,
805 <&clks IMX6QDL_CLK_VPU_AXI>;
806 #power-domain-cells = <1>;
807 };
809 gpr: iomuxc-gpr@020e0000 {
810 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
811 reg = <0x020e0000 0x38>;
812 };
814 iomuxc: iomuxc@020e0000 {
815 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
816 reg = <0x020e0000 0x4000>;
817 };
819 ldb: ldb {
820 #address-cells = <1>;
821 #size-cells = <0>;
822 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
823 gpr = <&gpr>;
824 status = "disabled";
826 lvds-channel@0 {
827 #address-cells = <1>;
828 #size-cells = <0>;
829 reg = <0>;
830 status = "disabled";
832 port@0 {
833 reg = <0>;
835 lvds0_mux_0: endpoint {
836 remote-endpoint = <&ipu1_di0_lvds0>;
837 };
838 };
840 port@1 {
841 reg = <1>;
843 lvds0_mux_1: endpoint {
844 remote-endpoint = <&ipu1_di1_lvds0>;
845 };
846 };
847 };
849 lvds-channel@1 {
850 #address-cells = <1>;
851 #size-cells = <0>;
852 reg = <1>;
853 status = "disabled";
855 port@0 {
856 reg = <0>;
858 lvds1_mux_0: endpoint {
859 remote-endpoint = <&ipu1_di0_lvds1>;
860 };
861 };
863 port@1 {
864 reg = <1>;
866 lvds1_mux_1: endpoint {
867 remote-endpoint = <&ipu1_di1_lvds1>;
868 };
869 };
870 };
871 };
873 dcic1: dcic@020e4000 {
874 reg = <0x020e4000 0x4000>;
875 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
876 };
878 dcic2: dcic@020e8000 {
879 reg = <0x020e8000 0x4000>;
880 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
881 };
883 sdma: sdma@020ec000 {
884 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
885 reg = <0x020ec000 0x4000>;
886 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
887 clocks = <&clks IMX6QDL_CLK_SDMA>,
888 <&clks IMX6QDL_CLK_SDMA>;
889 clock-names = "ipg", "ahb";
890 #dma-cells = <3>;
891 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
892 };
893 };
895 aips-bus@02100000 { /* AIPS2 */
896 compatible = "fsl,aips-bus", "simple-bus";
897 #address-cells = <1>;
898 #size-cells = <1>;
899 reg = <0x02100000 0x100000>;
900 ranges;
902 crypto: caam@2100000 {
903 compatible = "fsl,sec-v4.0";
904 fsl,sec-era = <4>;
905 #address-cells = <1>;
906 #size-cells = <1>;
907 reg = <0x2100000 0x10000>;
908 ranges = <0 0x2100000 0x10000>;
909 clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
910 <&clks IMX6QDL_CLK_CAAM_ACLK>,
911 <&clks IMX6QDL_CLK_CAAM_IPG>,
912 <&clks IMX6QDL_CLK_EIM_SLOW>;
913 clock-names = "mem", "aclk", "ipg", "emi_slow";
915 sec_jr0: jr0@1000 {
916 compatible = "fsl,sec-v4.0-job-ring";
917 reg = <0x1000 0x1000>;
918 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
919 };
921 sec_jr1: jr1@2000 {
922 compatible = "fsl,sec-v4.0-job-ring";
923 reg = <0x2000 0x1000>;
924 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
925 };
926 };
928 aipstz@0217c000 { /* AIPSTZ2 */
929 reg = <0x0217c000 0x4000>;
930 };
932 usbotg: usb@02184000 {
933 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
934 reg = <0x02184000 0x200>;
935 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
936 clocks = <&clks IMX6QDL_CLK_USBOH3>;
937 fsl,usbphy = <&usbphy1>;
938 fsl,usbmisc = <&usbmisc 0>;
939 ahb-burst-config = <0x0>;
940 tx-burst-size-dword = <0x10>;
941 rx-burst-size-dword = <0x10>;
942 status = "disabled";
943 };
945 usbh1: usb@02184200 {
946 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
947 reg = <0x02184200 0x200>;
948 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
949 clocks = <&clks IMX6QDL_CLK_USBOH3>;
950 fsl,usbphy = <&usbphy2>;
951 fsl,usbmisc = <&usbmisc 1>;
952 dr_mode = "host";
953 ahb-burst-config = <0x0>;
954 tx-burst-size-dword = <0x10>;
955 rx-burst-size-dword = <0x10>;
956 status = "disabled";
957 };
959 usbh2: usb@02184400 {
960 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
961 reg = <0x02184400 0x200>;
962 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
963 clocks = <&clks IMX6QDL_CLK_USBOH3>;
964 fsl,usbmisc = <&usbmisc 2>;
965 dr_mode = "host";
966 ahb-burst-config = <0x0>;
967 tx-burst-size-dword = <0x10>;
968 rx-burst-size-dword = <0x10>;
969 status = "disabled";
970 };
972 usbh3: usb@02184600 {
973 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
974 reg = <0x02184600 0x200>;
975 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
976 clocks = <&clks IMX6QDL_CLK_USBOH3>;
977 fsl,usbmisc = <&usbmisc 3>;
978 dr_mode = "host";
979 ahb-burst-config = <0x0>;
980 tx-burst-size-dword = <0x10>;
981 rx-burst-size-dword = <0x10>;
982 status = "disabled";
983 };
985 usbmisc: usbmisc@02184800 {
986 #index-cells = <1>;
987 compatible = "fsl,imx6q-usbmisc";
988 reg = <0x02184800 0x200>;
989 clocks = <&clks IMX6QDL_CLK_USBOH3>;
990 };
992 fec: ethernet@02188000 {
993 compatible = "fsl,imx6q-fec";
994 reg = <0x02188000 0x4000>;
995 interrupts-extended =
996 <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
997 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
998 clocks = <&clks IMX6QDL_CLK_ENET>,
999 <&clks IMX6QDL_CLK_ENET>,
1000 <&clks IMX6QDL_CLK_ENET_REF>;
1001 clock-names = "ipg", "ahb", "ptp";
1002 status = "disabled";
1003 };
1005 mlb@0218c000 {
1006 reg = <0x0218c000 0x4000>;
1007 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
1008 <0 117 IRQ_TYPE_LEVEL_HIGH>,
1009 <0 126 IRQ_TYPE_LEVEL_HIGH>;
1010 };
1012 usdhc1: usdhc@02190000 {
1013 compatible = "fsl,imx6q-usdhc";
1014 reg = <0x02190000 0x4000>;
1015 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
1016 clocks = <&clks IMX6QDL_CLK_USDHC1>,
1017 <&clks IMX6QDL_CLK_USDHC1>,
1018 <&clks IMX6QDL_CLK_USDHC1>;
1019 clock-names = "ipg", "ahb", "per";
1020 bus-width = <4>;
1021 status = "disabled";
1022 };
1024 usdhc2: usdhc@02194000 {
1025 compatible = "fsl,imx6q-usdhc";
1026 reg = <0x02194000 0x4000>;
1027 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
1028 clocks = <&clks IMX6QDL_CLK_USDHC2>,
1029 <&clks IMX6QDL_CLK_USDHC2>,
1030 <&clks IMX6QDL_CLK_USDHC2>;
1031 clock-names = "ipg", "ahb", "per";
1032 bus-width = <4>;
1033 status = "disabled";
1034 };
1036 usdhc3: usdhc@02198000 {
1037 compatible = "fsl,imx6q-usdhc";
1038 reg = <0x02198000 0x4000>;
1039 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
1040 clocks = <&clks IMX6QDL_CLK_USDHC3>,
1041 <&clks IMX6QDL_CLK_USDHC3>,
1042 <&clks IMX6QDL_CLK_USDHC3>;
1043 clock-names = "ipg", "ahb", "per";
1044 bus-width = <4>;
1045 status = "disabled";
1046 };
1048 usdhc4: usdhc@0219c000 {
1049 compatible = "fsl,imx6q-usdhc";
1050 reg = <0x0219c000 0x4000>;
1051 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
1052 clocks = <&clks IMX6QDL_CLK_USDHC4>,
1053 <&clks IMX6QDL_CLK_USDHC4>,
1054 <&clks IMX6QDL_CLK_USDHC4>;
1055 clock-names = "ipg", "ahb", "per";
1056 bus-width = <4>;
1057 status = "disabled";
1058 };
1060 i2c1: i2c@021a0000 {
1061 #address-cells = <1>;
1062 #size-cells = <0>;
1063 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1064 reg = <0x021a0000 0x4000>;
1065 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
1066 clocks = <&clks IMX6QDL_CLK_I2C1>;
1067 status = "disabled";
1068 };
1070 i2c2: i2c@021a4000 {
1071 #address-cells = <1>;
1072 #size-cells = <0>;
1073 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1074 reg = <0x021a4000 0x4000>;
1075 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
1076 clocks = <&clks IMX6QDL_CLK_I2C2>;
1077 status = "disabled";
1078 };
1080 i2c3: i2c@021a8000 {
1081 #address-cells = <1>;
1082 #size-cells = <0>;
1083 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1084 reg = <0x021a8000 0x4000>;
1085 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
1086 clocks = <&clks IMX6QDL_CLK_I2C3>;
1087 status = "disabled";
1088 };
1090 romcp@021ac000 {
1091 reg = <0x021ac000 0x4000>;
1092 };
1094 mmdc0: mmdc@021b0000 { /* MMDC0 */
1095 compatible = "fsl,imx6q-mmdc";
1096 reg = <0x021b0000 0x4000>;
1097 };
1099 mmdc1: mmdc@021b4000 { /* MMDC1 */
1100 reg = <0x021b4000 0x4000>;
1101 };
1103 weim: weim@021b8000 {
1104 #address-cells = <2>;
1105 #size-cells = <1>;
1106 compatible = "fsl,imx6q-weim";
1107 reg = <0x021b8000 0x4000>;
1108 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
1109 clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
1110 fsl,weim-cs-gpr = <&gpr>;
1111 status = "disabled";
1112 };
1114 ocotp: ocotp@021bc000 {
1115 compatible = "fsl,imx6q-ocotp", "syscon";
1116 reg = <0x021bc000 0x4000>;
1117 clocks = <&clks IMX6QDL_CLK_IIM>;
1118 };
1120 tzasc@021d0000 { /* TZASC1 */
1121 reg = <0x021d0000 0x4000>;
1122 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1123 };
1125 tzasc@021d4000 { /* TZASC2 */
1126 reg = <0x021d4000 0x4000>;
1127 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
1128 };
1130 audmux: audmux@021d8000 {
1131 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
1132 reg = <0x021d8000 0x4000>;
1133 status = "disabled";
1134 };
1136 mipi_csi: mipi@021dc000 {
1137 reg = <0x021dc000 0x4000>;
1138 };
1140 mipi_dsi: mipi@021e0000 {
1141 #address-cells = <1>;
1142 #size-cells = <0>;
1143 reg = <0x021e0000 0x4000>;
1144 status = "disabled";
1146 ports {
1147 #address-cells = <1>;
1148 #size-cells = <0>;
1150 port@0 {
1151 reg = <0>;
1153 mipi_mux_0: endpoint {
1154 remote-endpoint = <&ipu1_di0_mipi>;
1155 };
1156 };
1158 port@1 {
1159 reg = <1>;
1161 mipi_mux_1: endpoint {
1162 remote-endpoint = <&ipu1_di1_mipi>;
1163 };
1164 };
1165 };
1166 };
1168 vdoa@021e4000 {
1169 compatible = "fsl,imx6q-vdoa";
1170 reg = <0x021e4000 0x4000>;
1171 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
1172 clocks = <&clks IMX6QDL_CLK_VDOA>;
1173 };
1175 uart2: serial@021e8000 {
1176 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1177 reg = <0x021e8000 0x4000>;
1178 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
1179 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1180 <&clks IMX6QDL_CLK_UART_SERIAL>;
1181 clock-names = "ipg", "per";
1182 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1183 dma-names = "rx", "tx";
1184 status = "disabled";
1185 };
1187 uart3: serial@021ec000 {
1188 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1189 reg = <0x021ec000 0x4000>;
1190 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1191 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1192 <&clks IMX6QDL_CLK_UART_SERIAL>;
1193 clock-names = "ipg", "per";
1194 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1195 dma-names = "rx", "tx";
1196 status = "disabled";
1197 };
1199 uart4: serial@021f0000 {
1200 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1201 reg = <0x021f0000 0x4000>;
1202 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1203 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1204 <&clks IMX6QDL_CLK_UART_SERIAL>;
1205 clock-names = "ipg", "per";
1206 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1207 dma-names = "rx", "tx";
1208 status = "disabled";
1209 };
1211 uart5: serial@021f4000 {
1212 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1213 reg = <0x021f4000 0x4000>;
1214 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1215 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1216 <&clks IMX6QDL_CLK_UART_SERIAL>;
1217 clock-names = "ipg", "per";
1218 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1219 dma-names = "rx", "tx";
1220 status = "disabled";
1221 };
1222 };
1224 ipu1: ipu@02400000 {
1225 #address-cells = <1>;
1226 #size-cells = <0>;
1227 compatible = "fsl,imx6q-ipu";
1228 reg = <0x02400000 0x400000>;
1229 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1230 <0 5 IRQ_TYPE_LEVEL_HIGH>;
1231 clocks = <&clks IMX6QDL_CLK_IPU1>,
1232 <&clks IMX6QDL_CLK_IPU1_DI0>,
1233 <&clks IMX6QDL_CLK_IPU1_DI1>;
1234 clock-names = "bus", "di0", "di1";
1235 resets = <&src 2>;
1237 ipu1_csi0: port@0 {
1238 reg = <0>;
1239 };
1241 ipu1_csi1: port@1 {
1242 reg = <1>;
1243 };
1245 ipu1_di0: port@2 {
1246 #address-cells = <1>;
1247 #size-cells = <0>;
1248 reg = <2>;
1250 ipu1_di0_disp0: disp0-endpoint {
1251 };
1253 ipu1_di0_hdmi: hdmi-endpoint {
1254 remote-endpoint = <&hdmi_mux_0>;
1255 };
1257 ipu1_di0_mipi: mipi-endpoint {
1258 remote-endpoint = <&mipi_mux_0>;
1259 };
1261 ipu1_di0_lvds0: lvds0-endpoint {
1262 remote-endpoint = <&lvds0_mux_0>;
1263 };
1265 ipu1_di0_lvds1: lvds1-endpoint {
1266 remote-endpoint = <&lvds1_mux_0>;
1267 };
1268 };
1270 ipu1_di1: port@3 {
1271 #address-cells = <1>;
1272 #size-cells = <0>;
1273 reg = <3>;
1275 ipu1_di1_disp1: disp1-endpoint {
1276 };
1278 ipu1_di1_hdmi: hdmi-endpoint {
1279 remote-endpoint = <&hdmi_mux_1>;
1280 };
1282 ipu1_di1_mipi: mipi-endpoint {
1283 remote-endpoint = <&mipi_mux_1>;
1284 };
1286 ipu1_di1_lvds0: lvds0-endpoint {
1287 remote-endpoint = <&lvds0_mux_1>;
1288 };
1290 ipu1_di1_lvds1: lvds1-endpoint {
1291 remote-endpoint = <&lvds1_mux_1>;
1292 };
1293 };
1294 };
1295 };
1296 };