arch/arm/boot/dts/imx6sx-nitrogen6sx.dts

   1 /*
   2  * Copyright (C) 2016 Boundary Devices, Inc.
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License
  11  *     version 2 as published by the Free Software Foundation.
  12  *
  13  *     This file is distributed in the hope that it will be useful,
  14  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *     GNU General Public License for more details.
  17  *
  18  * Or, alternatively,
  19  *
  20  *  b) Permission is hereby granted, free of charge, to any person
  21  *     obtaining a copy of this software and associated documentation
  22  *     files (the "Software"), to deal in the Software without
  23  *     restriction, including without limitation the rights to use,
  24  *     copy, modify, merge, publish, distribute, sublicense, and/or
  25  *     sell copies of the Software, and to permit persons to whom the
  26  *     Software is furnished to do so, subject to the following
  27  *     conditions:
  28  *
  29  *     The above copyright notice and this permission notice shall be
  30  *     included in all copies or substantial portions of the Software.
  31  *
  32  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  33  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  34  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  35  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  36  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  37  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  38  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  39  *     OTHER DEALINGS IN THE SOFTWARE.
  40  */
  41
  42 /dts-v1/;
  43
  44 #include "imx6sx.dtsi"
  45
  46 / {
  47         model = "Boundary Devices i.MX6 SoloX Nitrogen6sx Board";
  48         compatible = "boundary,imx6sx-nitrogen6sx", "fsl,imx6sx";
  49
  50         aliases {
  51                 fb_lcd = &lcdif1;
  52                 t_lcd = &t_lcd;
  53         };
  54
  55         memory {
  56                 reg = <0x80000000 0x40000000>;
  57         };
  58
  59         backlight-lvds {
  60                 compatible = "pwm-backlight";
  61                 pwms = <&pwm4 0 5000000>;
  62                 brightness-levels = <0 4 8 16 32 64 128 255>;
  63                 default-brightness-level = <6>;
  64                 power-supply = <&reg_3p3v>;
  65         };
  66
  67         reg_1p8v: regulator-1p8v {
  68                 compatible = "regulator-fixed";
  69                 regulator-name = "1P8V";
  70                 regulator-min-microvolt = <1800000>;
  71                 regulator-max-microvolt = <1800000>;
  72                 regulator-always-on;
  73         };
  74
  75         reg_3p3v: regulator-3p3v {
  76                 compatible = "regulator-fixed";
  77                 regulator-name = "3P3V";
  78                 regulator-min-microvolt = <3300000>;
  79                 regulator-max-microvolt = <3300000>;
  80                 regulator-always-on;
  81         };
  82
  83         reg_can1_3v3: regulator-can1-3v3 {
  84                 compatible = "regulator-fixed";
  85                 regulator-name = "can1-3v3";
  86                 regulator-min-microvolt = <3300000>;
  87                 regulator-max-microvolt = <3300000>;
  88                 gpio = <&gpio4 27 GPIO_ACTIVE_LOW>;
  89         };
  90
  91         reg_can2_3v3: regulator-can2-3v3 {
  92                 compatible = "regulator-fixed";
  93                 regulator-name = "can2-3v3";
  94                 regulator-min-microvolt = <3300000>;
  95                 regulator-max-microvolt = <3300000>;
  96                 gpio = <&gpio4 24 GPIO_ACTIVE_LOW>;
  97         };
  98
  99         reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
 100                 pinctrl-names = "default";
 101                 pinctrl-0 = <&pinctrl_usbotg1_vbus>;
 102                 compatible = "regulator-fixed";
 103                 regulator-name = "usb_otg1_vbus";
 104                 regulator-min-microvolt = <5000000>;
 105                 regulator-max-microvolt = <5000000>;
 106                 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
 107                 enable-active-high;
 108         };
 109
 110         reg_wlan: regulator-wlan {
 111                 pinctrl-names = "default";
 112                 pinctrl-0 = <&pinctrl_reg_wlan>;
 113                 compatible = "regulator-fixed";
 114                 clocks = <&clks IMX6SX_CLK_CKO>;
 115                 clock-names = "slow";
 116                 regulator-name = "wlan-en";
 117                 regulator-min-microvolt = <3300000>;
 118                 regulator-max-microvolt = <3300000>;
 119                 startup-delay-us = <70000>;
 120                 gpio = <&gpio7 6 GPIO_ACTIVE_HIGH>;
 121                 enable-active-high;
 122         };
 123
 124         sound {
 125                 compatible = "fsl,imx-audio-sgtl5000";
 126                 model = "imx6sx-nitrogen6sx-sgtl5000";
 127                 cpu-dai = <&ssi1>;
 128                 audio-codec = <&codec>;
 129                 audio-routing =
 130                         "MIC_IN", "Mic Jack",
 131                         "Mic Jack", "Mic Bias",
 132                         "Headphone Jack", "HP_OUT";
 133                 mux-int-port = <1>;
 134                 mux-ext-port = <5>;
 135         };
 136 };
 137
 138 &audmux {
 139         pinctrl-names = "default";
 140         pinctrl-0 = <&pinctrl_audmux>;
 141         status = "okay";
 142 };
 143
 144 &ecspi1 {
 145         cs-gpios = <&gpio2 16 GPIO_ACTIVE_LOW>;
 146         pinctrl-names = "default";
 147         pinctrl-0 = <&pinctrl_ecspi1>;
 148         status = "okay";
 149
 150         flash: m25p80@0 {
 151                 compatible = "microchip,sst25vf016b";
 152                 spi-max-frequency = <20000000>;
 153                 reg = <0>;
 154                 #address-cells = <1>;
 155                 #size-cells = <1>;
 156
 157                 partition@0 {
 158                         label = "U-Boot";
 159                         reg = <0x0 0xc0000>;
 160                         read-only;
 161                 };
 162
 163                 partition@c0000 {
 164                         label = "env";
 165                         reg = <0xc0000 0x2000>;
 166                         read-only;
 167                 };
 168
 169                 partition@c2000 {
 170                         label = "Kernel";
 171                         reg = <0xc2000 0x11e000>;
 172                 };
 173
 174                 partition@1e0000 {
 175                         label = "M4";
 176                         reg = <0x1e0000 0x20000>;
 177                 };
 178         };
 179 };
 180
 181 &fec1 {
 182         pinctrl-names = "default";
 183         pinctrl-0 = <&pinctrl_enet1>;
 184         phy-mode = "rgmii";
 185         phy-handle = <&ethphy1>;
 186         phy-supply = <&reg_3p3v>;
 187         fsl,magic-packet;
 188         status = "okay";
 189
 190         mdio {
 191                 #address-cells = <1>;
 192                 #size-cells = <0>;
 193
 194                 ethphy1: ethernet-phy@4 {
 195                         reg = <4>;
 196                 };
 197
 198                 ethphy2: ethernet-phy@5 {
 199                         reg = <5>;
 200                 };
 201         };
 202 };
 203
 204 &fec2 {
 205         pinctrl-names = "default";
 206         pinctrl-0 = <&pinctrl_enet2>;
 207         phy-mode = "rgmii";
 208         phy-handle = <&ethphy2>;
 209         phy-supply = <&reg_3p3v>;
 210         fsl,magic-packet;
 211         status = "okay";
 212 };
 213
 214 &flexcan1 {
 215         pinctrl-names = "default";
 216         pinctrl-0 = <&pinctrl_flexcan1>;
 217         xceiver-supply = <&reg_can1_3v3>;
 218         status = "okay";
 219 };
 220
 221 &flexcan2 {
 222         pinctrl-names = "default";
 223         pinctrl-0 = <&pinctrl_flexcan2>;
 224         xceiver-supply = <&reg_can2_3v3>;
 225         status = "okay";
 226 };
 227
 228 &i2c1 {
 229         clock-frequency = <100000>;
 230         pinctrl-names = "default";
 231         pinctrl-0 = <&pinctrl_i2c1>;
 232         status = "okay";
 233
 234         codec: sgtl5000@0a {
 235                 compatible = "fsl,sgtl5000";
 236                 pinctrl-names = "default";
 237                 pinctrl-0 = <&pinctrl_sgtl5000>;
 238                 reg = <0x0a>;
 239                 clocks = <&clks IMX6SX_CLK_CKO2>;
 240                 VDDA-supply = <&reg_1p8v>;
 241                 VDDIO-supply = <&reg_1p8v>;
 242                 VDDD-supply = <&reg_1p8v>;
 243                 assigned-clocks = <&clks IMX6SX_CLK_CKO2_SEL>,
 244                                   <&clks IMX6SX_CLK_CKO2>;
 245                 assigned-clock-parents = <&clks IMX6SX_CLK_OSC>;
 246                 assigned-clock-rates = <0>, <24000000>;
 247         };
 248 };
 249
 250 &i2c2 {
 251         clock-frequency = <100000>;
 252         pinctrl-names = "default";
 253         pinctrl-0 = <&pinctrl_i2c2>;
 254         status = "okay";
 255 };
 256
 257 &i2c3 {
 258         clock-frequency = <100000>;
 259         pinctrl-names = "default";
 260         pinctrl-0 = <&pinctrl_i2c3>;
 261         status = "okay";
 262 };
 263
 264 &lcdif1 {
 265         pinctrl-names = "default";
 266         pinctrl-0 = <&pinctrl_lcdif1>;
 267         lcd-supply = <&reg_3p3v>;
 268         display = <&display0>;
 269         status = "okay";
 270
 271         display0: display0 {
 272                 bits-per-pixel = <16>;
 273                 bus-width = <24>;
 274
 275                 display-timings {
 276                         native-mode = <&t_lcd>;
 277                         t_lcd: t_lcd_default {
 278                                 clock-frequency = <74160000>;
 279                                 hactive = <1280>;
 280                                 vactive = <720>;
 281                                 hback-porch = <220>;
 282                                 hfront-porch = <110>;
 283                                 vback-porch = <20>;
 284                                 vfront-porch = <5>;
 285                                 hsync-len = <40>;
 286                                 vsync-len = <5>;
 287                                 hsync-active = <0>;
 288                                 vsync-active = <0>;
 289                                 de-active = <1>;
 290                                 pixelclk-active = <0>;
 291                         };
 292                 };
 293         };
 294 };
 295
 296 &pcie {
 297         pinctrl-names = "default";
 298         pinctrl-0 = <&pinctrl_pcie>;
 299         reset-gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>;
 300         status = "okay";
 301 };
 302
 303 &pwm4 {
 304         pinctrl-names = "default";
 305         pinctrl-0 = <&pinctrl_pwm4>;
 306         status = "okay";
 307 };
 308
 309 &ssi1 {
 310         status = "okay";
 311 };
 312
 313 &uart1 {
 314         pinctrl-names = "default";
 315         pinctrl-0 = <&pinctrl_uart1>;
 316         status = "okay";
 317 };
 318
 319 &uart2 {
 320         pinctrl-names = "default";
 321         pinctrl-0 = <&pinctrl_uart2>;
 322         status = "okay";
 323 };
 324
 325 &uart3 {
 326         pinctrl-names = "default";
 327         pinctrl-0 = <&pinctrl_uart3>;
 328         uart-has-rtscts;
 329         status = "okay";
 330 };
 331
 332 &uart5 {
 333         pinctrl-names = "default";
 334         pinctrl-0 = <&pinctrl_uart5>;
 335         status = "okay";
 336 };
 337
 338 &usbotg1 {
 339         vbus-supply = <&reg_usb_otg1_vbus>;
 340         pinctrl-names = "default";
 341         pinctrl-0 = <&pinctrl_usbotg1>;
 342         status = "okay";
 343 };
 344
 345 &usbotg2 {
 346         pinctrl-names = "default";
 347         pinctrl-0 = <&pinctrl_usbotg2>;
 348         dr_mode = "host";
 349         disable-over-current;
 350         reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
 351         status = "okay";
 352 };
 353
 354 &usdhc2 {
 355         pinctrl-names = "default";
 356         pinctrl-0 = <&pinctrl_usdhc2>;
 357         bus-width = <4>;
 358         cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
 359         keep-power-in-suspend;
 360         wakeup-source;
 361         status = "okay";
 362 };
 363
 364 &usdhc3 {
 365         #address-cells = <1>;
 366         #size-cells = <0>;
 367         pinctrl-names = "default";
 368         pinctrl-0 = <&pinctrl_usdhc3>;
 369         bus-width = <4>;
 370         non-removable;
 371         keep-power-in-suspend;
 372         vmmc-supply = <&reg_wlan>;
 373         cap-power-off-card;
 374         cap-sdio-irq;
 375         status = "okay";
 376
 377         brcmf: bcrmf@1 {
 378                 reg = <1>;
 379                 compatible = "brcm,bcm4329-fmac";
 380                 interrupt-parent = <&gpio7>;
 381                 interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
 382         };
 383
 384         wlcore: wlcore@2 {
 385                 compatible = "ti,wl1271";
 386                 reg = <2>;
 387                 interrupt-parent = <&gpio7>;
 388                 interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
 389                 ref-clock-frequency = <38400000>;
 390         };
 391 };
 392
 393 &usdhc4 {
 394         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 395         pinctrl-0 = <&pinctrl_usdhc4_50mhz>;
 396         pinctrl-1 = <&pinctrl_usdhc4_100mhz>;
 397         pinctrl-2 = <&pinctrl_usdhc4_200mhz>;
 398         bus-width = <8>;
 399         non-removable;
 400         vmmc-supply = <&reg_1p8v>;
 401         keep-power-in-suspend;
 402         status = "okay";
 403 };
 404
 405 &iomuxc {
 406         pinctrl-names = "default";
 407         pinctrl-0 = <&pinctrl_hog>;
 408
 409         pinctrl_audmux: audmuxgrp {
 410                 fsl,pins = <
 411                         MX6SX_PAD_SD1_DATA0__AUDMUX_AUD5_RXD    0x1b0b0
 412                         MX6SX_PAD_SD1_DATA1__AUDMUX_AUD5_TXC    0x1b0b0
 413                         MX6SX_PAD_SD1_DATA2__AUDMUX_AUD5_TXFS   0x1b0b0
 414                         MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_TXD    0x1b0b0
 415                 >;
 416         };
 417
 418         pinctrl_ecspi1: ecspi1grp {
 419                 fsl,pins = <
 420                         MX6SX_PAD_KEY_COL1__ECSPI1_MISO         0x100b1
 421                         MX6SX_PAD_KEY_ROW0__ECSPI1_MOSI         0x100b1
 422                         MX6SX_PAD_KEY_COL0__ECSPI1_SCLK         0x100b1
 423                         MX6SX_PAD_KEY_ROW1__GPIO2_IO_16         0x0b0b1
 424                 >;
 425         };
 426
 427         pinctrl_enet1: enet1grp {
 428                 fsl,pins = <
 429                         MX6SX_PAD_ENET1_MDIO__ENET1_MDIO        0x1b0b0
 430                         MX6SX_PAD_ENET1_MDC__ENET1_MDC          0x1b0b0
 431                         MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0   0x30b1
 432                         MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1   0x30b1
 433                         MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2   0x30b1
 434                         MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3   0x30b1
 435                         MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC   0x30b1
 436                         MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN    0x30b1
 437                         MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0   0x3081
 438                         MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1   0x3081
 439                         MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN    0x3081
 440                         MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2   0x3081
 441                         MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3   0x3081
 442                         MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK      0x3081
 443                         MX6SX_PAD_ENET2_CRS__GPIO2_IO_7         0xb0b0
 444                         MX6SX_PAD_ENET1_RX_CLK__GPIO2_IO_4      0xb0b0
 445                         MX6SX_PAD_ENET1_TX_CLK__GPIO2_IO_5      0xb0b0
 446                 >;
 447         };
 448
 449         pinctrl_enet2: enet2grp {
 450                 fsl,pins = <
 451                         MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0   0x30b1
 452                         MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1   0x30b1
 453                         MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2   0x30b1
 454                         MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3   0x30b1
 455                         MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC   0x30b1
 456                         MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN    0x30b1
 457                         MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0   0x3081
 458                         MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1   0x3081
 459                         MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN    0x3081
 460                         MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2   0x3081
 461                         MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3   0x3081
 462                         MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK      0x3081
 463                         MX6SX_PAD_ENET2_COL__GPIO2_IO_6         0xb0b0
 464                         MX6SX_PAD_ENET2_RX_CLK__GPIO2_IO_8      0xb0b0
 465                         MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9      0xb0b0
 466                 >;
 467         };
 468
 469         pinctrl_flexcan1: flexcan1grp {
 470                 fsl,pins = <
 471                         MX6SX_PAD_QSPI1B_DQS__CAN1_TX           0x1b0b0
 472                         MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX         0x1b0b0
 473                         MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27     0x1b0b0
 474                         MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27     0x0b0b0
 475                 >;
 476         };
 477
 478         pinctrl_flexcan2: flexcan2grp {
 479                 fsl,pins = <
 480                         MX6SX_PAD_QSPI1A_DQS__CAN2_TX           0x1b0b0
 481                         MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX         0x1b0b0
 482                         MX6SX_PAD_QSPI1B_DATA0__GPIO4_IO_24     0x0b0b0
 483                 >;
 484         };
 485
 486         pinctrl_hog: hoggrp {
 487                 fsl,pins = <
 488                         MX6SX_PAD_NAND_CE0_B__GPIO4_IO_1        0x1b0b0
 489                         MX6SX_PAD_NAND_CLE__GPIO4_IO_3          0x1b0b0
 490                         MX6SX_PAD_NAND_RE_B__GPIO4_IO_12        0x1b0b0
 491                         MX6SX_PAD_NAND_WE_B__GPIO4_IO_14        0x1b0b0
 492                         MX6SX_PAD_NAND_WP_B__GPIO4_IO_15        0x1b0b0
 493                         MX6SX_PAD_NAND_READY_B__GPIO4_IO_13     0x1b0b0
 494                         MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16     0x1b0b0
 495                         MX6SX_PAD_QSPI1A_DATA1__GPIO4_IO_17     0x1b0b0
 496                         MX6SX_PAD_QSPI1A_DATA2__GPIO4_IO_18     0x1b0b0
 497                         MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19     0x1b0b0
 498                         MX6SX_PAD_SD1_CMD__CCM_CLKO1            0x000b0
 499                         MX6SX_PAD_SD3_DATA5__GPIO7_IO_7         0x1b0b0
 500                         /* Test points */
 501                         MX6SX_PAD_NAND_DATA04__GPIO4_IO_8       0x1b0b0
 502                         MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25     0x1b0b0
 503                 >;
 504         };
 505
 506         pinctrl_i2c1: i2c1grp {
 507                 fsl,pins = <
 508                         MX6SX_PAD_GPIO1_IO00__I2C1_SCL          0x4001b8b1
 509                         MX6SX_PAD_GPIO1_IO01__I2C1_SDA          0x4001b8b1
 510                 >;
 511         };
 512
 513         pinctrl_i2c2: i2c2grp {
 514                 fsl,pins = <
 515                         MX6SX_PAD_GPIO1_IO02__I2C2_SCL          0x4001b8b1
 516                         MX6SX_PAD_GPIO1_IO03__I2C2_SDA          0x4001b8b1
 517                 >;
 518         };
 519
 520         pinctrl_i2c3: i2c3grp {
 521                 fsl,pins = <
 522                         MX6SX_PAD_KEY_COL4__I2C3_SCL            0x4001b8b1
 523                         MX6SX_PAD_KEY_ROW4__I2C3_SDA            0x4001b8b1
 524                 >;
 525         };
 526
 527         pinctrl_lcdif1: lcdif1grp {
 528                 fsl,pins = <
 529                         MX6SX_PAD_LCD1_CLK__LCDIF1_CLK          0x4001b0b0
 530                         MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE    0x4001b0b0
 531                         MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC      0x4001b0b0
 532                         MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC      0x4001b0b0
 533                         MX6SX_PAD_LCD1_RESET__GPIO3_IO_27       0x4001b0b0
 534                         MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0    0x4001b0b0
 535                         MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1    0x4001b0b0
 536                         MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2    0x4001b0b0
 537                         MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3    0x4001b0b0
 538                         MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4    0x4001b0b0
 539                         MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5    0x4001b0b0
 540                         MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6    0x4001b0b0
 541                         MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7    0x4001b0b0
 542                         MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8    0x4001b0b0
 543                         MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9    0x4001b0b0
 544                         MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10   0x4001b0b0
 545                         MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11   0x4001b0b0
 546                         MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12   0x4001b0b0
 547                         MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13   0x4001b0b0
 548                         MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14   0x4001b0b0
 549                         MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15   0x4001b0b0
 550                         MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16   0x4001b0b0
 551                         MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17   0x4001b0b0
 552                         MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18   0x4001b0b0
 553                         MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19   0x4001b0b0
 554                         MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20   0x4001b0b0
 555                         MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21   0x4001b0b0
 556                         MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22   0x4001b0b0
 557                         MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23   0x4001b0b0
 558                 >;
 559         };
 560
 561         pinctrl_pcie: pciegrp {
 562                 fsl,pins = <
 563                         MX6SX_PAD_NAND_DATA05__GPIO4_IO_9       0xb0b0
 564                         MX6SX_PAD_NAND_DATA06__GPIO4_IO_10      0xb0b0
 565                         MX6SX_PAD_NAND_DATA07__GPIO4_IO_11      0xb0b0
 566                 >;
 567         };
 568
 569         pinctrl_pwm4: pwm4grp {
 570                 fsl,pins = <
 571                         MX6SX_PAD_GPIO1_IO13__PWM4_OUT          0x110b0
 572                 >;
 573         };
 574
 575         pinctrl_reg_wlan: reg-wlangrp {
 576                 fsl,pins = <
 577                         MX6SX_PAD_SD3_DATA4__GPIO7_IO_6         0x1b0b0
 578                         MX6SX_PAD_GPIO1_IO11__CCM_CLKO1         0x000b0
 579                 >;
 580         };
 581
 582         pinctrl_sgtl5000: sgtl5000grp {
 583                 fsl,pins = <
 584                         MX6SX_PAD_GPIO1_IO12__CCM_CLKO2         0x000b0
 585                         MX6SX_PAD_ENET1_COL__GPIO2_IO_0         0x1b0b0
 586                         MX6SX_PAD_ENET1_CRS__GPIO2_IO_1         0x1b0b0
 587                         MX6SX_PAD_QSPI1A_SS0_B__GPIO4_IO_22     0xb0b0
 588                 >;
 589         };
 590
 591         pinctrl_uart1: uart1grp {
 592                 fsl,pins = <
 593                         MX6SX_PAD_GPIO1_IO04__UART1_TX          0x1b0b1
 594                         MX6SX_PAD_GPIO1_IO05__UART1_RX          0x1b0b1
 595                 >;
 596         };
 597
 598         pinctrl_uart2: uart2grp {
 599                 fsl,pins = <
 600                         MX6SX_PAD_GPIO1_IO06__UART2_TX          0x1b0b1
 601                         MX6SX_PAD_GPIO1_IO07__UART2_RX          0x1b0b1
 602                 >;
 603         };
 604
 605         pinctrl_uart3: uart3grp {
 606                 fsl,pins = <
 607                         MX6SX_PAD_QSPI1B_SS0_B__UART3_TX        0x1b0b1
 608                         MX6SX_PAD_QSPI1B_SCLK__UART3_RX         0x1b0b1
 609                 >;
 610         };
 611
 612         pinctrl_uart5: uart5grp {
 613                 fsl,pins = <
 614                         MX6SX_PAD_KEY_COL3__UART5_TX            0x1b0b1
 615                         MX6SX_PAD_KEY_ROW3__UART5_RX            0x1b0b1
 616                         MX6SX_PAD_SD3_DATA6__UART3_RTS_B        0x1b0b1
 617                         MX6SX_PAD_SD3_DATA7__UART3_CTS_B        0x1b0b1
 618                 >;
 619         };
 620
 621         pinctrl_usbotg1: usbotg1grp {
 622                 fsl,pins = <
 623                         MX6SX_PAD_GPIO1_IO08__USB_OTG1_OC       0x1b0b0
 624                         MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID    0x170b1
 625                 >;
 626         };
 627
 628         pinctrl_usbotg1_vbus: usbotg1-vbusgrp {
 629                 fsl,pins = <
 630                         MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9        0x1b0b0
 631                 >;
 632         };
 633
 634         pinctrl_usbotg2: usbotg2grp {
 635                 fsl,pins = <
 636                         MX6SX_PAD_QSPI1B_DATA2__GPIO4_IO_26     0xb0b0
 637                 >;
 638         };
 639
 640         pinctrl_usdhc2: usdhc2grp {
 641                 fsl,pins = <
 642                         MX6SX_PAD_SD2_CMD__USDHC2_CMD           0x17059
 643                         MX6SX_PAD_SD2_CLK__USDHC2_CLK           0x10059
 644                         MX6SX_PAD_SD2_DATA0__USDHC2_DATA0       0x17059
 645                         MX6SX_PAD_SD2_DATA1__USDHC2_DATA1       0x17059
 646                         MX6SX_PAD_SD2_DATA2__USDHC2_DATA2       0x17059
 647                         MX6SX_PAD_SD2_DATA3__USDHC2_DATA3       0x17059
 648                         MX6SX_PAD_KEY_COL2__GPIO2_IO_12         0x1b0b0
 649                 >;
 650         };
 651
 652         pinctrl_usdhc3: usdhc3grp {
 653                 fsl,pins = <
 654                         MX6SX_PAD_SD3_CLK__USDHC3_CLK           0x10071
 655                         MX6SX_PAD_SD3_CMD__USDHC3_CMD           0x17071
 656                         MX6SX_PAD_SD3_DATA0__USDHC3_DATA0       0x17071
 657                         MX6SX_PAD_SD3_DATA1__USDHC3_DATA1       0x17071
 658                         MX6SX_PAD_SD3_DATA2__USDHC3_DATA2       0x17071
 659                         MX6SX_PAD_SD3_DATA3__USDHC3_DATA3       0x17071
 660                 >;
 661         };
 662
 663         pinctrl_usdhc4_50mhz: usdhc4-50mhzgrp {
 664                 fsl,pins = <
 665                         MX6SX_PAD_SD4_CLK__USDHC4_CLK           0x10071
 666                         MX6SX_PAD_SD4_CMD__USDHC4_CMD           0x17071
 667                         MX6SX_PAD_SD4_RESET_B__USDHC4_RESET_B   0x17071
 668                         MX6SX_PAD_SD4_DATA0__USDHC4_DATA0       0x17071
 669                         MX6SX_PAD_SD4_DATA1__USDHC4_DATA1       0x17071
 670                         MX6SX_PAD_SD4_DATA2__USDHC4_DATA2       0x17071
 671                         MX6SX_PAD_SD4_DATA3__USDHC4_DATA3       0x17071
 672                         MX6SX_PAD_SD4_DATA4__USDHC4_DATA4       0x17071
 673                         MX6SX_PAD_SD4_DATA5__USDHC4_DATA5       0x17071
 674                         MX6SX_PAD_SD4_DATA6__USDHC4_DATA6       0x17071
 675                         MX6SX_PAD_SD4_DATA7__USDHC4_DATA7       0x17071
 676                 >;
 677         };
 678
 679         pinctrl_usdhc4_100mhz: usdhc4-100mhzgrp {
 680                 fsl,pins = <
 681                         MX6SX_PAD_SD4_CLK__USDHC4_CLK           0x100b9
 682                         MX6SX_PAD_SD4_CMD__USDHC4_CMD           0x170b9
 683                         MX6SX_PAD_SD4_DATA0__USDHC4_DATA0       0x170b9
 684                         MX6SX_PAD_SD4_DATA1__USDHC4_DATA1       0x170b9
 685                         MX6SX_PAD_SD4_DATA2__USDHC4_DATA2       0x170b9
 686                         MX6SX_PAD_SD4_DATA3__USDHC4_DATA3       0x170b9
 687                         MX6SX_PAD_SD4_DATA4__USDHC4_DATA4       0x170b9
 688                         MX6SX_PAD_SD4_DATA5__USDHC4_DATA5       0x170b9
 689                         MX6SX_PAD_SD4_DATA6__USDHC4_DATA6       0x170b9
 690                         MX6SX_PAD_SD4_DATA7__USDHC4_DATA7       0x170b9
 691                 >;
 692         };
 693
 694         pinctrl_usdhc4_200mhz: usdhc4-200mhzgrp {
 695                 fsl,pins = <
 696                         MX6SX_PAD_SD4_CLK__USDHC4_CLK           0x100f9
 697                         MX6SX_PAD_SD4_CMD__USDHC4_CMD           0x170f9
 698                         MX6SX_PAD_SD4_DATA0__USDHC4_DATA0       0x170f9
 699                         MX6SX_PAD_SD4_DATA1__USDHC4_DATA1       0x170f9
 700                         MX6SX_PAD_SD4_DATA2__USDHC4_DATA2       0x170f9
 701                         MX6SX_PAD_SD4_DATA3__USDHC4_DATA3       0x170f9
 702                         MX6SX_PAD_SD4_DATA4__USDHC4_DATA4       0x170f9
 703                         MX6SX_PAD_SD4_DATA5__USDHC4_DATA5       0x170f9
 704                         MX6SX_PAD_SD4_DATA6__USDHC4_DATA6       0x170f9
 705                         MX6SX_PAD_SD4_DATA7__USDHC4_DATA7       0x170f9
 706                 >;
 707         };
 708 };