arch/arm/boot/dts/imx7d-cl-som-imx7.dts

   1 /*
   2  * Support for CompuLab CL-SOM-iMX7 System-on-Module
   3  *
   4  * Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/
   5  * Author: Ilya Ledvich <ilya@compulab.co.il>
   6  *
   7  * This file is dual-licensed: you can use it either under the terms
   8  * of the GPL or the X11 license, at your option. Note that this dual
   9  * licensing only applies to this file, and not this project as a
  10  * whole.
  11  */
  12
  13 /dts-v1/;
  14
  15 #include "imx7d.dtsi"
  16
  17 / {
  18         model = "CompuLab CL-SOM-iMX7";
  19         compatible = "compulab,cl-som-imx7", "fsl,imx7d";
  20
  21         memory {
  22                 reg = <0x80000000 0x10000000>; /* 256 MB - minimal configuration */
  23         };
  24
  25         reg_usb_otg1_vbus: regulator-vbus {
  26                 compatible = "regulator-fixed";
  27                 regulator-name = "usb_otg1_vbus";
  28                 regulator-min-microvolt = <5000000>;
  29                 regulator-max-microvolt = <5000000>;
  30                 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
  31                 enable-active-high;
  32         };
  33 };
  34
  35 &cpu0 {
  36         arm-supply = <&sw1a_reg>;
  37 };
  38
  39 &fec1 {
  40         pinctrl-names = "default";
  41         pinctrl-0 = <&pinctrl_enet1>;
  42         assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
  43                           <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
  44         assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
  45         assigned-clock-rates = <0>, <100000000>;
  46         phy-mode = "rgmii";
  47         phy-handle = <&ethphy0>;
  48         fsl,magic-packet;
  49         status = "okay";
  50
  51         mdio {
  52                 #address-cells = <1>;
  53                 #size-cells = <0>;
  54
  55                 ethphy0: ethernet-phy@0 {
  56                         reg = <0>;
  57                 };
  58
  59                 ethphy1: ethernet-phy@1 {
  60                         reg = <1>;
  61                 };
  62         };
  63 };
  64
  65 &fec2 {
  66         pinctrl-names = "default";
  67         pinctrl-0 = <&pinctrl_enet2>;
  68         assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
  69                           <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
  70         assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
  71         assigned-clock-rates = <0>, <100000000>;
  72         phy-mode = "rgmii";
  73         phy-handle = <&ethphy1>;
  74         fsl,magic-packet;
  75         status = "okay";
  76 };
  77
  78 &i2c2 {
  79         pinctrl-names = "default";
  80         pinctrl-0 = <&pinctrl_i2c2>;
  81         status = "okay";
  82
  83         pmic: pmic@8 {
  84                 compatible = "fsl,pfuze3000";
  85                 reg = <0x08>;
  86
  87                 regulators {
  88                         sw1a_reg: sw1a {
  89                                 regulator-min-microvolt = <700000>;
  90                                 regulator-max-microvolt = <1475000>;
  91                                 regulator-boot-on;
  92                                 regulator-always-on;
  93                                 regulator-ramp-delay = <6250>;
  94                         };
  95
  96                         /* use sw1c_reg to align with pfuze100/pfuze200 */
  97                         sw1c_reg: sw1b {
  98                                 regulator-min-microvolt = <700000>;
  99                                 regulator-max-microvolt = <1475000>;
 100                                 regulator-boot-on;
 101                                 regulator-always-on;
 102                                 regulator-ramp-delay = <6250>;
 103                         };
 104
 105                         sw2_reg: sw2 {
 106                                 regulator-min-microvolt = <1500000>;
 107                                 regulator-max-microvolt = <1850000>;
 108                                 regulator-boot-on;
 109                                 regulator-always-on;
 110                         };
 111
 112                         sw3a_reg: sw3 {
 113                                 regulator-min-microvolt = <900000>;
 114                                 regulator-max-microvolt = <1650000>;
 115                                 regulator-boot-on;
 116                                 regulator-always-on;
 117                         };
 118
 119                         swbst_reg: swbst {
 120                                 regulator-min-microvolt = <5000000>;
 121                                 regulator-max-microvolt = <5150000>;
 122                         };
 123
 124                         snvs_reg: vsnvs {
 125                                 regulator-min-microvolt = <1000000>;
 126                                 regulator-max-microvolt = <3000000>;
 127                                 regulator-boot-on;
 128                                 regulator-always-on;
 129                         };
 130
 131                         vref_reg: vrefddr {
 132                                 regulator-boot-on;
 133                                 regulator-always-on;
 134                         };
 135
 136                         vgen1_reg: vldo1 {
 137                                 regulator-min-microvolt = <1800000>;
 138                                 regulator-max-microvolt = <3300000>;
 139                                 regulator-always-on;
 140                         };
 141
 142                         vgen2_reg: vldo2 {
 143                                 regulator-min-microvolt = <800000>;
 144                                 regulator-max-microvolt = <1550000>;
 145                         };
 146
 147                         vgen3_reg: vccsd {
 148                                 regulator-min-microvolt = <2850000>;
 149                                 regulator-max-microvolt = <3300000>;
 150                                 regulator-always-on;
 151                         };
 152
 153                         vgen4_reg: v33 {
 154                                 regulator-min-microvolt = <2850000>;
 155                                 regulator-max-microvolt = <3300000>;
 156                                 regulator-always-on;
 157                         };
 158
 159                         vgen5_reg: vldo3 {
 160                                 regulator-min-microvolt = <1800000>;
 161                                 regulator-max-microvolt = <3300000>;
 162                                 regulator-always-on;
 163                         };
 164
 165                         vgen6_reg: vldo4 {
 166                                 regulator-min-microvolt = <1800000>;
 167                                 regulator-max-microvolt = <3300000>;
 168                                 regulator-always-on;
 169                         };
 170                 };
 171         };
 172
 173         pca9555: pca9555@20 {
 174                 compatible = "nxp,pca9555";
 175                 gpio-controller;
 176                 #gpio-cells = <2>;
 177                 reg = <0x20>;
 178         };
 179
 180         eeprom@50 {
 181                 compatible = "atmel,24c08";
 182                 reg = <0x50>;
 183                 pagesize = <16>;
 184         };
 185 };
 186
 187 &uart1 {
 188         pinctrl-names = "default";
 189         pinctrl-0 = <&pinctrl_uart1>;
 190         assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
 191         assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
 192         status = "okay";
 193 };
 194
 195 &usbotg1 {
 196         pinctrl-names = "default";
 197         pinctrl-0 = <&pinctrl_usbotg1>;
 198         vbus-supply = <&reg_usb_otg1_vbus>;
 199         status = "okay";
 200 };
 201
 202 &usdhc3 {
 203         pinctrl-names = "default";
 204         pinctrl-0 = <&pinctrl_usdhc3>;
 205         assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
 206         assigned-clock-rates = <400000000>;
 207         bus-width = <8>;
 208         fsl,tuning-step = <2>;
 209         non-removable;
 210         status = "okay";
 211 };
 212
 213 &iomuxc {
 214         pinctrl_enet1: enet1grp {
 215                 fsl,pins = <
 216                         MX7D_PAD_SD2_CD_B__ENET1_MDIO                   0x3
 217                         MX7D_PAD_SD2_WP__ENET1_MDC                      0x3
 218                         MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC       0x1
 219                         MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0       0x1
 220                         MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1       0x1
 221                         MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2       0x1
 222                         MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3       0x1
 223                         MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
 224                         MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC       0x1
 225                         MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0       0x1
 226                         MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1       0x1
 227                         MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2       0x1
 228                         MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3       0x1
 229                         MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
 230                 >;
 231         };
 232
 233         pinctrl_enet2: enet2grp {
 234                 fsl,pins = <
 235                         MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC             0x1
 236                         MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0            0x1
 237                         MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1            0x1
 238                         MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2            0x1
 239                         MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3             0x1
 240                         MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL          0x1
 241                         MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC            0x1
 242                         MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0            0x1
 243                         MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1             0x1
 244                         MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2             0x1
 245                         MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3            0x1
 246                         MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL         0x1
 247                 >;
 248         };
 249
 250         pinctrl_i2c2: i2c2grp {
 251                 fsl,pins = <
 252                         MX7D_PAD_I2C2_SDA__I2C2_SDA             0x4000007f
 253                         MX7D_PAD_I2C2_SCL__I2C2_SCL             0x4000007f
 254                 >;
 255         };
 256
 257         pinctrl_uart1: uart1grp {
 258                 fsl,pins = <
 259                         MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX    0x79
 260                         MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX    0x79
 261                 >;
 262         };
 263
 264         pinctrl_usdhc3: usdhc3grp {
 265                 fsl,pins = <
 266                         MX7D_PAD_SD3_CMD__SD3_CMD               0x59
 267                         MX7D_PAD_SD3_CLK__SD3_CLK               0x19
 268                         MX7D_PAD_SD3_DATA0__SD3_DATA0           0x59
 269                         MX7D_PAD_SD3_DATA1__SD3_DATA1           0x59
 270                         MX7D_PAD_SD3_DATA2__SD3_DATA2           0x59
 271                         MX7D_PAD_SD3_DATA3__SD3_DATA3           0x59
 272                         MX7D_PAD_SD3_DATA4__SD3_DATA4           0x59
 273                         MX7D_PAD_SD3_DATA5__SD3_DATA5           0x59
 274                         MX7D_PAD_SD3_DATA6__SD3_DATA6           0x59
 275                         MX7D_PAD_SD3_DATA7__SD3_DATA7           0x59
 276                         MX7D_PAD_SD3_STROBE__SD3_STROBE         0x19
 277                 >;
 278         };
 279 };
 280
 281 &iomuxc_lpsr {
 282         pinctrl_usbotg1: usbotg1grp {
 283                 fsl,pins = <
 284                         MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5     0x14 /* OTG PWREN */
 285                 >;
 286         };
 287 };