arch/arm/boot/dts/imx7d-nitrogen7.dts

   1 /*
   2  * Copyright 2016 Boundary Devices, Inc.
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 /dts-v1/;
  44
  45 #include "imx7d.dtsi"
  46
  47 / {
  48         model = "Boundary Devices i.MX7 Nitrogen7 Board";
  49         compatible = "boundary,imx7d-nitrogen7", "fsl,imx7d";
  50
  51         aliases {
  52                 fb_lcd = &lcdif;
  53                 t_lcd = &t_lcd;
  54         };
  55
  56         memory {
  57                 reg = <0x80000000 0x40000000>;
  58         };
  59
  60         backlight-j9 {
  61                 compatible = "gpio-backlight";
  62                 pinctrl-names = "default";
  63                 pinctrl-0 = <&pinctrl_backlight_j9>;
  64                 gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
  65                 default-on;
  66         };
  67
  68         backlight-j20 {
  69                 compatible = "pwm-backlight";
  70                 pwms = <&pwm1 0 5000000>;
  71                 brightness-levels = <0 4 8 16 32 64 128 255>;
  72                 default-brightness-level = <6>;
  73                 status = "okay";
  74         };
  75
  76         reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
  77                 compatible = "regulator-fixed";
  78                 regulator-name = "usb_otg1_vbus";
  79                 regulator-min-microvolt = <5000000>;
  80                 regulator-max-microvolt = <5000000>;
  81                 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
  82                 enable-active-high;
  83         };
  84
  85         reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
  86                 compatible = "regulator-fixed";
  87                 regulator-name = "usb_otg2_vbus";
  88                 regulator-min-microvolt = <5000000>;
  89                 regulator-max-microvolt = <5000000>;
  90                 gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
  91                 enable-active-high;
  92         };
  93
  94         reg_can2_3v3: regulator-can2-3v3 {
  95                 compatible = "regulator-fixed";
  96                 regulator-name = "can2-3v3";
  97                 regulator-min-microvolt = <3300000>;
  98                 regulator-max-microvolt = <3300000>;
  99                 gpio = <&gpio2 14 GPIO_ACTIVE_LOW>;
 100         };
 101
 102         reg_vref_1v8: regulator-vref-1v8 {
 103                 compatible = "regulator-fixed";
 104                 regulator-name = "vref-1v8";
 105                 regulator-min-microvolt = <1800000>;
 106                 regulator-max-microvolt = <1800000>;
 107         };
 108
 109         reg_vref_3v3: regulator-vref-3v3 {
 110                 compatible = "regulator-fixed";
 111                 regulator-name = "vref-3v3";
 112                 regulator-min-microvolt = <3300000>;
 113                 regulator-max-microvolt = <3300000>;
 114         };
 115
 116         reg_wlan: regulator-wlan {
 117                 compatible = "regulator-fixed";
 118                 regulator-min-microvolt = <3300000>;
 119                 regulator-max-microvolt = <3300000>;
 120                 clocks = <&clks IMX7D_CLKO2_ROOT_DIV>;
 121                 clock-names = "slow";
 122                 regulator-name = "reg_wlan";
 123                 startup-delay-us = <70000>;
 124                 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
 125                 enable-active-high;
 126         };
 127 };
 128
 129 &adc1 {
 130         vref-supply = <&reg_vref_1v8>;
 131         status = "okay";
 132 };
 133
 134 &adc2 {
 135         vref-supply = <&reg_vref_1v8>;
 136         status = "okay";
 137 };
 138
 139 &clks {
 140         assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
 141                           <&clks IMX7D_CLKO2_ROOT_DIV>;
 142         assigned-clock-parents = <&clks IMX7D_CKIL>;
 143         assigned-clock-rates = <0>, <32768>;
 144 };
 145
 146 &cpu0 {
 147         arm-supply = <&sw1a_reg>;
 148 };
 149
 150 &fec1 {
 151         pinctrl-names = "default";
 152         pinctrl-0 = <&pinctrl_enet1>;
 153         assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
 154                           <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
 155         assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
 156         assigned-clock-rates = <0>, <100000000>;
 157         phy-mode = "rgmii";
 158         phy-handle = <&ethphy0>;
 159         fsl,magic-packet;
 160         status = "okay";
 161
 162         mdio {
 163                 #address-cells = <1>;
 164                 #size-cells = <0>;
 165
 166                 ethphy0: ethernet-phy@4 {
 167                         reg = <4>;
 168                 };
 169         };
 170 };
 171
 172 &flexcan2 {
 173         pinctrl-names = "default";
 174         pinctrl-0 = <&pinctrl_flexcan2>;
 175         xceiver-supply = <&reg_can2_3v3>;
 176         status = "okay";
 177 };
 178
 179 &i2c1 {
 180         pinctrl-names = "default";
 181         pinctrl-0 = <&pinctrl_i2c1>;
 182         status = "okay";
 183
 184         pmic: pfuze3000@08 {
 185                 compatible = "fsl,pfuze3000";
 186                 reg = <0x08>;
 187
 188                 regulators {
 189                         sw1a_reg: sw1a {
 190                                 regulator-min-microvolt = <700000>;
 191                                 regulator-max-microvolt = <1475000>;
 192                                 regulator-boot-on;
 193                                 regulator-always-on;
 194                                 regulator-ramp-delay = <6250>;
 195                         };
 196
 197                         /* use sw1c_reg to align with pfuze100/pfuze200 */
 198                         sw1c_reg: sw1b {
 199                                 regulator-min-microvolt = <700000>;
 200                                 regulator-max-microvolt = <1475000>;
 201                                 regulator-boot-on;
 202                                 regulator-always-on;
 203                                 regulator-ramp-delay = <6250>;
 204                         };
 205
 206                         sw2_reg: sw2 {
 207                                 regulator-min-microvolt = <1500000>;
 208                                 regulator-max-microvolt = <1850000>;
 209                                 regulator-boot-on;
 210                                 regulator-always-on;
 211                         };
 212
 213                         sw3a_reg: sw3 {
 214                                 regulator-min-microvolt = <900000>;
 215                                 regulator-max-microvolt = <1650000>;
 216                                 regulator-boot-on;
 217                                 regulator-always-on;
 218                         };
 219
 220                         swbst_reg: swbst {
 221                                 regulator-min-microvolt = <5000000>;
 222                                 regulator-max-microvolt = <5150000>;
 223                         };
 224
 225                         snvs_reg: vsnvs {
 226                                 regulator-min-microvolt = <1000000>;
 227                                 regulator-max-microvolt = <3000000>;
 228                                 regulator-boot-on;
 229                                 regulator-always-on;
 230                         };
 231
 232                         vref_reg: vrefddr {
 233                                 regulator-boot-on;
 234                                 regulator-always-on;
 235                         };
 236
 237                         vgen1_reg: vldo1 {
 238                                 regulator-min-microvolt = <1800000>;
 239                                 regulator-max-microvolt = <3300000>;
 240                                 regulator-always-on;
 241                         };
 242
 243                         vgen2_reg: vldo2 {
 244                                 regulator-min-microvolt = <800000>;
 245                                 regulator-max-microvolt = <1550000>;
 246                                 regulator-always-on;
 247                         };
 248
 249                         vgen3_reg: vccsd {
 250                                 regulator-min-microvolt = <2850000>;
 251                                 regulator-max-microvolt = <3300000>;
 252                                 regulator-always-on;
 253                         };
 254
 255                         vgen4_reg: v33 {
 256                                 regulator-min-microvolt = <2850000>;
 257                                 regulator-max-microvolt = <3300000>;
 258                                 regulator-always-on;
 259                         };
 260
 261                         vgen5_reg: vldo3 {
 262                                 regulator-min-microvolt = <1800000>;
 263                                 regulator-max-microvolt = <3300000>;
 264                                 regulator-always-on;
 265                         };
 266
 267                         vgen6_reg: vldo4 {
 268                                 regulator-min-microvolt = <1800000>;
 269                                 regulator-max-microvolt = <3300000>;
 270                                 regulator-always-on;
 271                         };
 272                 };
 273         };
 274 };
 275
 276 &i2c2 {
 277         pinctrl-names = "default";
 278         pinctrl-0 = <&pinctrl_i2c2>;
 279         status = "okay";
 280
 281         rtc@68 {
 282                 compatible = "rv4162";
 283                 pinctrl-names = "default";
 284                 pinctrl-0 = <&pinctrl_i2c2_rv4162>;
 285                 reg = <0x68>;
 286                 interrupts-extended = <&gpio2 15 IRQ_TYPE_LEVEL_LOW>;
 287         };
 288 };
 289
 290 &i2c3 {
 291         pinctrl-names = "default";
 292         pinctrl-0 = <&pinctrl_i2c3>;
 293         status = "okay";
 294
 295         touch@48 {
 296                 compatible = "ti,tsc2004";
 297                 reg = <0x48>;
 298                 pinctrl-names = "default";
 299                 pinctrl-0 = <&pinctrl_i2c3_tsc2004>;
 300                 interrupts-extended = <&gpio3 4 IRQ_TYPE_EDGE_FALLING>;
 301                 wakeup-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>;
 302         };
 303 };
 304
 305 &i2c4 {
 306         pinctrl-names = "default";
 307         pinctrl-0 = <&pinctrl_i2c4>;
 308         status = "okay";
 309
 310         codec: wm8960@1a {
 311                 compatible = "wlf,wm8960";
 312                 reg = <0x1a>;
 313                 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
 314                 clock-names = "mclk";
 315                 wlf,shared-lrclk;
 316         };
 317 };
 318
 319 &lcdif {
 320         pinctrl-names = "default";
 321         pinctrl-0 = <&pinctrl_lcdif_dat
 322                      &pinctrl_lcdif_ctrl>;
 323         lcd-supply = <&reg_vref_3v3>;
 324         display = <&display0>;
 325         status = "okay";
 326
 327         display0: lcd-display {
 328                 bits-per-pixel = <16>;
 329                 bus-width = <18>;
 330
 331                 display-timings {
 332                         native-mode = <&t_lcd>;
 333                         t_lcd: t_lcd_default {
 334                                 /* default to Okaya display */
 335                                 clock-frequency = <30000000>;
 336                                 hactive = <800>;
 337                                 vactive = <480>;
 338                                 hfront-porch = <40>;
 339                                 hback-porch = <40>;
 340                                 hsync-len = <48>;
 341                                 vback-porch = <29>;
 342                                 vfront-porch = <13>;
 343                                 vsync-len = <3>;
 344                                 hsync-active = <0>;
 345                                 vsync-active = <0>;
 346                                 de-active = <1>;
 347                                 pixelclk-active = <0>;
 348                         };
 349                 };
 350         };
 351 };
 352
 353 &pwm1 {
 354         pinctrl-names = "default";
 355         pinctrl-0 = <&pinctrl_pwm1>;
 356         status = "okay";
 357 };
 358
 359 &pwm2 {
 360         pinctrl-names = "default";
 361         pinctrl-0 = <&pinctrl_pwm2>;
 362         status = "okay";
 363 };
 364
 365 &uart1 {
 366         pinctrl-names = "default";
 367         pinctrl-0 = <&pinctrl_uart1>;
 368         assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
 369         assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
 370         status = "okay";
 371 };
 372
 373 &uart2 {
 374         pinctrl-names = "default";
 375         pinctrl-0 = <&pinctrl_uart2>;
 376         assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
 377         assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
 378         status = "okay";
 379 };
 380
 381 &uart3 {
 382         pinctrl-names = "default";
 383         pinctrl-0 = <&pinctrl_uart3>;
 384         assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
 385         assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
 386         status = "okay";
 387 };
 388
 389 &uart6 {
 390         pinctrl-names = "default";
 391         pinctrl-0 = <&pinctrl_uart6>;
 392         assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
 393         assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
 394         uart-has-rtscts;
 395         status = "okay";
 396 };
 397
 398 &usbotg1 {
 399         vbus-supply = <&reg_usb_otg1_vbus>;
 400         pinctrl-names = "default";
 401         pinctrl-0 = <&pinctrl_usbotg1>;
 402         status = "okay";
 403 };
 404
 405 &usbotg2 {
 406         vbus-supply = <&reg_usb_otg2_vbus>;
 407         pinctrl-names = "default";
 408         pinctrl-0 = <&pinctrl_usbotg2>;
 409         dr_mode = "host";
 410         status = "okay";
 411 };
 412
 413 &usdhc1 {
 414         pinctrl-names = "default";
 415         pinctrl-0 = <&pinctrl_usdhc1>;
 416         cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
 417         vmmc-supply = <&vgen3_reg>;
 418         bus-width = <4>;
 419         fsl,tuning-step = <2>;
 420         wakeup-source;
 421         keep-power-in-suspend;
 422         status = "okay";
 423 };
 424
 425 &usdhc2 {
 426         #address-cells = <1>;
 427         #size-cells = <0>;
 428         pinctrl-names = "default";
 429         pinctrl-0 = <&pinctrl_usdhc2>;
 430         bus-width = <4>;
 431         non-removable;
 432         vmmc-supply = <&reg_wlan>;
 433         cap-power-off-card;
 434         keep-power-in-suspend;
 435         status = "okay";
 436
 437         wlcore: wlcore@2 {
 438                 compatible = "ti,wl1271";
 439                 reg = <2>;
 440                 interrupt-parent = <&gpio4>;
 441                 interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
 442                 ref-clock-frequency = <38400000>;
 443         };
 444 };
 445
 446 &usdhc3 {
 447         pinctrl-names = "default";
 448         pinctrl-0 = <&pinctrl_usdhc3>;
 449         assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
 450         assigned-clock-rates = <400000000>;
 451         bus-width = <8>;
 452         fsl,tuning-step = <2>;
 453         non-removable;
 454         status = "okay";
 455 };
 456
 457 &wdog1 {
 458         pinctrl-names = "default";
 459         pinctrl-0 = <&pinctrl_wdog1>;
 460         status = "okay";
 461 };
 462
 463 &iomuxc {
 464         pinctrl-names = "default";
 465         pinctrl-0 = <&pinctrl_hog_1 &pinctrl_j2>;
 466
 467         pinctrl_hog_1: hoggrp-1 {
 468                 fsl,pins = <
 469                         MX7D_PAD_SD3_RESET_B__GPIO6_IO11        0x5d
 470                         MX7D_PAD_GPIO1_IO13__GPIO1_IO13         0x7d
 471                         MX7D_PAD_ECSPI2_MISO__GPIO4_IO22        0x7d
 472                 >;
 473         };
 474
 475         pinctrl_enet1: enet1grp {
 476                 fsl,pins = <
 477                         MX7D_PAD_GPIO1_IO10__ENET1_MDIO                 0x3
 478                         MX7D_PAD_GPIO1_IO11__ENET1_MDC                  0x3
 479                         MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1          0x3
 480                         MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC       0x71
 481                         MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0       0x71
 482                         MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1       0x71
 483                         MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2       0x71
 484                         MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3       0x71
 485                         MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x71
 486                         MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC       0x71
 487                         MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0       0x11
 488                         MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1       0x11
 489                         MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2       0x11
 490                         MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3       0x71
 491                         MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x11
 492                         MX7D_PAD_SD3_STROBE__GPIO6_IO10                 0x75
 493                 >;
 494         };
 495
 496         pinctrl_flexcan2: flexcan2grp {
 497                 fsl,pins = <
 498                         MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX        0x7d
 499                         MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX        0x7d
 500                         MX7D_PAD_EPDC_DATA14__GPIO2_IO14        0x7d
 501                 >;
 502         };
 503
 504         pinctrl_i2c1: i2c1grp {
 505                 fsl,pins = <
 506                         MX7D_PAD_I2C1_SDA__I2C1_SDA             0x4000007f
 507                         MX7D_PAD_I2C1_SCL__I2C1_SCL             0x4000007f
 508                 >;
 509         };
 510
 511         pinctrl_i2c2: i2c2grp {
 512                 fsl,pins = <
 513                         MX7D_PAD_I2C2_SDA__I2C2_SDA             0x4000007f
 514                         MX7D_PAD_I2C2_SCL__I2C2_SCL             0x4000007f
 515                 >;
 516         };
 517
 518         pinctrl_i2c2_rv4162: i2c2-rv4162grp {
 519                 fsl,pins = <
 520                         MX7D_PAD_EPDC_DATA15__GPIO2_IO15        0x7d
 521                 >;
 522         };
 523
 524         pinctrl_i2c3: i2c3grp {
 525                 fsl,pins = <
 526                         MX7D_PAD_I2C3_SDA__I2C3_SDA             0x4000007f
 527                         MX7D_PAD_I2C3_SCL__I2C3_SCL             0x4000007f
 528                 >;
 529         };
 530
 531         pinctrl_i2c3_tsc2004: i2c3tsc2004grp {
 532                 fsl,pins = <
 533                         MX7D_PAD_LCD_RESET__GPIO3_IO4           0x79
 534                         MX7D_PAD_SD2_WP__GPIO5_IO10             0x7d
 535                 >;
 536         };
 537
 538         pinctrl_i2c4: i2c4grp {
 539                 fsl,pins = <
 540                         MX7D_PAD_I2C4_SDA__I2C4_SDA             0x4000007f
 541                         MX7D_PAD_I2C4_SCL__I2C4_SCL             0x4000007f
 542                 >;
 543         };
 544
 545         pinctrl_j2: j2grp {
 546                 fsl,pins = <
 547                         MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15       0x7d
 548                         MX7D_PAD_EPDC_BDR0__GPIO2_IO28          0x7d
 549                         MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12       0x7d
 550                         MX7D_PAD_EPDC_BDR1__GPIO2_IO29          0x7d
 551                         MX7D_PAD_SD1_WP__GPIO5_IO1              0x7d
 552                         MX7D_PAD_EPDC_SDSHR__GPIO2_IO19         0x7d
 553                         MX7D_PAD_SD1_RESET_B__GPIO5_IO2         0x7d
 554                         MX7D_PAD_SD2_RESET_B__GPIO5_IO11        0x7d
 555                         MX7D_PAD_EPDC_DATA07__GPIO2_IO7         0x7d
 556                         MX7D_PAD_EPDC_DATA08__GPIO2_IO8         0x7d
 557                         MX7D_PAD_EPDC_DATA09__GPIO2_IO9         0x7d
 558                         MX7D_PAD_EPDC_DATA10__GPIO2_IO10        0x7d
 559                         MX7D_PAD_EPDC_DATA11__GPIO2_IO11        0x7d
 560                         MX7D_PAD_EPDC_DATA12__GPIO2_IO12        0x7d
 561                         MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14       0x7d
 562                         MX7D_PAD_EPDC_DATA13__GPIO2_IO13        0x7d
 563                         MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13       0x7d
 564                         MX7D_PAD_SD2_CD_B__GPIO5_IO9            0x7d
 565                         MX7D_PAD_EPDC_GDCLK__GPIO2_IO24         0x7d
 566                         MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21       0x7d
 567                         MX7D_PAD_EPDC_GDOE__GPIO2_IO25          0x7d
 568                         MX7D_PAD_EPDC_GDRL__GPIO2_IO26          0x7d
 569                         MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22       0x7d
 570                         MX7D_PAD_EPDC_SDCE0__GPIO2_IO20         0x7d
 571                         MX7D_PAD_SAI2_TX_BCLK__GPIO6_IO20       0x7d
 572                         MX7D_PAD_EPDC_SDCE1__GPIO2_IO21         0x7d
 573                         MX7D_PAD_SAI2_TX_SYNC__GPIO6_IO19       0x7d
 574                         MX7D_PAD_EPDC_SDCE2__GPIO2_IO22         0x7d
 575                         MX7D_PAD_EPDC_SDCE3__GPIO2_IO23         0x7d
 576                         MX7D_PAD_EPDC_GDSP__GPIO2_IO27          0x7d
 577                         MX7D_PAD_EPDC_SDCLK__GPIO2_IO16         0x7d
 578                         MX7D_PAD_EPDC_SDLE__GPIO2_IO17          0x7d
 579                         MX7D_PAD_EPDC_SDOE__GPIO2_IO18          0x7d
 580                         MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30       0x7d
 581                         MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31      0x7d
 582                 >;
 583         };
 584
 585         pinctrl_lcdif_dat: lcdifdatgrp {
 586                 fsl,pins = <
 587                         MX7D_PAD_LCD_DATA00__LCD_DATA0          0x79
 588                         MX7D_PAD_LCD_DATA01__LCD_DATA1          0x79
 589                         MX7D_PAD_LCD_DATA02__LCD_DATA2          0x79
 590                         MX7D_PAD_LCD_DATA03__LCD_DATA3          0x79
 591                         MX7D_PAD_LCD_DATA04__LCD_DATA4          0x79
 592                         MX7D_PAD_LCD_DATA05__LCD_DATA5          0x79
 593                         MX7D_PAD_LCD_DATA06__LCD_DATA6          0x79
 594                         MX7D_PAD_LCD_DATA07__LCD_DATA7          0x79
 595                         MX7D_PAD_LCD_DATA08__LCD_DATA8          0x79
 596                         MX7D_PAD_LCD_DATA09__LCD_DATA9          0x79
 597                         MX7D_PAD_LCD_DATA10__LCD_DATA10         0x79
 598                         MX7D_PAD_LCD_DATA11__LCD_DATA11         0x79
 599                         MX7D_PAD_LCD_DATA12__LCD_DATA12         0x79
 600                         MX7D_PAD_LCD_DATA13__LCD_DATA13         0x79
 601                         MX7D_PAD_LCD_DATA14__LCD_DATA14         0x79
 602                         MX7D_PAD_LCD_DATA15__LCD_DATA15         0x79
 603                         MX7D_PAD_LCD_DATA16__LCD_DATA16         0x79
 604                         MX7D_PAD_LCD_DATA17__LCD_DATA17         0x79
 605                         MX7D_PAD_LCD_DATA18__LCD_DATA18         0x79
 606                         MX7D_PAD_LCD_DATA19__LCD_DATA19         0x79
 607                         MX7D_PAD_LCD_DATA20__LCD_DATA20         0x79
 608                         MX7D_PAD_LCD_DATA21__LCD_DATA21         0x79
 609                         MX7D_PAD_LCD_DATA22__LCD_DATA22         0x79
 610                         MX7D_PAD_LCD_DATA23__LCD_DATA23         0x79
 611                 >;
 612         };
 613
 614         pinctrl_lcdif_ctrl: lcdifctrlgrp {
 615                 fsl,pins = <
 616                         MX7D_PAD_LCD_CLK__LCD_CLK               0x79
 617                         MX7D_PAD_LCD_ENABLE__LCD_ENABLE         0x79
 618                         MX7D_PAD_LCD_VSYNC__LCD_VSYNC           0x79
 619                         MX7D_PAD_LCD_HSYNC__LCD_HSYNC           0x79
 620                 >;
 621         };
 622
 623         pinctrl_pwm2: pwm2grp {
 624                 fsl,pins = <
 625                         MX7D_PAD_GPIO1_IO09__PWM2_OUT           0x7d
 626                 >;
 627         };
 628
 629         pinctrl_uart1: uart1grp {
 630                 fsl,pins = <
 631                         MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX    0x79
 632                         MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX    0x79
 633                 >;
 634         };
 635
 636         pinctrl_uart2: uart2grp {
 637                 fsl,pins = <
 638                         MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX    0x79
 639                         MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX    0x79
 640                 >;
 641         };
 642
 643         pinctrl_uart3: uart3grp {
 644                 fsl,pins = <
 645                         MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX    0x79
 646                         MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX    0x79
 647                         MX7D_PAD_EPDC_DATA04__GPIO2_IO4         0x7d
 648                 >;
 649         };
 650
 651         pinctrl_uart6: uart6grp {
 652                 fsl,pins = <
 653                         MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX      0x79
 654                         MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX      0x79
 655                         MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS      0x79
 656                         MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS     0x79
 657                 >;
 658         };
 659
 660         pinctrl_usbotg2: usbotg2grp {
 661                 fsl,pins = <
 662                         MX7D_PAD_UART3_RTS_B__USB_OTG2_OC       0x7d
 663                         MX7D_PAD_UART3_CTS_B__GPIO4_IO7         0x14
 664                 >;
 665         };
 666
 667         pinctrl_usdhc1: usdhc1grp {
 668                 fsl,pins = <
 669                         MX7D_PAD_SD1_CMD__SD1_CMD               0x59
 670                         MX7D_PAD_SD1_CLK__SD1_CLK               0x19
 671                         MX7D_PAD_SD1_DATA0__SD1_DATA0           0x59
 672                         MX7D_PAD_SD1_DATA1__SD1_DATA1           0x59
 673                         MX7D_PAD_SD1_DATA2__SD1_DATA2           0x59
 674                         MX7D_PAD_SD1_DATA3__SD1_DATA3           0x59
 675                         MX7D_PAD_GPIO1_IO08__SD1_VSELECT        0x75
 676                         MX7D_PAD_SD1_CD_B__GPIO5_IO0            0x75
 677                 >;
 678         };
 679
 680         pinctrl_usdhc2: usdhc2grp {
 681                 fsl,pins = <
 682                         MX7D_PAD_SD2_CMD__SD2_CMD               0x59
 683                         MX7D_PAD_SD2_CLK__SD2_CLK               0x19
 684                         MX7D_PAD_SD2_DATA0__SD2_DATA0           0x59
 685                         MX7D_PAD_SD2_DATA1__SD2_DATA1           0x59
 686                         MX7D_PAD_SD2_DATA2__SD2_DATA2           0x59
 687                         MX7D_PAD_SD2_DATA3__SD2_DATA3           0x59
 688                         MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20        0x59
 689                         MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21        0x59
 690                 >;
 691         };
 692
 693         pinctrl_usdhc3: usdhc3grp {
 694                 fsl,pins = <
 695                         MX7D_PAD_SD3_CMD__SD3_CMD               0x59
 696                         MX7D_PAD_SD3_CLK__SD3_CLK               0x19
 697                         MX7D_PAD_SD3_DATA0__SD3_DATA0           0x59
 698                         MX7D_PAD_SD3_DATA1__SD3_DATA1           0x59
 699                         MX7D_PAD_SD3_DATA2__SD3_DATA2           0x59
 700                         MX7D_PAD_SD3_DATA3__SD3_DATA3           0x59
 701                         MX7D_PAD_SD3_DATA4__SD3_DATA4           0x59
 702                         MX7D_PAD_SD3_DATA5__SD3_DATA5           0x59
 703                         MX7D_PAD_SD3_DATA6__SD3_DATA6           0x59
 704                         MX7D_PAD_SD3_DATA7__SD3_DATA7           0x59
 705                 >;
 706         };
 707 };
 708
 709 &iomuxc_lpsr {
 710         pinctrl-names = "default";
 711         pinctrl-0 = <&pinctrl_hog_2>;
 712
 713         pinctrl_hog_2: hoggrp-2 {
 714                 fsl,pins = <
 715                         MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2     0x7d
 716                         MX7D_PAD_LPSR_GPIO1_IO03__CCM_CLKO2     0x7d
 717                 >;
 718         };
 719
 720         pinctrl_backlight_j9: backlightj9grp {
 721                 fsl,pins = <
 722                         MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7     0x7d
 723                 >;
 724         };
 725
 726         pinctrl_pwm1: pwm1grp {
 727                 fsl,pins = <
 728                         MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT      0x7d
 729                 >;
 730         };
 731
 732         pinctrl_usbotg1: usbotg1grp {
 733                 fsl,pins = <
 734                         MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC   0x7d
 735                         MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5     0x14
 736                 >;
 737         };
 738
 739         pinctrl_wdog1: wdog1grp {
 740                 fsl,pins = <
 741                         MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG_B  0x75
 742                 >;
 743         };
 744 };