arch/arm/boot/dts/meson8.dtsi

   1 /*
   2  * Copyright 2014 Carlo Caione <carlo@caione.org>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  *     You should have received a copy of the GNU General Public License
  20  *     along with this program. If not, see <http://www.gnu.org/licenses/>.
  21  *
  22  * Or, alternatively,
  23  *
  24  *  b) Permission is hereby granted, free of charge, to any person
  25  *     obtaining a copy of this software and associated documentation
  26  *     files (the "Software"), to deal in the Software without
  27  *     restriction, including without limitation the rights to use,
  28  *     copy, modify, merge, publish, distribute, sublicense, and/or
  29  *     sell copies of the Software, and to permit persons to whom the
  30  *     Software is furnished to do so, subject to the following
  31  *     conditions:
  32  *
  33  *     The above copyright notice and this permission notice shall be
  34  *     included in all copies or substantial portions of the Software.
  35  *
  36  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  37  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  38  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  39  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  40  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  41  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  42  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  43  *     OTHER DEALINGS IN THE SOFTWARE.
  44  */
  45
  46 #include <dt-bindings/gpio/meson8-gpio.h>
  47 /include/ "meson.dtsi"
  48
  49 / {
  50         model = "Amlogic Meson8 SoC";
  51         compatible = "amlogic,meson8";
  52
  53         interrupt-parent = <&gic>;
  54
  55         cpus {
  56                 #address-cells = <1>;
  57                 #size-cells = <0>;
  58
  59                 cpu@200 {
  60                         device_type = "cpu";
  61                         compatible = "arm,cortex-a9";
  62                         next-level-cache = <&L2>;
  63                         reg = <0x200>;
  64                 };
  65
  66                 cpu@201 {
  67                         device_type = "cpu";
  68                         compatible = "arm,cortex-a9";
  69                         next-level-cache = <&L2>;
  70                         reg = <0x201>;
  71                 };
  72
  73                 cpu@202 {
  74                         device_type = "cpu";
  75                         compatible = "arm,cortex-a9";
  76                         next-level-cache = <&L2>;
  77                         reg = <0x202>;
  78                 };
  79
  80                 cpu@203 {
  81                         device_type = "cpu";
  82                         compatible = "arm,cortex-a9";
  83                         next-level-cache = <&L2>;
  84                         reg = <0x203>;
  85                 };
  86         };
  87
  88         clk81: clk@0 {
  89                 #clock-cells = <0>;
  90                 compatible = "fixed-clock";
  91                 clock-frequency = <141666666>;
  92         };
  93
  94         pinctrl_cbus: pinctrl@c1109880 {
  95                 compatible = "amlogic,meson8-cbus-pinctrl";
  96                 reg = <0xc1109880 0x10>;
  97                 #address-cells = <1>;
  98                 #size-cells = <1>;
  99                 ranges;
 100
 101                 gpio: banks@c11080b0 {
 102                         reg = <0xc11080b0 0x28>,
 103                               <0xc11080e8 0x18>,
 104                               <0xc1108120 0x18>,
 105                               <0xc1108030 0x30>;
 106                         reg-names = "mux", "pull", "pull-enable", "gpio";
 107                         gpio-controller;
 108                         #gpio-cells = <2>;
 109                 };
 110
 111                 spi_nor_pins: nor {
 112                         mux {
 113                                 groups = "nor_d", "nor_q", "nor_c", "nor_cs";
 114                                 function = "nor";
 115                         };
 116                 };
 117
 118                 ir_recv_pins: remote {
 119                         mux {
 120                                 groups = "remote_input";
 121                                 function = "remote";
 122                         };
 123                 };
 124
 125                 eth_pins: ethernet {
 126                         mux {
 127                                 groups = "eth_tx_clk_50m", "eth_tx_en",
 128                                          "eth_txd1", "eth_txd0",
 129                                          "eth_rx_clk_in", "eth_rx_dv",
 130                                          "eth_rxd1", "eth_rxd0", "eth_mdio",
 131                                          "eth_mdc";
 132                                 function = "ethernet";
 133                         };
 134                 };
 135         };
 136
 137         pinctrl_aobus: pinctrl@c8100084 {
 138                 compatible = "amlogic,meson8-aobus-pinctrl";
 139                 reg = <0xc8100084 0xc>;
 140                 #address-cells = <1>;
 141                 #size-cells = <1>;
 142                 ranges;
 143
 144                 gpio_ao: ao-bank@c1108030 {
 145                         reg = <0xc8100014 0x4>,
 146                               <0xc810002c 0x4>,
 147                               <0xc8100024 0x8>;
 148                         reg-names = "mux", "pull", "gpio";
 149                         gpio-controller;
 150                         #gpio-cells = <2>;
 151                 };
 152
 153                 uart_ao_a_pins: uart_ao_a {
 154                         mux {
 155                                 groups = "uart_tx_ao_a", "uart_rx_ao_a";
 156                                 function = "uart_ao";
 157                         };
 158                 };
 159
 160                 i2c_ao_pins: i2c_mst_ao {
 161                         mux {
 162                                 groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao";
 163                                 function = "i2c_mst_ao";
 164                         };
 165                 };
 166         };
 167 }; /* end of / */