arch/arm/boot/dts/qcom-ipq8064.dtsi

   1 /dts-v1/;
   2
   3 #include "skeleton.dtsi"
   4 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
   5 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
   6 #include <dt-bindings/soc/qcom,gsbi.h>
   7
   8 / {
   9         model = "Qualcomm IPQ8064";
  10         compatible = "qcom,ipq8064";
  11         interrupt-parent = <&intc>;
  12
  13         cpus {
  14                 #address-cells = <1>;
  15                 #size-cells = <0>;
  16
  17                 cpu@0 {
  18                         compatible = "qcom,krait";
  19                         enable-method = "qcom,kpss-acc-v1";
  20                         device_type = "cpu";
  21                         reg = <0>;
  22                         next-level-cache = <&L2>;
  23                         qcom,acc = <&acc0>;
  24                         qcom,saw = <&saw0>;
  25                 };
  26
  27                 cpu@1 {
  28                         compatible = "qcom,krait";
  29                         enable-method = "qcom,kpss-acc-v1";
  30                         device_type = "cpu";
  31                         reg = <1>;
  32                         next-level-cache = <&L2>;
  33                         qcom,acc = <&acc1>;
  34                         qcom,saw = <&saw1>;
  35                 };
  36
  37                 L2: l2-cache {
  38                         compatible = "cache";
  39                         cache-level = <2>;
  40                 };
  41         };
  42
  43         cpu-pmu {
  44                 compatible = "qcom,krait-pmu";
  45                 interrupts = <1 10 0x304>;
  46         };
  47
  48         reserved-memory {
  49                 #address-cells = <1>;
  50                 #size-cells = <1>;
  51                 ranges;
  52
  53                 nss@40000000 {
  54                         reg = <0x40000000 0x1000000>;
  55                         no-map;
  56                 };
  57
  58                 smem@41000000 {
  59                         reg = <0x41000000 0x200000>;
  60                         no-map;
  61                 };
  62         };
  63
  64         clocks {
  65                 cxo_board {
  66                         compatible = "fixed-clock";
  67                         #clock-cells = <0>;
  68                         clock-frequency = <25000000>;
  69                 };
  70
  71                 pxo_board {
  72                         compatible = "fixed-clock";
  73                         #clock-cells = <0>;
  74                         clock-frequency = <25000000>;
  75                 };
  76
  77                 sleep_clk: sleep_clk {
  78                         compatible = "fixed-clock";
  79                         clock-frequency = <32768>;
  80                         #clock-cells = <0>;
  81                 };
  82         };
  83
  84         soc: soc {
  85                 #address-cells = <1>;
  86                 #size-cells = <1>;
  87                 ranges;
  88                 compatible = "simple-bus";
  89
  90                 lpass@28100000 {
  91                         compatible = "qcom,lpass-cpu";
  92                         status = "disabled";
  93                         clocks = <&lcc AHBIX_CLK>,
  94                                         <&lcc MI2S_OSR_CLK>,
  95                                         <&lcc MI2S_BIT_CLK>;
  96                         clock-names = "ahbix-clk",
  97                                         "mi2s-osr-clk",
  98                                         "mi2s-bit-clk";
  99                         interrupts = <0 85 1>;
 100                         interrupt-names = "lpass-irq-lpaif";
 101                         reg = <0x28100000 0x10000>;
 102                         reg-names = "lpass-lpaif";
 103                 };
 104
 105                 qcom_pinmux: pinmux@800000 {
 106                         compatible = "qcom,ipq8064-pinctrl";
 107                         reg = <0x800000 0x4000>;
 108
 109                         gpio-controller;
 110                         #gpio-cells = <2>;
 111                         interrupt-controller;
 112                         #interrupt-cells = <2>;
 113                         interrupts = <0 16 0x4>;
 114                 };
 115
 116                 intc: interrupt-controller@2000000 {
 117                         compatible = "qcom,msm-qgic2";
 118                         interrupt-controller;
 119                         #interrupt-cells = <3>;
 120                         reg = <0x02000000 0x1000>,
 121                               <0x02002000 0x1000>;
 122                 };
 123
 124                 timer@200a000 {
 125                         compatible = "qcom,kpss-timer",
 126                                      "qcom,kpss-wdt-ipq8064", "qcom,msm-timer";
 127                         interrupts = <1 1 0x301>,
 128                                      <1 2 0x301>,
 129                                      <1 3 0x301>,
 130                                      <1 4 0x301>,
 131                                      <1 5 0x301>;
 132                         reg = <0x0200a000 0x100>;
 133                         clock-frequency = <25000000>,
 134                                           <32768>;
 135                         clocks = <&sleep_clk>;
 136                         clock-names = "sleep";
 137                         cpu-offset = <0x80000>;
 138                 };
 139
 140                 acc0: clock-controller@2088000 {
 141                         compatible = "qcom,kpss-acc-v1";
 142                         reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
 143                 };
 144
 145                 acc1: clock-controller@2098000 {
 146                         compatible = "qcom,kpss-acc-v1";
 147                         reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
 148                 };
 149
 150                 saw0: regulator@2089000 {
 151                         compatible = "qcom,saw2";
 152                         reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
 153                         regulator;
 154                 };
 155
 156                 saw1: regulator@2099000 {
 157                         compatible = "qcom,saw2";
 158                         reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
 159                         regulator;
 160                 };
 161
 162                 gsbi2: gsbi@12480000 {
 163                         compatible = "qcom,gsbi-v1.0.0";
 164                         cell-index = <2>;
 165                         reg = <0x12480000 0x100>;
 166                         clocks = <&gcc GSBI2_H_CLK>;
 167                         clock-names = "iface";
 168                         #address-cells = <1>;
 169                         #size-cells = <1>;
 170                         ranges;
 171                         status = "disabled";
 172
 173                         syscon-tcsr = <&tcsr>;
 174
 175                         serial@12490000 {
 176                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 177                                 reg = <0x12490000 0x1000>,
 178                                       <0x12480000 0x1000>;
 179                                 interrupts = <0 195 0x0>;
 180                                 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
 181                                 clock-names = "core", "iface";
 182                                 status = "disabled";
 183                         };
 184
 185                         i2c@124a0000 {
 186                                 compatible = "qcom,i2c-qup-v1.1.1";
 187                                 reg = <0x124a0000 0x1000>;
 188                                 interrupts = <0 196 0>;
 189
 190                                 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
 191                                 clock-names = "core", "iface";
 192                                 status = "disabled";
 193
 194                                 #address-cells = <1>;
 195                                 #size-cells = <0>;
 196                         };
 197
 198                 };
 199
 200                 gsbi4: gsbi@16300000 {
 201                         compatible = "qcom,gsbi-v1.0.0";
 202                         cell-index = <4>;
 203                         reg = <0x16300000 0x100>;
 204                         clocks = <&gcc GSBI4_H_CLK>;
 205                         clock-names = "iface";
 206                         #address-cells = <1>;
 207                         #size-cells = <1>;
 208                         ranges;
 209                         status = "disabled";
 210
 211                         syscon-tcsr = <&tcsr>;
 212
 213                         gsbi4_serial: serial@16340000 {
 214                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 215                                 reg = <0x16340000 0x1000>,
 216                                       <0x16300000 0x1000>;
 217                                 interrupts = <0 152 0x0>;
 218                                 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
 219                                 clock-names = "core", "iface";
 220                                 status = "disabled";
 221                         };
 222
 223                         i2c@16380000 {
 224                                 compatible = "qcom,i2c-qup-v1.1.1";
 225                                 reg = <0x16380000 0x1000>;
 226                                 interrupts = <0 153 0>;
 227
 228                                 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
 229                                 clock-names = "core", "iface";
 230                                 status = "disabled";
 231
 232                                 #address-cells = <1>;
 233                                 #size-cells = <0>;
 234                         };
 235                 };
 236
 237                 gsbi5: gsbi@1a200000 {
 238                         compatible = "qcom,gsbi-v1.0.0";
 239                         cell-index = <5>;
 240                         reg = <0x1a200000 0x100>;
 241                         clocks = <&gcc GSBI5_H_CLK>;
 242                         clock-names = "iface";
 243                         #address-cells = <1>;
 244                         #size-cells = <1>;
 245                         ranges;
 246                         status = "disabled";
 247
 248                         syscon-tcsr = <&tcsr>;
 249
 250                         serial@1a240000 {
 251                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 252                                 reg = <0x1a240000 0x1000>,
 253                                       <0x1a200000 0x1000>;
 254                                 interrupts = <0 154 0x0>;
 255                                 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
 256                                 clock-names = "core", "iface";
 257                                 status = "disabled";
 258                         };
 259
 260                         i2c@1a280000 {
 261                                 compatible = "qcom,i2c-qup-v1.1.1";
 262                                 reg = <0x1a280000 0x1000>;
 263                                 interrupts = <0 155 0>;
 264
 265                                 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
 266                                 clock-names = "core", "iface";
 267                                 status = "disabled";
 268
 269                                 #address-cells = <1>;
 270                                 #size-cells = <0>;
 271                         };
 272
 273                         spi@1a280000 {
 274                                 compatible = "qcom,spi-qup-v1.1.1";
 275                                 reg = <0x1a280000 0x1000>;
 276                                 interrupts = <0 155 0>;
 277
 278                                 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
 279                                 clock-names = "core", "iface";
 280                                 status = "disabled";
 281
 282                                 #address-cells = <1>;
 283                                 #size-cells = <0>;
 284                         };
 285                 };
 286
 287                 sata_phy: sata-phy@1b400000 {
 288                         compatible = "qcom,ipq806x-sata-phy";
 289                         reg = <0x1b400000 0x200>;
 290
 291                         clocks = <&gcc SATA_PHY_CFG_CLK>;
 292                         clock-names = "cfg";
 293
 294                         #phy-cells = <0>;
 295                         status = "disabled";
 296                 };
 297
 298                 sata@29000000 {
 299                         compatible = "qcom,ipq806x-ahci", "generic-ahci";
 300                         reg = <0x29000000 0x180>;
 301
 302                         interrupts = <0 209 0x0>;
 303
 304                         clocks = <&gcc SFAB_SATA_S_H_CLK>,
 305                                  <&gcc SATA_H_CLK>,
 306                                  <&gcc SATA_A_CLK>,
 307                                  <&gcc SATA_RXOOB_CLK>,
 308                                  <&gcc SATA_PMALIVE_CLK>;
 309                         clock-names = "slave_face", "iface", "core",
 310                                         "rxoob", "pmalive";
 311
 312                         assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
 313                         assigned-clock-rates = <100000000>, <100000000>;
 314
 315                         phys = <&sata_phy>;
 316                         phy-names = "sata-phy";
 317                         status = "disabled";
 318                 };
 319
 320                 qcom,ssbi@500000 {
 321                         compatible = "qcom,ssbi";
 322                         reg = <0x00500000 0x1000>;
 323                         qcom,controller-type = "pmic-arbiter";
 324                 };
 325
 326                 gcc: clock-controller@900000 {
 327                         compatible = "qcom,gcc-ipq8064";
 328                         reg = <0x00900000 0x4000>;
 329                         #clock-cells = <1>;
 330                         #reset-cells = <1>;
 331                 };
 332
 333                 tcsr: syscon@1a400000 {
 334                         compatible = "qcom,tcsr-ipq8064", "syscon";
 335                         reg = <0x1a400000 0x100>;
 336                 };
 337
 338                 lcc: clock-controller@28000000 {
 339                         compatible = "qcom,lcc-ipq8064";
 340                         reg = <0x28000000 0x1000>;
 341                         #clock-cells = <1>;
 342                         #reset-cells = <1>;
 343                 };
 344
 345         };
 346 };