| blob | b8aa256bd51533ba4ba7484aa02d26738c040535 |
1 /*
2 * Device Tree Source for the r7s72100 SoC
3 *
4 * Copyright (C) 2013-14 Renesas Solutions Corp.
5 * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
12 #include <dt-bindings/clock/r7s72100-clock.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
16 / {
17 compatible = "renesas,r7s72100";
18 interrupt-parent = <&gic>;
19 #address-cells = <1>;
20 #size-cells = <1>;
22 aliases {
23 i2c0 = &i2c0;
24 i2c1 = &i2c1;
25 i2c2 = &i2c2;
26 i2c3 = &i2c3;
27 spi0 = &spi0;
28 spi1 = &spi1;
29 spi2 = &spi2;
30 spi3 = &spi3;
31 spi4 = &spi4;
32 };
34 clocks {
35 ranges;
36 #address-cells = <1>;
37 #size-cells = <1>;
39 /* External clocks */
40 extal_clk: extal {
41 #clock-cells = <0>;
42 compatible = "fixed-clock";
43 /* If clk present, value must be set by board */
44 clock-frequency = <0>;
45 };
47 usb_x1_clk: usb_x1 {
48 #clock-cells = <0>;
49 compatible = "fixed-clock";
50 /* If clk present, value must be set by board */
51 clock-frequency = <0>;
52 };
54 /* Fixed factor clocks */
55 b_clk: b {
56 #clock-cells = <0>;
57 compatible = "fixed-factor-clock";
58 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
59 clock-mult = <1>;
60 clock-div = <3>;
61 };
62 p1_clk: p1 {
63 #clock-cells = <0>;
64 compatible = "fixed-factor-clock";
65 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
66 clock-mult = <1>;
67 clock-div = <6>;
68 };
69 p0_clk: p0 {
70 #clock-cells = <0>;
71 compatible = "fixed-factor-clock";
72 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
73 clock-mult = <1>;
74 clock-div = <12>;
75 };
77 /* Special CPG clocks */
78 cpg_clocks: cpg_clocks@fcfe0000 {
79 #clock-cells = <1>;
80 compatible = "renesas,r7s72100-cpg-clocks",
81 "renesas,rz-cpg-clocks";
82 reg = <0xfcfe0000 0x18>;
83 clocks = <&extal_clk>, <&usb_x1_clk>;
84 clock-output-names = "pll", "i", "g";
85 #power-domain-cells = <0>;
86 };
88 /* MSTP clocks */
89 mstp3_clks: mstp3_clks@fcfe0420 {
90 #clock-cells = <1>;
91 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
92 reg = <0xfcfe0420 4>;
93 clocks = <&p0_clk>;
94 clock-indices = <R7S72100_CLK_MTU2>;
95 clock-output-names = "mtu2";
96 };
98 mstp4_clks: mstp4_clks@fcfe0424 {
99 #clock-cells = <1>;
100 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
101 reg = <0xfcfe0424 4>;
102 clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
103 <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
104 clock-indices = <
105 R7S72100_CLK_SCIF0 R7S72100_CLK_SCIF1 R7S72100_CLK_SCIF2 R7S72100_CLK_SCIF3
106 R7S72100_CLK_SCIF4 R7S72100_CLK_SCIF5 R7S72100_CLK_SCIF6 R7S72100_CLK_SCIF7
107 >;
108 clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7";
109 };
111 mstp5_clks: mstp5_clks@fcfe0428 {
112 #clock-cells = <1>;
113 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
114 reg = <0xfcfe0428 4>;
115 clocks = <&p0_clk>, <&p0_clk>;
116 clock-indices = <R7S72100_CLK_OSTM0 R7S72100_CLK_OSTM1>;
117 clock-output-names = "ostm0", "ostm1";
118 };
120 mstp7_clks: mstp7_clks@fcfe0430 {
121 #clock-cells = <1>;
122 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
123 reg = <0xfcfe0430 4>;
124 clocks = <&p0_clk>;
125 clock-indices = <R7S72100_CLK_ETHER>;
126 clock-output-names = "ether";
127 };
129 mstp8_clks: mstp8_clks@fcfe0434 {
130 #clock-cells = <1>;
131 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
132 reg = <0xfcfe0434 4>;
133 clocks = <&p1_clk>;
134 clock-indices = <R7S72100_CLK_MMCIF>;
135 clock-output-names = "mmcif";
136 };
138 mstp9_clks: mstp9_clks@fcfe0438 {
139 #clock-cells = <1>;
140 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
141 reg = <0xfcfe0438 4>;
142 clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>;
143 clock-indices = <
144 R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3
145 >;
146 clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3";
147 };
149 mstp10_clks: mstp10_clks@fcfe043c {
150 #clock-cells = <1>;
151 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
152 reg = <0xfcfe043c 4>;
153 clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
154 <&p1_clk>;
155 clock-indices = <
156 R7S72100_CLK_SPI0 R7S72100_CLK_SPI1 R7S72100_CLK_SPI2 R7S72100_CLK_SPI3
157 R7S72100_CLK_SPI4
158 >;
159 clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4";
160 };
161 mstp12_clks: mstp12_clks@fcfe0444 {
162 #clock-cells = <1>;
163 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
164 reg = <0xfcfe0444 4>;
165 clocks = <&p1_clk>, <&p1_clk>;
166 clock-indices = <R7S72100_CLK_SDHI1 R7S72100_CLK_SDHI0>;
167 clock-output-names = "sdhi1", "sdhi0";
168 };
169 };
171 cpus {
172 #address-cells = <1>;
173 #size-cells = <0>;
175 cpu@0 {
176 device_type = "cpu";
177 compatible = "arm,cortex-a9";
178 reg = <0>;
179 clock-frequency = <400000000>;
180 };
181 };
183 scif0: serial@e8007000 {
184 compatible = "renesas,scif-r7s72100", "renesas,scif";
185 reg = <0xe8007000 64>;
186 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
187 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
188 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
189 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
190 clocks = <&mstp4_clks R7S72100_CLK_SCIF0>;
191 clock-names = "fck";
192 power-domains = <&cpg_clocks>;
193 status = "disabled";
194 };
196 scif1: serial@e8007800 {
197 compatible = "renesas,scif-r7s72100", "renesas,scif";
198 reg = <0xe8007800 64>;
199 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
201 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
202 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
203 clocks = <&mstp4_clks R7S72100_CLK_SCIF1>;
204 clock-names = "fck";
205 power-domains = <&cpg_clocks>;
206 status = "disabled";
207 };
209 scif2: serial@e8008000 {
210 compatible = "renesas,scif-r7s72100", "renesas,scif";
211 reg = <0xe8008000 64>;
212 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
213 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
216 clocks = <&mstp4_clks R7S72100_CLK_SCIF2>;
217 clock-names = "fck";
218 power-domains = <&cpg_clocks>;
219 status = "disabled";
220 };
222 scif3: serial@e8008800 {
223 compatible = "renesas,scif-r7s72100", "renesas,scif";
224 reg = <0xe8008800 64>;
225 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
226 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
227 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
228 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
229 clocks = <&mstp4_clks R7S72100_CLK_SCIF3>;
230 clock-names = "fck";
231 power-domains = <&cpg_clocks>;
232 status = "disabled";
233 };
235 scif4: serial@e8009000 {
236 compatible = "renesas,scif-r7s72100", "renesas,scif";
237 reg = <0xe8009000 64>;
238 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
239 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
240 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
241 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
242 clocks = <&mstp4_clks R7S72100_CLK_SCIF4>;
243 clock-names = "fck";
244 power-domains = <&cpg_clocks>;
245 status = "disabled";
246 };
248 scif5: serial@e8009800 {
249 compatible = "renesas,scif-r7s72100", "renesas,scif";
250 reg = <0xe8009800 64>;
251 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
253 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
254 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
255 clocks = <&mstp4_clks R7S72100_CLK_SCIF5>;
256 clock-names = "fck";
257 power-domains = <&cpg_clocks>;
258 status = "disabled";
259 };
261 scif6: serial@e800a000 {
262 compatible = "renesas,scif-r7s72100", "renesas,scif";
263 reg = <0xe800a000 64>;
264 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
265 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
266 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
267 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
268 clocks = <&mstp4_clks R7S72100_CLK_SCIF6>;
269 clock-names = "fck";
270 power-domains = <&cpg_clocks>;
271 status = "disabled";
272 };
274 scif7: serial@e800a800 {
275 compatible = "renesas,scif-r7s72100", "renesas,scif";
276 reg = <0xe800a800 64>;
277 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
278 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
279 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
281 clocks = <&mstp4_clks R7S72100_CLK_SCIF7>;
282 clock-names = "fck";
283 power-domains = <&cpg_clocks>;
284 status = "disabled";
285 };
287 spi0: spi@e800c800 {
288 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
289 reg = <0xe800c800 0x24>;
290 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
293 interrupt-names = "error", "rx", "tx";
294 clocks = <&mstp10_clks R7S72100_CLK_SPI0>;
295 power-domains = <&cpg_clocks>;
296 num-cs = <1>;
297 #address-cells = <1>;
298 #size-cells = <0>;
299 status = "disabled";
300 };
302 spi1: spi@e800d000 {
303 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
304 reg = <0xe800d000 0x24>;
305 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
306 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
307 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
308 interrupt-names = "error", "rx", "tx";
309 clocks = <&mstp10_clks R7S72100_CLK_SPI1>;
310 power-domains = <&cpg_clocks>;
311 num-cs = <1>;
312 #address-cells = <1>;
313 #size-cells = <0>;
314 status = "disabled";
315 };
317 spi2: spi@e800d800 {
318 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
319 reg = <0xe800d800 0x24>;
320 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
321 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
322 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
323 interrupt-names = "error", "rx", "tx";
324 clocks = <&mstp10_clks R7S72100_CLK_SPI2>;
325 power-domains = <&cpg_clocks>;
326 num-cs = <1>;
327 #address-cells = <1>;
328 #size-cells = <0>;
329 status = "disabled";
330 };
332 spi3: spi@e800e000 {
333 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
334 reg = <0xe800e000 0x24>;
335 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
336 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
337 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
338 interrupt-names = "error", "rx", "tx";
339 clocks = <&mstp10_clks R7S72100_CLK_SPI3>;
340 power-domains = <&cpg_clocks>;
341 num-cs = <1>;
342 #address-cells = <1>;
343 #size-cells = <0>;
344 status = "disabled";
345 };
347 spi4: spi@e800e800 {
348 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
349 reg = <0xe800e800 0x24>;
350 interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
351 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
352 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
353 interrupt-names = "error", "rx", "tx";
354 clocks = <&mstp10_clks R7S72100_CLK_SPI4>;
355 power-domains = <&cpg_clocks>;
356 num-cs = <1>;
357 #address-cells = <1>;
358 #size-cells = <0>;
359 status = "disabled";
360 };
362 gic: interrupt-controller@e8201000 {
363 compatible = "arm,pl390";
364 #interrupt-cells = <3>;
365 #address-cells = <0>;
366 interrupt-controller;
367 reg = <0xe8201000 0x1000>,
368 <0xe8202000 0x1000>;
369 };
371 i2c0: i2c@fcfee000 {
372 #address-cells = <1>;
373 #size-cells = <0>;
374 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
375 reg = <0xfcfee000 0x44>;
376 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
377 <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
378 <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
379 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
380 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
381 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
382 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
383 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
384 clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
385 clock-frequency = <100000>;
386 power-domains = <&cpg_clocks>;
387 status = "disabled";
388 };
390 i2c1: i2c@fcfee400 {
391 #address-cells = <1>;
392 #size-cells = <0>;
393 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
394 reg = <0xfcfee400 0x44>;
395 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
396 <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
397 <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
398 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
399 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
400 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
401 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
402 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
403 clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
404 clock-frequency = <100000>;
405 power-domains = <&cpg_clocks>;
406 status = "disabled";
407 };
409 i2c2: i2c@fcfee800 {
410 #address-cells = <1>;
411 #size-cells = <0>;
412 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
413 reg = <0xfcfee800 0x44>;
414 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
415 <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
416 <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
417 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
418 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
419 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
420 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
421 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
422 clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
423 clock-frequency = <100000>;
424 power-domains = <&cpg_clocks>;
425 status = "disabled";
426 };
428 i2c3: i2c@fcfeec00 {
429 #address-cells = <1>;
430 #size-cells = <0>;
431 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
432 reg = <0xfcfeec00 0x44>;
433 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
434 <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
435 <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
436 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
437 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
438 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
439 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
440 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
441 clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
442 clock-frequency = <100000>;
443 power-domains = <&cpg_clocks>;
444 status = "disabled";
445 };
447 mtu2: timer@fcff0000 {
448 compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
449 reg = <0xfcff0000 0x400>;
450 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
451 interrupt-names = "tgi0a";
452 clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
453 clock-names = "fck";
454 power-domains = <&cpg_clocks>;
455 status = "disabled";
456 };
458 ether: ethernet@e8203000 {
459 compatible = "renesas,ether-r7s72100";
460 reg = <0xe8203000 0x800>,
461 <0xe8204800 0x200>;
462 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
463 clocks = <&mstp7_clks R7S72100_CLK_ETHER>;
464 power-domains = <&cpg_clocks>;
465 phy-mode = "mii";
466 #address-cells = <1>;
467 #size-cells = <0>;
468 status = "disabled";
469 };
471 mmcif: mmc@e804c800 {
472 compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif";
473 reg = <0xe804c800 0x80>;
474 interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH
475 GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH
476 GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
477 clocks = <&mstp8_clks R7S72100_CLK_MMCIF>;
478 power-domains = <&cpg_clocks>;
479 reg-io-width = <4>;
480 bus-width = <8>;
481 status = "disabled";
482 };
484 sdhi0: sd@e804e000 {
485 compatible = "renesas,sdhi-r7s72100";
486 reg = <0xe804e000 0x100>;
487 interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH
488 GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH
489 GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
491 clocks = <&mstp12_clks R7S72100_CLK_SDHI0>;
492 cap-sd-highspeed;
493 cap-sdio-irq;
494 status = "disabled";
495 };
497 sdhi1: sd@e804e800 {
498 compatible = "renesas,sdhi-r7s72100";
499 reg = <0xe804e800 0x100>;
500 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH
501 GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH
502 GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
504 clocks = <&mstp12_clks R7S72100_CLK_SDHI1>;
505 cap-sd-highspeed;
506 cap-sdio-irq;
507 status = "disabled";
508 };
510 ostm0: timer@fcfec000 {
511 compatible = "renesas,r7s72100-ostm", "renesas,ostm";
512 reg = <0xfcfec000 0x30>;
513 interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
514 clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
515 power-domains = <&cpg_clocks>;
516 status = "disabled";
517 };
519 ostm1: timer@fcfec400 {
520 compatible = "renesas,r7s72100-ostm", "renesas,ostm";
521 reg = <0xfcfec400 0x30>;
522 interrupts = <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>;
523 clocks = <&mstp5_clks R7S72100_CLK_OSTM1>;
524 power-domains = <&cpg_clocks>;
525 status = "disabled";
526 };
527 };