| blob | 48ce21c5e8db3c52990026226d85852cfec1e1a6 |
1 /*
2 * Device Tree Source for the r8a7793 SoC
3 *
4 * Copyright (C) 2014-2015 Renesas Electronics Corporation
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
11 #include <dt-bindings/clock/r8a7793-clock.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/power/r8a7793-sysc.h>
16 / {
17 compatible = "renesas,r8a7793";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
22 aliases {
23 i2c0 = &i2c0;
24 i2c1 = &i2c1;
25 i2c2 = &i2c2;
26 i2c3 = &i2c3;
27 i2c4 = &i2c4;
28 i2c5 = &i2c5;
29 i2c6 = &i2c6;
30 i2c7 = &i2c7;
31 i2c8 = &i2c8;
32 spi0 = &qspi;
33 };
35 cpus {
36 #address-cells = <1>;
37 #size-cells = <0>;
38 enable-method = "renesas,apmu";
40 cpu0: cpu@0 {
41 device_type = "cpu";
42 compatible = "arm,cortex-a15";
43 reg = <0>;
44 clock-frequency = <1500000000>;
45 voltage-tolerance = <1>; /* 1% */
46 clocks = <&cpg_clocks R8A7793_CLK_Z>;
47 clock-latency = <300000>; /* 300 us */
48 power-domains = <&sysc R8A7793_PD_CA15_CPU0>;
50 /* kHz - uV - OPPs unknown yet */
51 operating-points = <1500000 1000000>,
52 <1312500 1000000>,
53 <1125000 1000000>,
54 < 937500 1000000>,
55 < 750000 1000000>,
56 < 375000 1000000>;
57 next-level-cache = <&L2_CA15>;
58 };
60 cpu1: cpu@1 {
61 device_type = "cpu";
62 compatible = "arm,cortex-a15";
63 reg = <1>;
64 clock-frequency = <1500000000>;
65 power-domains = <&sysc R8A7793_PD_CA15_CPU1>;
66 };
68 L2_CA15: cache-controller@0 {
69 compatible = "cache";
70 reg = <0>;
71 power-domains = <&sysc R8A7793_PD_CA15_SCU>;
72 cache-unified;
73 cache-level = <2>;
74 };
75 };
77 apmu@e6152000 {
78 compatible = "renesas,r8a7793-apmu", "renesas,apmu";
79 reg = <0 0xe6152000 0 0x188>;
80 cpus = <&cpu0 &cpu1>;
81 };
83 thermal-zones {
84 cpu_thermal: cpu-thermal {
85 polling-delay-passive = <0>;
86 polling-delay = <0>;
88 thermal-sensors = <&thermal>;
90 trips {
91 cpu-crit {
92 temperature = <115000>;
93 hysteresis = <0>;
94 type = "critical";
95 };
96 };
97 cooling-maps {
98 };
99 };
100 };
102 gic: interrupt-controller@f1001000 {
103 compatible = "arm,gic-400";
104 #interrupt-cells = <3>;
105 #address-cells = <0>;
106 interrupt-controller;
107 reg = <0 0xf1001000 0 0x1000>,
108 <0 0xf1002000 0 0x2000>,
109 <0 0xf1004000 0 0x2000>,
110 <0 0xf1006000 0 0x2000>;
111 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
112 };
114 gpio0: gpio@e6050000 {
115 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
116 reg = <0 0xe6050000 0 0x50>;
117 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
118 #gpio-cells = <2>;
119 gpio-controller;
120 gpio-ranges = <&pfc 0 0 32>;
121 #interrupt-cells = <2>;
122 interrupt-controller;
123 clocks = <&mstp9_clks R8A7793_CLK_GPIO0>;
124 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
125 };
127 gpio1: gpio@e6051000 {
128 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
129 reg = <0 0xe6051000 0 0x50>;
130 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
131 #gpio-cells = <2>;
132 gpio-controller;
133 gpio-ranges = <&pfc 0 32 26>;
134 #interrupt-cells = <2>;
135 interrupt-controller;
136 clocks = <&mstp9_clks R8A7793_CLK_GPIO1>;
137 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
138 };
140 gpio2: gpio@e6052000 {
141 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
142 reg = <0 0xe6052000 0 0x50>;
143 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
144 #gpio-cells = <2>;
145 gpio-controller;
146 gpio-ranges = <&pfc 0 64 32>;
147 #interrupt-cells = <2>;
148 interrupt-controller;
149 clocks = <&mstp9_clks R8A7793_CLK_GPIO2>;
150 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
151 };
153 gpio3: gpio@e6053000 {
154 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
155 reg = <0 0xe6053000 0 0x50>;
156 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
157 #gpio-cells = <2>;
158 gpio-controller;
159 gpio-ranges = <&pfc 0 96 32>;
160 #interrupt-cells = <2>;
161 interrupt-controller;
162 clocks = <&mstp9_clks R8A7793_CLK_GPIO3>;
163 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
164 };
166 gpio4: gpio@e6054000 {
167 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
168 reg = <0 0xe6054000 0 0x50>;
169 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
170 #gpio-cells = <2>;
171 gpio-controller;
172 gpio-ranges = <&pfc 0 128 32>;
173 #interrupt-cells = <2>;
174 interrupt-controller;
175 clocks = <&mstp9_clks R8A7793_CLK_GPIO4>;
176 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
177 };
179 gpio5: gpio@e6055000 {
180 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
181 reg = <0 0xe6055000 0 0x50>;
182 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
183 #gpio-cells = <2>;
184 gpio-controller;
185 gpio-ranges = <&pfc 0 160 32>;
186 #interrupt-cells = <2>;
187 interrupt-controller;
188 clocks = <&mstp9_clks R8A7793_CLK_GPIO5>;
189 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
190 };
192 gpio6: gpio@e6055400 {
193 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
194 reg = <0 0xe6055400 0 0x50>;
195 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
196 #gpio-cells = <2>;
197 gpio-controller;
198 gpio-ranges = <&pfc 0 192 32>;
199 #interrupt-cells = <2>;
200 interrupt-controller;
201 clocks = <&mstp9_clks R8A7793_CLK_GPIO6>;
202 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
203 };
205 gpio7: gpio@e6055800 {
206 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
207 reg = <0 0xe6055800 0 0x50>;
208 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
209 #gpio-cells = <2>;
210 gpio-controller;
211 gpio-ranges = <&pfc 0 224 26>;
212 #interrupt-cells = <2>;
213 interrupt-controller;
214 clocks = <&mstp9_clks R8A7793_CLK_GPIO7>;
215 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
216 };
218 thermal: thermal@e61f0000 {
219 compatible = "renesas,thermal-r8a7793",
220 "renesas,rcar-gen2-thermal",
221 "renesas,rcar-thermal";
222 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
223 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
224 clocks = <&mstp5_clks R8A7793_CLK_THERMAL>;
225 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
226 #thermal-sensor-cells = <0>;
227 };
229 timer {
230 compatible = "arm,armv7-timer";
231 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
232 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
233 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
234 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
235 };
237 cmt0: timer@ffca0000 {
238 compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2";
239 reg = <0 0xffca0000 0 0x1004>;
240 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
241 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
242 clocks = <&mstp1_clks R8A7793_CLK_CMT0>;
243 clock-names = "fck";
244 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
246 renesas,channels-mask = <0x60>;
248 status = "disabled";
249 };
251 cmt1: timer@e6130000 {
252 compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2";
253 reg = <0 0xe6130000 0 0x1004>;
254 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
255 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
256 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
257 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
258 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
259 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
260 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
261 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
262 clocks = <&mstp3_clks R8A7793_CLK_CMT1>;
263 clock-names = "fck";
264 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
266 renesas,channels-mask = <0xff>;
268 status = "disabled";
269 };
271 irqc0: interrupt-controller@e61c0000 {
272 compatible = "renesas,irqc-r8a7793", "renesas,irqc";
273 #interrupt-cells = <2>;
274 interrupt-controller;
275 reg = <0 0xe61c0000 0 0x200>;
276 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
277 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
278 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
279 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&mstp4_clks R8A7793_CLK_IRQC>;
287 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
288 };
290 dmac0: dma-controller@e6700000 {
291 compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
292 reg = <0 0xe6700000 0 0x20000>;
293 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
294 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
295 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
296 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
297 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
298 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
299 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
300 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
301 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
302 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
303 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
304 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
305 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
306 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
307 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
308 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
309 interrupt-names = "error",
310 "ch0", "ch1", "ch2", "ch3",
311 "ch4", "ch5", "ch6", "ch7",
312 "ch8", "ch9", "ch10", "ch11",
313 "ch12", "ch13", "ch14";
314 clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC0>;
315 clock-names = "fck";
316 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
317 #dma-cells = <1>;
318 dma-channels = <15>;
319 };
321 dmac1: dma-controller@e6720000 {
322 compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
323 reg = <0 0xe6720000 0 0x20000>;
324 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
325 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
326 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
327 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
328 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
329 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
330 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
331 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
332 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
333 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
334 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
335 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
336 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
337 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
338 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
339 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
340 interrupt-names = "error",
341 "ch0", "ch1", "ch2", "ch3",
342 "ch4", "ch5", "ch6", "ch7",
343 "ch8", "ch9", "ch10", "ch11",
344 "ch12", "ch13", "ch14";
345 clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC1>;
346 clock-names = "fck";
347 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
348 #dma-cells = <1>;
349 dma-channels = <15>;
350 };
352 audma0: dma-controller@ec700000 {
353 compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
354 reg = <0 0xec700000 0 0x10000>;
355 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
356 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
357 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
358 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
359 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
360 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
361 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
362 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
363 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
364 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
365 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
366 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
367 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
368 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
369 interrupt-names = "error",
370 "ch0", "ch1", "ch2", "ch3",
371 "ch4", "ch5", "ch6", "ch7",
372 "ch8", "ch9", "ch10", "ch11",
373 "ch12";
374 clocks = <&mstp5_clks R8A7793_CLK_AUDIO_DMAC0>;
375 clock-names = "fck";
376 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
377 #dma-cells = <1>;
378 dma-channels = <13>;
379 };
381 audma1: dma-controller@ec720000 {
382 compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
383 reg = <0 0xec720000 0 0x10000>;
384 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
385 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
386 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
387 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
388 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
389 GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
390 GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
391 GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
392 GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
393 GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
394 GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
395 GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
396 GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
397 GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
398 interrupt-names = "error",
399 "ch0", "ch1", "ch2", "ch3",
400 "ch4", "ch5", "ch6", "ch7",
401 "ch8", "ch9", "ch10", "ch11",
402 "ch12";
403 clocks = <&mstp5_clks R8A7793_CLK_AUDIO_DMAC1>;
404 clock-names = "fck";
405 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
406 #dma-cells = <1>;
407 dma-channels = <13>;
408 };
410 /* The memory map in the User's Manual maps the cores to bus numbers */
411 i2c0: i2c@e6508000 {
412 #address-cells = <1>;
413 #size-cells = <0>;
414 compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c";
415 reg = <0 0xe6508000 0 0x40>;
416 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
417 clocks = <&mstp9_clks R8A7793_CLK_I2C0>;
418 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
419 i2c-scl-internal-delay-ns = <6>;
420 status = "disabled";
421 };
423 i2c1: i2c@e6518000 {
424 #address-cells = <1>;
425 #size-cells = <0>;
426 compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c";
427 reg = <0 0xe6518000 0 0x40>;
428 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
429 clocks = <&mstp9_clks R8A7793_CLK_I2C1>;
430 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
431 i2c-scl-internal-delay-ns = <6>;
432 status = "disabled";
433 };
435 i2c2: i2c@e6530000 {
436 #address-cells = <1>;
437 #size-cells = <0>;
438 compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c";
439 reg = <0 0xe6530000 0 0x40>;
440 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
441 clocks = <&mstp9_clks R8A7793_CLK_I2C2>;
442 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
443 i2c-scl-internal-delay-ns = <6>;
444 status = "disabled";
445 };
447 i2c3: i2c@e6540000 {
448 #address-cells = <1>;
449 #size-cells = <0>;
450 compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c";
451 reg = <0 0xe6540000 0 0x40>;
452 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
453 clocks = <&mstp9_clks R8A7793_CLK_I2C3>;
454 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
455 i2c-scl-internal-delay-ns = <6>;
456 status = "disabled";
457 };
459 i2c4: i2c@e6520000 {
460 #address-cells = <1>;
461 #size-cells = <0>;
462 compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c";
463 reg = <0 0xe6520000 0 0x40>;
464 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
465 clocks = <&mstp9_clks R8A7793_CLK_I2C4>;
466 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
467 i2c-scl-internal-delay-ns = <6>;
468 status = "disabled";
469 };
471 i2c5: i2c@e6528000 {
472 /* doesn't need pinmux */
473 #address-cells = <1>;
474 #size-cells = <0>;
475 compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c";
476 reg = <0 0xe6528000 0 0x40>;
477 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
478 clocks = <&mstp9_clks R8A7793_CLK_I2C5>;
479 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
480 i2c-scl-internal-delay-ns = <110>;
481 status = "disabled";
482 };
484 i2c6: i2c@e60b0000 {
485 /* doesn't need pinmux */
486 #address-cells = <1>;
487 #size-cells = <0>;
488 compatible = "renesas,iic-r8a7793", "renesas,rcar-gen2-iic",
489 "renesas,rmobile-iic";
490 reg = <0 0xe60b0000 0 0x425>;
491 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
492 clocks = <&mstp9_clks R8A7793_CLK_IICDVFS>;
493 dmas = <&dmac0 0x77>, <&dmac0 0x78>,
494 <&dmac1 0x77>, <&dmac1 0x78>;
495 dma-names = "tx", "rx", "tx", "rx";
496 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
497 status = "disabled";
498 };
500 i2c7: i2c@e6500000 {
501 #address-cells = <1>;
502 #size-cells = <0>;
503 compatible = "renesas,iic-r8a7793", "renesas,rcar-gen2-iic",
504 "renesas,rmobile-iic";
505 reg = <0 0xe6500000 0 0x425>;
506 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
507 clocks = <&mstp3_clks R8A7793_CLK_IIC0>;
508 dmas = <&dmac0 0x61>, <&dmac0 0x62>,
509 <&dmac1 0x61>, <&dmac1 0x62>;
510 dma-names = "tx", "rx", "tx", "rx";
511 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
512 status = "disabled";
513 };
515 i2c8: i2c@e6510000 {
516 #address-cells = <1>;
517 #size-cells = <0>;
518 compatible = "renesas,iic-r8a7793", "renesas,rcar-gen2-iic",
519 "renesas,rmobile-iic";
520 reg = <0 0xe6510000 0 0x425>;
521 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
522 clocks = <&mstp3_clks R8A7793_CLK_IIC1>;
523 dmas = <&dmac0 0x65>, <&dmac0 0x66>,
524 <&dmac1 0x65>, <&dmac1 0x66>;
525 dma-names = "tx", "rx", "tx", "rx";
526 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
527 status = "disabled";
528 };
530 pfc: pfc@e6060000 {
531 compatible = "renesas,pfc-r8a7793";
532 reg = <0 0xe6060000 0 0x250>;
533 };
535 sdhi0: sd@ee100000 {
536 compatible = "renesas,sdhi-r8a7793";
537 reg = <0 0xee100000 0 0x328>;
538 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
539 clocks = <&mstp3_clks R8A7793_CLK_SDHI0>;
540 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
541 <&dmac1 0xcd>, <&dmac1 0xce>;
542 dma-names = "tx", "rx", "tx", "rx";
543 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
544 status = "disabled";
545 };
547 sdhi1: sd@ee140000 {
548 compatible = "renesas,sdhi-r8a7793";
549 reg = <0 0xee140000 0 0x100>;
550 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
551 clocks = <&mstp3_clks R8A7793_CLK_SDHI1>;
552 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
553 <&dmac1 0xc1>, <&dmac1 0xc2>;
554 dma-names = "tx", "rx", "tx", "rx";
555 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
556 status = "disabled";
557 };
559 sdhi2: sd@ee160000 {
560 compatible = "renesas,sdhi-r8a7793";
561 reg = <0 0xee160000 0 0x100>;
562 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
563 clocks = <&mstp3_clks R8A7793_CLK_SDHI2>;
564 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
565 <&dmac1 0xd3>, <&dmac1 0xd4>;
566 dma-names = "tx", "rx", "tx", "rx";
567 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
568 status = "disabled";
569 };
571 mmcif0: mmc@ee200000 {
572 compatible = "renesas,mmcif-r8a7793", "renesas,sh-mmcif";
573 reg = <0 0xee200000 0 0x80>;
574 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
575 clocks = <&mstp3_clks R8A7793_CLK_MMCIF0>;
576 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
577 <&dmac1 0xd1>, <&dmac1 0xd2>;
578 dma-names = "tx", "rx", "tx", "rx";
579 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
580 reg-io-width = <4>;
581 status = "disabled";
582 max-frequency = <97500000>;
583 };
585 scifa0: serial@e6c40000 {
586 compatible = "renesas,scifa-r8a7793",
587 "renesas,rcar-gen2-scifa", "renesas,scifa";
588 reg = <0 0xe6c40000 0 64>;
589 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
590 clocks = <&mstp2_clks R8A7793_CLK_SCIFA0>;
591 clock-names = "fck";
592 dmas = <&dmac0 0x21>, <&dmac0 0x22>,
593 <&dmac1 0x21>, <&dmac1 0x22>;
594 dma-names = "tx", "rx", "tx", "rx";
595 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
596 status = "disabled";
597 };
599 scifa1: serial@e6c50000 {
600 compatible = "renesas,scifa-r8a7793",
601 "renesas,rcar-gen2-scifa", "renesas,scifa";
602 reg = <0 0xe6c50000 0 64>;
603 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
604 clocks = <&mstp2_clks R8A7793_CLK_SCIFA1>;
605 clock-names = "fck";
606 dmas = <&dmac0 0x25>, <&dmac0 0x26>,
607 <&dmac1 0x25>, <&dmac1 0x26>;
608 dma-names = "tx", "rx", "tx", "rx";
609 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
610 status = "disabled";
611 };
613 scifa2: serial@e6c60000 {
614 compatible = "renesas,scifa-r8a7793",
615 "renesas,rcar-gen2-scifa", "renesas,scifa";
616 reg = <0 0xe6c60000 0 64>;
617 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
618 clocks = <&mstp2_clks R8A7793_CLK_SCIFA2>;
619 clock-names = "fck";
620 dmas = <&dmac0 0x27>, <&dmac0 0x28>,
621 <&dmac1 0x27>, <&dmac1 0x28>;
622 dma-names = "tx", "rx", "tx", "rx";
623 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
624 status = "disabled";
625 };
627 scifa3: serial@e6c70000 {
628 compatible = "renesas,scifa-r8a7793",
629 "renesas,rcar-gen2-scifa", "renesas,scifa";
630 reg = <0 0xe6c70000 0 64>;
631 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
632 clocks = <&mstp11_clks R8A7793_CLK_SCIFA3>;
633 clock-names = "fck";
634 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
635 <&dmac1 0x1b>, <&dmac1 0x1c>;
636 dma-names = "tx", "rx", "tx", "rx";
637 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
638 status = "disabled";
639 };
641 scifa4: serial@e6c78000 {
642 compatible = "renesas,scifa-r8a7793",
643 "renesas,rcar-gen2-scifa", "renesas,scifa";
644 reg = <0 0xe6c78000 0 64>;
645 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
646 clocks = <&mstp11_clks R8A7793_CLK_SCIFA4>;
647 clock-names = "fck";
648 dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
649 <&dmac1 0x1f>, <&dmac1 0x20>;
650 dma-names = "tx", "rx", "tx", "rx";
651 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
652 status = "disabled";
653 };
655 scifa5: serial@e6c80000 {
656 compatible = "renesas,scifa-r8a7793",
657 "renesas,rcar-gen2-scifa", "renesas,scifa";
658 reg = <0 0xe6c80000 0 64>;
659 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
660 clocks = <&mstp11_clks R8A7793_CLK_SCIFA5>;
661 clock-names = "fck";
662 dmas = <&dmac0 0x23>, <&dmac0 0x24>,
663 <&dmac1 0x23>, <&dmac1 0x24>;
664 dma-names = "tx", "rx", "tx", "rx";
665 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
666 status = "disabled";
667 };
669 scifb0: serial@e6c20000 {
670 compatible = "renesas,scifb-r8a7793",
671 "renesas,rcar-gen2-scifb", "renesas,scifb";
672 reg = <0 0xe6c20000 0 0x100>;
673 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
674 clocks = <&mstp2_clks R8A7793_CLK_SCIFB0>;
675 clock-names = "fck";
676 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
677 <&dmac1 0x3d>, <&dmac1 0x3e>;
678 dma-names = "tx", "rx", "tx", "rx";
679 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
680 status = "disabled";
681 };
683 scifb1: serial@e6c30000 {
684 compatible = "renesas,scifb-r8a7793",
685 "renesas,rcar-gen2-scifb", "renesas,scifb";
686 reg = <0 0xe6c30000 0 0x100>;
687 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
688 clocks = <&mstp2_clks R8A7793_CLK_SCIFB1>;
689 clock-names = "fck";
690 dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
691 <&dmac1 0x19>, <&dmac1 0x1a>;
692 dma-names = "tx", "rx", "tx", "rx";
693 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
694 status = "disabled";
695 };
697 scifb2: serial@e6ce0000 {
698 compatible = "renesas,scifb-r8a7793",
699 "renesas,rcar-gen2-scifb", "renesas,scifb";
700 reg = <0 0xe6ce0000 0 0x100>;
701 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
702 clocks = <&mstp2_clks R8A7793_CLK_SCIFB2>;
703 clock-names = "fck";
704 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
705 <&dmac1 0x1d>, <&dmac1 0x1e>;
706 dma-names = "tx", "rx", "tx", "rx";
707 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
708 status = "disabled";
709 };
711 scif0: serial@e6e60000 {
712 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
713 "renesas,scif";
714 reg = <0 0xe6e60000 0 64>;
715 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
716 clocks = <&mstp7_clks R8A7793_CLK_SCIF0>, <&zs_clk>,
717 <&scif_clk>;
718 clock-names = "fck", "brg_int", "scif_clk";
719 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
720 <&dmac1 0x29>, <&dmac1 0x2a>;
721 dma-names = "tx", "rx", "tx", "rx";
722 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
723 status = "disabled";
724 };
726 scif1: serial@e6e68000 {
727 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
728 "renesas,scif";
729 reg = <0 0xe6e68000 0 64>;
730 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
731 clocks = <&mstp7_clks R8A7793_CLK_SCIF1>, <&zs_clk>,
732 <&scif_clk>;
733 clock-names = "fck", "brg_int", "scif_clk";
734 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
735 <&dmac1 0x2d>, <&dmac1 0x2e>;
736 dma-names = "tx", "rx", "tx", "rx";
737 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
738 status = "disabled";
739 };
741 scif2: serial@e6e58000 {
742 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
743 "renesas,scif";
744 reg = <0 0xe6e58000 0 64>;
745 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
746 clocks = <&mstp7_clks R8A7793_CLK_SCIF2>, <&zs_clk>,
747 <&scif_clk>;
748 clock-names = "fck", "brg_int", "scif_clk";
749 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
750 <&dmac1 0x2b>, <&dmac1 0x2c>;
751 dma-names = "tx", "rx", "tx", "rx";
752 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
753 status = "disabled";
754 };
756 scif3: serial@e6ea8000 {
757 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
758 "renesas,scif";
759 reg = <0 0xe6ea8000 0 64>;
760 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
761 clocks = <&mstp7_clks R8A7793_CLK_SCIF3>, <&zs_clk>,
762 <&scif_clk>;
763 clock-names = "fck", "brg_int", "scif_clk";
764 dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
765 <&dmac1 0x2f>, <&dmac1 0x30>;
766 dma-names = "tx", "rx", "tx", "rx";
767 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
768 status = "disabled";
769 };
771 scif4: serial@e6ee0000 {
772 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
773 "renesas,scif";
774 reg = <0 0xe6ee0000 0 64>;
775 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
776 clocks = <&mstp7_clks R8A7793_CLK_SCIF4>, <&zs_clk>,
777 <&scif_clk>;
778 clock-names = "fck", "brg_int", "scif_clk";
779 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
780 <&dmac1 0xfb>, <&dmac1 0xfc>;
781 dma-names = "tx", "rx", "tx", "rx";
782 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
783 status = "disabled";
784 };
786 scif5: serial@e6ee8000 {
787 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
788 "renesas,scif";
789 reg = <0 0xe6ee8000 0 64>;
790 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
791 clocks = <&mstp7_clks R8A7793_CLK_SCIF5>, <&zs_clk>,
792 <&scif_clk>;
793 clock-names = "fck", "brg_int", "scif_clk";
794 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
795 <&dmac1 0xfd>, <&dmac1 0xfe>;
796 dma-names = "tx", "rx", "tx", "rx";
797 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
798 status = "disabled";
799 };
801 hscif0: serial@e62c0000 {
802 compatible = "renesas,hscif-r8a7793",
803 "renesas,rcar-gen2-hscif", "renesas,hscif";
804 reg = <0 0xe62c0000 0 96>;
805 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
806 clocks = <&mstp7_clks R8A7793_CLK_HSCIF0>, <&zs_clk>,
807 <&scif_clk>;
808 clock-names = "fck", "brg_int", "scif_clk";
809 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
810 <&dmac1 0x39>, <&dmac1 0x3a>;
811 dma-names = "tx", "rx", "tx", "rx";
812 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
813 status = "disabled";
814 };
816 hscif1: serial@e62c8000 {
817 compatible = "renesas,hscif-r8a7793",
818 "renesas,rcar-gen2-hscif", "renesas,hscif";
819 reg = <0 0xe62c8000 0 96>;
820 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
821 clocks = <&mstp7_clks R8A7793_CLK_HSCIF1>, <&zs_clk>,
822 <&scif_clk>;
823 clock-names = "fck", "brg_int", "scif_clk";
824 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
825 <&dmac1 0x4d>, <&dmac1 0x4e>;
826 dma-names = "tx", "rx", "tx", "rx";
827 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
828 status = "disabled";
829 };
831 hscif2: serial@e62d0000 {
832 compatible = "renesas,hscif-r8a7793",
833 "renesas,rcar-gen2-hscif", "renesas,hscif";
834 reg = <0 0xe62d0000 0 96>;
835 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
836 clocks = <&mstp7_clks R8A7793_CLK_HSCIF2>, <&zs_clk>,
837 <&scif_clk>;
838 clock-names = "fck", "brg_int", "scif_clk";
839 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
840 <&dmac1 0x3b>, <&dmac1 0x3c>;
841 dma-names = "tx", "rx", "tx", "rx";
842 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
843 status = "disabled";
844 };
846 ether: ethernet@ee700000 {
847 compatible = "renesas,ether-r8a7793";
848 reg = <0 0xee700000 0 0x400>;
849 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
850 clocks = <&mstp8_clks R8A7793_CLK_ETHER>;
851 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
852 phy-mode = "rmii";
853 #address-cells = <1>;
854 #size-cells = <0>;
855 status = "disabled";
856 };
858 vin0: video@e6ef0000 {
859 compatible = "renesas,vin-r8a7793", "renesas,rcar-gen2-vin";
860 reg = <0 0xe6ef0000 0 0x1000>;
861 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
862 clocks = <&mstp8_clks R8A7793_CLK_VIN0>;
863 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
864 status = "disabled";
865 };
867 vin1: video@e6ef1000 {
868 compatible = "renesas,vin-r8a7793", "renesas,rcar-gen2-vin";
869 reg = <0 0xe6ef1000 0 0x1000>;
870 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
871 clocks = <&mstp8_clks R8A7793_CLK_VIN1>;
872 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
873 status = "disabled";
874 };
876 vin2: video@e6ef2000 {
877 compatible = "renesas,vin-r8a7793", "renesas,rcar-gen2-vin";
878 reg = <0 0xe6ef2000 0 0x1000>;
879 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
880 clocks = <&mstp8_clks R8A7793_CLK_VIN2>;
881 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
882 status = "disabled";
883 };
885 qspi: spi@e6b10000 {
886 compatible = "renesas,qspi-r8a7793", "renesas,qspi";
887 reg = <0 0xe6b10000 0 0x2c>;
888 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
889 clocks = <&mstp9_clks R8A7793_CLK_QSPI_MOD>;
890 dmas = <&dmac0 0x17>, <&dmac0 0x18>,
891 <&dmac1 0x17>, <&dmac1 0x18>;
892 dma-names = "tx", "rx", "tx", "rx";
893 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
894 num-cs = <1>;
895 #address-cells = <1>;
896 #size-cells = <0>;
897 status = "disabled";
898 };
900 du: display@feb00000 {
901 compatible = "renesas,du-r8a7793";
902 reg = <0 0xfeb00000 0 0x40000>,
903 <0 0xfeb90000 0 0x1c>;
904 reg-names = "du", "lvds.0";
905 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
906 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
907 clocks = <&mstp7_clks R8A7793_CLK_DU0>,
908 <&mstp7_clks R8A7793_CLK_DU1>,
909 <&mstp7_clks R8A7793_CLK_LVDS0>;
910 clock-names = "du.0", "du.1", "lvds.0";
911 status = "disabled";
913 ports {
914 #address-cells = <1>;
915 #size-cells = <0>;
917 port@0 {
918 reg = <0>;
919 du_out_rgb: endpoint {
920 };
921 };
922 port@1 {
923 reg = <1>;
924 du_out_lvds0: endpoint {
925 };
926 };
927 };
928 };
930 can0: can@e6e80000 {
931 compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can";
932 reg = <0 0xe6e80000 0 0x1000>;
933 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
934 clocks = <&mstp9_clks R8A7793_CLK_RCAN0>,
935 <&cpg_clocks R8A7793_CLK_RCAN>, <&can_clk>;
936 clock-names = "clkp1", "clkp2", "can_clk";
937 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
938 status = "disabled";
939 };
941 can1: can@e6e88000 {
942 compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can";
943 reg = <0 0xe6e88000 0 0x1000>;
944 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
945 clocks = <&mstp9_clks R8A7793_CLK_RCAN1>,
946 <&cpg_clocks R8A7793_CLK_RCAN>, <&can_clk>;
947 clock-names = "clkp1", "clkp2", "can_clk";
948 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
949 status = "disabled";
950 };
952 clocks {
953 #address-cells = <2>;
954 #size-cells = <2>;
955 ranges;
957 /* External root clock */
958 extal_clk: extal {
959 compatible = "fixed-clock";
960 #clock-cells = <0>;
961 /* This value must be overridden by the board. */
962 clock-frequency = <0>;
963 };
965 /*
966 * The external audio clocks are configured as 0 Hz fixed frequency clocks by
967 * default. Boards that provide audio clocks should override them.
968 */
969 audio_clk_a: audio_clk_a {
970 compatible = "fixed-clock";
971 #clock-cells = <0>;
972 clock-frequency = <0>;
973 };
974 audio_clk_b: audio_clk_b {
975 compatible = "fixed-clock";
976 #clock-cells = <0>;
977 clock-frequency = <0>;
978 };
979 audio_clk_c: audio_clk_c {
980 compatible = "fixed-clock";
981 #clock-cells = <0>;
982 clock-frequency = <0>;
983 };
985 /* External USB clock - can be overridden by the board */
986 usb_extal_clk: usb_extal {
987 compatible = "fixed-clock";
988 #clock-cells = <0>;
989 clock-frequency = <48000000>;
990 };
992 /* External CAN clock */
993 can_clk: can {
994 compatible = "fixed-clock";
995 #clock-cells = <0>;
996 /* This value must be overridden by the board. */
997 clock-frequency = <0>;
998 };
1000 /* External SCIF clock */
1001 scif_clk: scif {
1002 compatible = "fixed-clock";
1003 #clock-cells = <0>;
1004 /* This value must be overridden by the board. */
1005 clock-frequency = <0>;
1006 };
1008 /* Special CPG clocks */
1009 cpg_clocks: cpg_clocks@e6150000 {
1010 compatible = "renesas,r8a7793-cpg-clocks",
1011 "renesas,rcar-gen2-cpg-clocks";
1012 reg = <0 0xe6150000 0 0x1000>;
1013 clocks = <&extal_clk &usb_extal_clk>;
1014 #clock-cells = <1>;
1015 clock-output-names = "main", "pll0", "pll1", "pll3",
1016 "lb", "qspi", "sdh", "sd0", "z",
1017 "rcan", "adsp";
1018 #power-domain-cells = <0>;
1019 };
1021 /* Variable factor clocks */
1022 sd2_clk: sd2@e6150078 {
1023 compatible = "renesas,r8a7793-div6-clock",
1024 "renesas,cpg-div6-clock";
1025 reg = <0 0xe6150078 0 4>;
1026 clocks = <&pll1_div2_clk>;
1027 #clock-cells = <0>;
1028 };
1029 sd3_clk: sd3@e615026c {
1030 compatible = "renesas,r8a7793-div6-clock",
1031 "renesas,cpg-div6-clock";
1032 reg = <0 0xe615026c 0 4>;
1033 clocks = <&pll1_div2_clk>;
1034 #clock-cells = <0>;
1035 };
1036 mmc0_clk: mmc0@e6150240 {
1037 compatible = "renesas,r8a7793-div6-clock",
1038 "renesas,cpg-div6-clock";
1039 reg = <0 0xe6150240 0 4>;
1040 clocks = <&pll1_div2_clk>;
1041 #clock-cells = <0>;
1042 };
1044 /* Fixed factor clocks */
1045 pll1_div2_clk: pll1_div2 {
1046 compatible = "fixed-factor-clock";
1047 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
1048 #clock-cells = <0>;
1049 clock-div = <2>;
1050 clock-mult = <1>;
1051 };
1052 zg_clk: zg {
1053 compatible = "fixed-factor-clock";
1054 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
1055 #clock-cells = <0>;
1056 clock-div = <5>;
1057 clock-mult = <1>;
1058 };
1059 zx_clk: zx {
1060 compatible = "fixed-factor-clock";
1061 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
1062 #clock-cells = <0>;
1063 clock-div = <3>;
1064 clock-mult = <1>;
1065 };
1066 zs_clk: zs {
1067 compatible = "fixed-factor-clock";
1068 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
1069 #clock-cells = <0>;
1070 clock-div = <6>;
1071 clock-mult = <1>;
1072 };
1073 hp_clk: hp {
1074 compatible = "fixed-factor-clock";
1075 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
1076 #clock-cells = <0>;
1077 clock-div = <12>;
1078 clock-mult = <1>;
1079 };
1080 p_clk: p {
1081 compatible = "fixed-factor-clock";
1082 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
1083 #clock-cells = <0>;
1084 clock-div = <24>;
1085 clock-mult = <1>;
1086 };
1087 m2_clk: m2 {
1088 compatible = "fixed-factor-clock";
1089 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
1090 #clock-cells = <0>;
1091 clock-div = <8>;
1092 clock-mult = <1>;
1093 };
1094 rclk_clk: rclk {
1095 compatible = "fixed-factor-clock";
1096 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
1097 #clock-cells = <0>;
1098 clock-div = <(48 * 1024)>;
1099 clock-mult = <1>;
1100 };
1101 mp_clk: mp {
1102 compatible = "fixed-factor-clock";
1103 clocks = <&pll1_div2_clk>;
1104 #clock-cells = <0>;
1105 clock-div = <15>;
1106 clock-mult = <1>;
1107 };
1108 cp_clk: cp {
1109 compatible = "fixed-factor-clock";
1110 clocks = <&extal_clk>;
1111 #clock-cells = <0>;
1112 clock-div = <2>;
1113 clock-mult = <1>;
1114 };
1116 /* Gate clocks */
1117 mstp1_clks: mstp1_clks@e6150134 {
1118 compatible = "renesas,r8a7793-mstp-clocks",
1119 "renesas,cpg-mstp-clocks";
1120 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
1121 clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1122 <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>,
1123 <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
1124 <&zs_clk>, <&zs_clk>, <&zs_clk>;
1125 #clock-cells = <1>;
1126 clock-indices = <
1127 R8A7793_CLK_VCP0 R8A7793_CLK_VPC0
1128 R8A7793_CLK_SSP1 R8A7793_CLK_TMU1
1129 R8A7793_CLK_3DG R8A7793_CLK_2DDMAC
1130 R8A7793_CLK_FDP1_1 R8A7793_CLK_FDP1_0
1131 R8A7793_CLK_TMU3 R8A7793_CLK_TMU2
1132 R8A7793_CLK_CMT0 R8A7793_CLK_TMU0
1133 R8A7793_CLK_VSP1_DU1 R8A7793_CLK_VSP1_DU0
1134 R8A7793_CLK_VSP1_S
1135 >;
1136 clock-output-names =
1137 "vcp0", "vpc0", "ssp_dev", "tmu1",
1138 "pvrsrvkm", "tddmac", "fdp1", "fdp0",
1139 "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
1140 "vsp1-du0", "vsps";
1141 };
1142 mstp2_clks: mstp2_clks@e6150138 {
1143 compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1144 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1145 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
1146 <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>;
1147 #clock-cells = <1>;
1148 clock-indices = <
1149 R8A7793_CLK_SCIFA2 R8A7793_CLK_SCIFA1 R8A7793_CLK_SCIFA0
1150 R8A7793_CLK_SCIFB0 R8A7793_CLK_SCIFB1 R8A7793_CLK_SCIFB2
1151 R8A7793_CLK_SYS_DMAC1 R8A7793_CLK_SYS_DMAC0
1152 >;
1153 clock-output-names =
1154 "scifa2", "scifa1", "scifa0", "scifb0",
1155 "scifb1", "scifb2", "sys-dmac1", "sys-dmac0";
1156 };
1157 mstp3_clks: mstp3_clks@e615013c {
1158 compatible = "renesas,r8a7793-mstp-clocks",
1159 "renesas,cpg-mstp-clocks";
1160 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1161 clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>,
1162 <&cpg_clocks R8A7793_CLK_SD0>, <&mmc0_clk>,
1163 <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>,
1164 <&rclk_clk>, <&hp_clk>, <&hp_clk>;
1165 #clock-cells = <1>;
1166 clock-indices = <
1167 R8A7793_CLK_TPU0 R8A7793_CLK_SDHI2
1168 R8A7793_CLK_SDHI1 R8A7793_CLK_SDHI0
1169 R8A7793_CLK_MMCIF0 R8A7793_CLK_IIC0
1170 R8A7793_CLK_PCIEC R8A7793_CLK_IIC1
1171 R8A7793_CLK_SSUSB R8A7793_CLK_CMT1
1172 R8A7793_CLK_USBDMAC0 R8A7793_CLK_USBDMAC1
1173 >;
1174 clock-output-names =
1175 "tpu0", "sdhi2", "sdhi1", "sdhi0", "mmcif0",
1176 "i2c7", "pciec", "i2c8", "ssusb", "cmt1",
1177 "usbdmac0", "usbdmac1";
1178 };
1179 mstp4_clks: mstp4_clks@e6150140 {
1180 compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1181 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1182 clocks = <&cp_clk>;
1183 #clock-cells = <1>;
1184 clock-indices = <R8A7793_CLK_IRQC>;
1185 clock-output-names = "irqc";
1186 };
1187 mstp5_clks: mstp5_clks@e6150144 {
1188 compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1189 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1190 clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>;
1191 #clock-cells = <1>;
1192 clock-indices = <R8A7793_CLK_AUDIO_DMAC0 R8A7793_CLK_AUDIO_DMAC1
1193 R8A7793_CLK_THERMAL>;
1194 clock-output-names = "audmac0", "audmac1", "thermal";
1195 };
1196 mstp7_clks: mstp7_clks@e615014c {
1197 compatible = "renesas,r8a7793-mstp-clocks",
1198 "renesas,cpg-mstp-clocks";
1199 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1200 clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&p_clk>,
1201 <&p_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1202 <&p_clk>, <&p_clk>, <&p_clk>, <&zx_clk>,
1203 <&zx_clk>, <&zx_clk>;
1204 #clock-cells = <1>;
1205 clock-indices = <
1206 R8A7793_CLK_EHCI R8A7793_CLK_HSUSB
1207 R8A7793_CLK_HSCIF2 R8A7793_CLK_SCIF5
1208 R8A7793_CLK_SCIF4 R8A7793_CLK_HSCIF1
1209 R8A7793_CLK_HSCIF0 R8A7793_CLK_SCIF3
1210 R8A7793_CLK_SCIF2 R8A7793_CLK_SCIF1
1211 R8A7793_CLK_SCIF0 R8A7793_CLK_DU1
1212 R8A7793_CLK_DU0 R8A7793_CLK_LVDS0
1213 >;
1214 clock-output-names =
1215 "ehci", "hsusb", "hscif2", "scif5", "scif4",
1216 "hscif1", "hscif0", "scif3", "scif2",
1217 "scif1", "scif0", "du1", "du0", "lvds0";
1218 };
1219 mstp8_clks: mstp8_clks@e6150990 {
1220 compatible = "renesas,r8a7793-mstp-clocks",
1221 "renesas,cpg-mstp-clocks";
1222 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1223 clocks = <&zx_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
1224 <&p_clk>, <&zs_clk>, <&zs_clk>;
1225 #clock-cells = <1>;
1226 clock-indices = <
1227 R8A7793_CLK_IPMMU_SGX R8A7793_CLK_VIN2
1228 R8A7793_CLK_VIN1 R8A7793_CLK_VIN0
1229 R8A7793_CLK_ETHER R8A7793_CLK_SATA1
1230 R8A7793_CLK_SATA0
1231 >;
1232 clock-output-names =
1233 "ipmmu_sgx", "vin2", "vin1", "vin0", "ether",
1234 "sata1", "sata0";
1235 };
1236 mstp9_clks: mstp9_clks@e6150994 {
1237 compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1238 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1239 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1240 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1241 <&p_clk>, <&p_clk>,
1242 <&cpg_clocks R8A7793_CLK_QSPI>, <&hp_clk>,
1243 <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
1244 <&hp_clk>, <&hp_clk>;
1245 #clock-cells = <1>;
1246 clock-indices = <
1247 R8A7793_CLK_GPIO7 R8A7793_CLK_GPIO6
1248 R8A7793_CLK_GPIO5 R8A7793_CLK_GPIO4
1249 R8A7793_CLK_GPIO3 R8A7793_CLK_GPIO2
1250 R8A7793_CLK_GPIO1 R8A7793_CLK_GPIO0
1251 R8A7793_CLK_QSPI_MOD R8A7793_CLK_RCAN1
1252 R8A7793_CLK_RCAN0 R8A7793_CLK_I2C5
1253 R8A7793_CLK_IICDVFS R8A7793_CLK_I2C4
1254 R8A7793_CLK_I2C3 R8A7793_CLK_I2C2
1255 R8A7793_CLK_I2C1 R8A7793_CLK_I2C0
1256 >;
1257 clock-output-names =
1258 "gpio7", "gpio6", "gpio5", "gpio4",
1259 "gpio3", "gpio2", "gpio1", "gpio0",
1260 "rcan1", "rcan0", "qspi_mod", "i2c5",
1261 "i2c6", "i2c4", "i2c3", "i2c2", "i2c1",
1262 "i2c0";
1263 };
1264 mstp10_clks: mstp10_clks@e6150998 {
1265 compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1266 reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1267 clocks = <&p_clk>,
1268 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1269 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1270 <&p_clk>,
1271 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1272 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1273 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1274 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1275 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1276 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1277 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>;
1279 #clock-cells = <1>;
1280 clock-indices = <
1281 R8A7793_CLK_SSI_ALL
1282 R8A7793_CLK_SSI9 R8A7793_CLK_SSI8 R8A7793_CLK_SSI7 R8A7793_CLK_SSI6 R8A7793_CLK_SSI5
1283 R8A7793_CLK_SSI4 R8A7793_CLK_SSI3 R8A7793_CLK_SSI2 R8A7793_CLK_SSI1 R8A7793_CLK_SSI0
1284 R8A7793_CLK_SCU_ALL
1285 R8A7793_CLK_SCU_DVC1 R8A7793_CLK_SCU_DVC0
1286 R8A7793_CLK_SCU_CTU1_MIX1 R8A7793_CLK_SCU_CTU0_MIX0
1287 R8A7793_CLK_SCU_SRC9 R8A7793_CLK_SCU_SRC8 R8A7793_CLK_SCU_SRC7 R8A7793_CLK_SCU_SRC6 R8A7793_CLK_SCU_SRC5
1288 R8A7793_CLK_SCU_SRC4 R8A7793_CLK_SCU_SRC3 R8A7793_CLK_SCU_SRC2 R8A7793_CLK_SCU_SRC1 R8A7793_CLK_SCU_SRC0
1289 >;
1290 clock-output-names =
1291 "ssi-all",
1292 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1293 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1294 "scu-all",
1295 "scu-dvc1", "scu-dvc0",
1296 "scu-ctu1-mix1", "scu-ctu0-mix0",
1297 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1298 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1299 };
1300 mstp11_clks: mstp11_clks@e615099c {
1301 compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1302 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
1303 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
1304 #clock-cells = <1>;
1305 clock-indices = <
1306 R8A7793_CLK_SCIFA3 R8A7793_CLK_SCIFA4 R8A7793_CLK_SCIFA5
1307 >;
1308 clock-output-names = "scifa3", "scifa4", "scifa5";
1309 };
1310 };
1312 rst: reset-controller@e6160000 {
1313 compatible = "renesas,r8a7793-rst";
1314 reg = <0 0xe6160000 0 0x0100>;
1315 };
1317 prr: chipid@ff000044 {
1318 compatible = "renesas,prr";
1319 reg = <0 0xff000044 0 4>;
1320 };
1322 sysc: system-controller@e6180000 {
1323 compatible = "renesas,r8a7793-sysc";
1324 reg = <0 0xe6180000 0 0x0200>;
1325 #power-domain-cells = <1>;
1326 };
1328 ipmmu_sy0: mmu@e6280000 {
1329 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1330 reg = <0 0xe6280000 0 0x1000>;
1331 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
1332 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
1333 #iommu-cells = <1>;
1334 status = "disabled";
1335 };
1337 ipmmu_sy1: mmu@e6290000 {
1338 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1339 reg = <0 0xe6290000 0 0x1000>;
1340 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1341 #iommu-cells = <1>;
1342 status = "disabled";
1343 };
1345 ipmmu_ds: mmu@e6740000 {
1346 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1347 reg = <0 0xe6740000 0 0x1000>;
1348 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1349 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1350 #iommu-cells = <1>;
1351 status = "disabled";
1352 };
1354 ipmmu_mp: mmu@ec680000 {
1355 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1356 reg = <0 0xec680000 0 0x1000>;
1357 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1358 #iommu-cells = <1>;
1359 status = "disabled";
1360 };
1362 ipmmu_mx: mmu@fe951000 {
1363 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1364 reg = <0 0xfe951000 0 0x1000>;
1365 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
1366 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1367 #iommu-cells = <1>;
1368 status = "disabled";
1369 };
1371 ipmmu_rt: mmu@ffc80000 {
1372 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1373 reg = <0 0xffc80000 0 0x1000>;
1374 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1375 #iommu-cells = <1>;
1376 status = "disabled";
1377 };
1379 ipmmu_gp: mmu@e62a0000 {
1380 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1381 reg = <0 0xe62a0000 0 0x1000>;
1382 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1383 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
1384 #iommu-cells = <1>;
1385 status = "disabled";
1386 };
1388 rcar_sound: sound@ec500000 {
1389 /*
1390 * #sound-dai-cells is required
1391 *
1392 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1393 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1394 */
1395 compatible = "renesas,rcar_sound-r8a7793", "renesas,rcar_sound-gen2";
1396 reg = <0 0xec500000 0 0x1000>, /* SCU */
1397 <0 0xec5a0000 0 0x100>, /* ADG */
1398 <0 0xec540000 0 0x1000>, /* SSIU */
1399 <0 0xec541000 0 0x280>, /* SSI */
1400 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
1401 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1403 clocks = <&mstp10_clks R8A7793_CLK_SSI_ALL>,
1404 <&mstp10_clks R8A7793_CLK_SSI9>, <&mstp10_clks R8A7793_CLK_SSI8>,
1405 <&mstp10_clks R8A7793_CLK_SSI7>, <&mstp10_clks R8A7793_CLK_SSI6>,
1406 <&mstp10_clks R8A7793_CLK_SSI5>, <&mstp10_clks R8A7793_CLK_SSI4>,
1407 <&mstp10_clks R8A7793_CLK_SSI3>, <&mstp10_clks R8A7793_CLK_SSI2>,
1408 <&mstp10_clks R8A7793_CLK_SSI1>, <&mstp10_clks R8A7793_CLK_SSI0>,
1409 <&mstp10_clks R8A7793_CLK_SCU_SRC9>, <&mstp10_clks R8A7793_CLK_SCU_SRC8>,
1410 <&mstp10_clks R8A7793_CLK_SCU_SRC7>, <&mstp10_clks R8A7793_CLK_SCU_SRC6>,
1411 <&mstp10_clks R8A7793_CLK_SCU_SRC5>, <&mstp10_clks R8A7793_CLK_SCU_SRC4>,
1412 <&mstp10_clks R8A7793_CLK_SCU_SRC3>, <&mstp10_clks R8A7793_CLK_SCU_SRC2>,
1413 <&mstp10_clks R8A7793_CLK_SCU_SRC1>, <&mstp10_clks R8A7793_CLK_SCU_SRC0>,
1414 <&mstp10_clks R8A7793_CLK_SCU_DVC0>, <&mstp10_clks R8A7793_CLK_SCU_DVC1>,
1415 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1416 clock-names = "ssi-all",
1417 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1418 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1419 "src.9", "src.8", "src.7", "src.6", "src.5",
1420 "src.4", "src.3", "src.2", "src.1", "src.0",
1421 "dvc.0", "dvc.1",
1422 "clk_a", "clk_b", "clk_c", "clk_i";
1423 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
1425 status = "disabled";
1427 rcar_sound,dvc {
1428 dvc0: dvc-0 {
1429 dmas = <&audma0 0xbc>;
1430 dma-names = "tx";
1431 };
1432 dvc1: dvc-1 {
1433 dmas = <&audma0 0xbe>;
1434 dma-names = "tx";
1435 };
1436 };
1438 rcar_sound,src {
1439 src0: src-0 {
1440 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1441 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1442 dma-names = "rx", "tx";
1443 };
1444 src1: src-1 {
1445 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1446 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1447 dma-names = "rx", "tx";
1448 };
1449 src2: src-2 {
1450 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1451 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1452 dma-names = "rx", "tx";
1453 };
1454 src3: src-3 {
1455 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1456 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1457 dma-names = "rx", "tx";
1458 };
1459 src4: src-4 {
1460 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1461 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1462 dma-names = "rx", "tx";
1463 };
1464 src5: src-5 {
1465 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1466 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1467 dma-names = "rx", "tx";
1468 };
1469 src6: src-6 {
1470 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1471 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1472 dma-names = "rx", "tx";
1473 };
1474 src7: src-7 {
1475 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1476 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1477 dma-names = "rx", "tx";
1478 };
1479 src8: src-8 {
1480 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1481 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1482 dma-names = "rx", "tx";
1483 };
1484 src9: src-9 {
1485 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1486 dmas = <&audma0 0x97>, <&audma1 0xba>;
1487 dma-names = "rx", "tx";
1488 };
1489 };
1491 rcar_sound,ssi {
1492 ssi0: ssi-0 {
1493 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1494 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
1495 dma-names = "rx", "tx", "rxu", "txu";
1496 };
1497 ssi1: ssi-1 {
1498 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1499 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
1500 dma-names = "rx", "tx", "rxu", "txu";
1501 };
1502 ssi2: ssi-2 {
1503 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1504 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
1505 dma-names = "rx", "tx", "rxu", "txu";
1506 };
1507 ssi3: ssi-3 {
1508 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1509 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
1510 dma-names = "rx", "tx", "rxu", "txu";
1511 };
1512 ssi4: ssi-4 {
1513 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1514 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
1515 dma-names = "rx", "tx", "rxu", "txu";
1516 };
1517 ssi5: ssi-5 {
1518 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1519 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
1520 dma-names = "rx", "tx", "rxu", "txu";
1521 };
1522 ssi6: ssi-6 {
1523 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1524 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
1525 dma-names = "rx", "tx", "rxu", "txu";
1526 };
1527 ssi7: ssi-7 {
1528 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1529 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
1530 dma-names = "rx", "tx", "rxu", "txu";
1531 };
1532 ssi8: ssi-8 {
1533 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1534 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
1535 dma-names = "rx", "tx", "rxu", "txu";
1536 };
1537 ssi9: ssi-9 {
1538 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1539 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
1540 dma-names = "rx", "tx", "rxu", "txu";
1541 };
1542 };
1543 };
1544 };