arch/arm/boot/dts/rk3288.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/clock/rk3288-cru.h>
  46 #include <dt-bindings/thermal/thermal.h>
  47 #include <dt-bindings/power/rk3288-power.h>
  48 #include <dt-bindings/soc/rockchip,boot-mode.h>
  49
  50 / {
  51         #address-cells = <1>;
  52         #size-cells = <1>;
  53
  54         compatible = "rockchip,rk3288";
  55
  56         interrupt-parent = <&gic>;
  57
  58         aliases {
  59                 ethernet0 = &gmac;
  60                 i2c0 = &i2c0;
  61                 i2c1 = &i2c1;
  62                 i2c2 = &i2c2;
  63                 i2c3 = &i2c3;
  64                 i2c4 = &i2c4;
  65                 i2c5 = &i2c5;
  66                 mshc0 = &emmc;
  67                 mshc1 = &sdmmc;
  68                 mshc2 = &sdio0;
  69                 mshc3 = &sdio1;
  70                 serial0 = &uart0;
  71                 serial1 = &uart1;
  72                 serial2 = &uart2;
  73                 serial3 = &uart3;
  74                 serial4 = &uart4;
  75                 spi0 = &spi0;
  76                 spi1 = &spi1;
  77                 spi2 = &spi2;
  78         };
  79
  80         arm-pmu {
  81                 compatible = "arm,cortex-a12-pmu";
  82                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
  83                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
  84                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  85                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  86                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  87         };
  88
  89         cpus {
  90                 #address-cells = <1>;
  91                 #size-cells = <0>;
  92                 enable-method = "rockchip,rk3066-smp";
  93                 rockchip,pmu = <&pmu>;
  94
  95                 cpu0: cpu@500 {
  96                         device_type = "cpu";
  97                         compatible = "arm,cortex-a12";
  98                         reg = <0x500>;
  99                         resets = <&cru SRST_CORE0>;
 100                         operating-points = <
 101                                 /* KHz    uV */
 102                                 1608000 1350000
 103                                 1512000 1300000
 104                                 1416000 1200000
 105                                 1200000 1100000
 106                                 1008000 1050000
 107                                  816000 1000000
 108                                  696000  950000
 109                                  600000  900000
 110                                  408000  900000
 111                                  312000  900000
 112                                  216000  900000
 113                                  126000  900000
 114                         >;
 115                         #cooling-cells = <2>; /* min followed by max */
 116                         clock-latency = <40000>;
 117                         clocks = <&cru ARMCLK>;
 118                 };
 119                 cpu1: cpu@501 {
 120                         device_type = "cpu";
 121                         compatible = "arm,cortex-a12";
 122                         reg = <0x501>;
 123                         resets = <&cru SRST_CORE1>;
 124                 };
 125                 cpu2: cpu@502 {
 126                         device_type = "cpu";
 127                         compatible = "arm,cortex-a12";
 128                         reg = <0x502>;
 129                         resets = <&cru SRST_CORE2>;
 130                 };
 131                 cpu3: cpu@503 {
 132                         device_type = "cpu";
 133                         compatible = "arm,cortex-a12";
 134                         reg = <0x503>;
 135                         resets = <&cru SRST_CORE3>;
 136                 };
 137         };
 138
 139         amba {
 140                 compatible = "simple-bus";
 141                 #address-cells = <1>;
 142                 #size-cells = <1>;
 143                 ranges;
 144
 145                 dmac_peri: dma-controller@ff250000 {
 146                         compatible = "arm,pl330", "arm,primecell";
 147                         reg = <0xff250000 0x4000>;
 148                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 149                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 150                         #dma-cells = <1>;
 151                         arm,pl330-broken-no-flushp;
 152                         clocks = <&cru ACLK_DMAC2>;
 153                         clock-names = "apb_pclk";
 154                 };
 155
 156                 dmac_bus_ns: dma-controller@ff600000 {
 157                         compatible = "arm,pl330", "arm,primecell";
 158                         reg = <0xff600000 0x4000>;
 159                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 160                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 161                         #dma-cells = <1>;
 162                         arm,pl330-broken-no-flushp;
 163                         clocks = <&cru ACLK_DMAC1>;
 164                         clock-names = "apb_pclk";
 165                         status = "disabled";
 166                 };
 167
 168                 dmac_bus_s: dma-controller@ffb20000 {
 169                         compatible = "arm,pl330", "arm,primecell";
 170                         reg = <0xffb20000 0x4000>;
 171                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 172                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 173                         #dma-cells = <1>;
 174                         arm,pl330-broken-no-flushp;
 175                         clocks = <&cru ACLK_DMAC1>;
 176                         clock-names = "apb_pclk";
 177                 };
 178         };
 179
 180         reserved-memory {
 181                 #address-cells = <1>;
 182                 #size-cells = <1>;
 183                 ranges;
 184
 185                 /*
 186                  * The rk3288 cannot use the memory area above 0xfe000000
 187                  * for dma operations for some reason. While there is
 188                  * probably a better solution available somewhere, we
 189                  * haven't found it yet and while devices with 2GB of ram
 190                  * are not affected, this issue prevents 4GB from booting.
 191                  * So to make these devices at least bootable, block
 192                  * this area for the time being until the real solution
 193                  * is found.
 194                  */
 195                 dma-unusable@fe000000 {
 196                         reg = <0xfe000000 0x1000000>;
 197                 };
 198         };
 199
 200         xin24m: oscillator {
 201                 compatible = "fixed-clock";
 202                 clock-frequency = <24000000>;
 203                 clock-output-names = "xin24m";
 204                 #clock-cells = <0>;
 205         };
 206
 207         timer {
 208                 compatible = "arm,armv7-timer";
 209                 arm,cpu-registers-not-fw-configured;
 210                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 211                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 212                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 213                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 214                 clock-frequency = <24000000>;
 215         };
 216
 217         timer: timer@ff810000 {
 218                 compatible = "rockchip,rk3288-timer";
 219                 reg = <0xff810000 0x20>;
 220                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 221                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 222                 clock-names = "timer", "pclk";
 223         };
 224
 225         display-subsystem {
 226                 compatible = "rockchip,display-subsystem";
 227                 ports = <&vopl_out>, <&vopb_out>;
 228         };
 229
 230         sdmmc: dwmmc@ff0c0000 {
 231                 compatible = "rockchip,rk3288-dw-mshc";
 232                 max-frequency = <150000000>;
 233                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 234                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 235                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 236                 fifo-depth = <0x100>;
 237                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 238                 reg = <0xff0c0000 0x4000>;
 239                 status = "disabled";
 240         };
 241
 242         sdio0: dwmmc@ff0d0000 {
 243                 compatible = "rockchip,rk3288-dw-mshc";
 244                 max-frequency = <150000000>;
 245                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 246                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 247                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 248                 fifo-depth = <0x100>;
 249                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 250                 reg = <0xff0d0000 0x4000>;
 251                 status = "disabled";
 252         };
 253
 254         sdio1: dwmmc@ff0e0000 {
 255                 compatible = "rockchip,rk3288-dw-mshc";
 256                 max-frequency = <150000000>;
 257                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
 258                          <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
 259                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 260                 fifo-depth = <0x100>;
 261                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 262                 reg = <0xff0e0000 0x4000>;
 263                 status = "disabled";
 264         };
 265
 266         emmc: dwmmc@ff0f0000 {
 267                 compatible = "rockchip,rk3288-dw-mshc";
 268                 max-frequency = <150000000>;
 269                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 270                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 271                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 272                 fifo-depth = <0x100>;
 273                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 274                 reg = <0xff0f0000 0x4000>;
 275                 status = "disabled";
 276         };
 277
 278         saradc: saradc@ff100000 {
 279                 compatible = "rockchip,saradc";
 280                 reg = <0xff100000 0x100>;
 281                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 282                 #io-channel-cells = <1>;
 283                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 284                 clock-names = "saradc", "apb_pclk";
 285                 resets = <&cru SRST_SARADC>;
 286                 reset-names = "saradc-apb";
 287                 status = "disabled";
 288         };
 289
 290         spi0: spi@ff110000 {
 291                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 292                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 293                 clock-names = "spiclk", "apb_pclk";
 294                 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
 295                 dma-names = "tx", "rx";
 296                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 297                 pinctrl-names = "default";
 298                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 299                 reg = <0xff110000 0x1000>;
 300                 #address-cells = <1>;
 301                 #size-cells = <0>;
 302                 status = "disabled";
 303         };
 304
 305         spi1: spi@ff120000 {
 306                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 307                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 308                 clock-names = "spiclk", "apb_pclk";
 309                 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
 310                 dma-names = "tx", "rx";
 311                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 312                 pinctrl-names = "default";
 313                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 314                 reg = <0xff120000 0x1000>;
 315                 #address-cells = <1>;
 316                 #size-cells = <0>;
 317                 status = "disabled";
 318         };
 319
 320         spi2: spi@ff130000 {
 321                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 322                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 323                 clock-names = "spiclk", "apb_pclk";
 324                 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
 325                 dma-names = "tx", "rx";
 326                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 327                 pinctrl-names = "default";
 328                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 329                 reg = <0xff130000 0x1000>;
 330                 #address-cells = <1>;
 331                 #size-cells = <0>;
 332                 status = "disabled";
 333         };
 334
 335         i2c1: i2c@ff140000 {
 336                 compatible = "rockchip,rk3288-i2c";
 337                 reg = <0xff140000 0x1000>;
 338                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 339                 #address-cells = <1>;
 340                 #size-cells = <0>;
 341                 clock-names = "i2c";
 342                 clocks = <&cru PCLK_I2C1>;
 343                 pinctrl-names = "default";
 344                 pinctrl-0 = <&i2c1_xfer>;
 345                 status = "disabled";
 346         };
 347
 348         i2c3: i2c@ff150000 {
 349                 compatible = "rockchip,rk3288-i2c";
 350                 reg = <0xff150000 0x1000>;
 351                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 352                 #address-cells = <1>;
 353                 #size-cells = <0>;
 354                 clock-names = "i2c";
 355                 clocks = <&cru PCLK_I2C3>;
 356                 pinctrl-names = "default";
 357                 pinctrl-0 = <&i2c3_xfer>;
 358                 status = "disabled";
 359         };
 360
 361         i2c4: i2c@ff160000 {
 362                 compatible = "rockchip,rk3288-i2c";
 363                 reg = <0xff160000 0x1000>;
 364                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 365                 #address-cells = <1>;
 366                 #size-cells = <0>;
 367                 clock-names = "i2c";
 368                 clocks = <&cru PCLK_I2C4>;
 369                 pinctrl-names = "default";
 370                 pinctrl-0 = <&i2c4_xfer>;
 371                 status = "disabled";
 372         };
 373
 374         i2c5: i2c@ff170000 {
 375                 compatible = "rockchip,rk3288-i2c";
 376                 reg = <0xff170000 0x1000>;
 377                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 378                 #address-cells = <1>;
 379                 #size-cells = <0>;
 380                 clock-names = "i2c";
 381                 clocks = <&cru PCLK_I2C5>;
 382                 pinctrl-names = "default";
 383                 pinctrl-0 = <&i2c5_xfer>;
 384                 status = "disabled";
 385         };
 386
 387         uart0: serial@ff180000 {
 388                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 389                 reg = <0xff180000 0x100>;
 390                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 391                 reg-shift = <2>;
 392                 reg-io-width = <4>;
 393                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 394                 clock-names = "baudclk", "apb_pclk";
 395                 pinctrl-names = "default";
 396                 pinctrl-0 = <&uart0_xfer>;
 397                 status = "disabled";
 398         };
 399
 400         uart1: serial@ff190000 {
 401                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 402                 reg = <0xff190000 0x100>;
 403                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 404                 reg-shift = <2>;
 405                 reg-io-width = <4>;
 406                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 407                 clock-names = "baudclk", "apb_pclk";
 408                 pinctrl-names = "default";
 409                 pinctrl-0 = <&uart1_xfer>;
 410                 status = "disabled";
 411         };
 412
 413         uart2: serial@ff690000 {
 414                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 415                 reg = <0xff690000 0x100>;
 416                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 417                 reg-shift = <2>;
 418                 reg-io-width = <4>;
 419                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 420                 clock-names = "baudclk", "apb_pclk";
 421                 pinctrl-names = "default";
 422                 pinctrl-0 = <&uart2_xfer>;
 423                 status = "disabled";
 424         };
 425
 426         uart3: serial@ff1b0000 {
 427                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 428                 reg = <0xff1b0000 0x100>;
 429                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 430                 reg-shift = <2>;
 431                 reg-io-width = <4>;
 432                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 433                 clock-names = "baudclk", "apb_pclk";
 434                 pinctrl-names = "default";
 435                 pinctrl-0 = <&uart3_xfer>;
 436                 status = "disabled";
 437         };
 438
 439         uart4: serial@ff1c0000 {
 440                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 441                 reg = <0xff1c0000 0x100>;
 442                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 443                 reg-shift = <2>;
 444                 reg-io-width = <4>;
 445                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 446                 clock-names = "baudclk", "apb_pclk";
 447                 pinctrl-names = "default";
 448                 pinctrl-0 = <&uart4_xfer>;
 449                 status = "disabled";
 450         };
 451
 452         thermal-zones {
 453                 reserve_thermal: reserve_thermal {
 454                         polling-delay-passive = <1000>; /* milliseconds */
 455                         polling-delay = <5000>; /* milliseconds */
 456
 457                         thermal-sensors = <&tsadc 0>;
 458                 };
 459
 460                 cpu_thermal: cpu_thermal {
 461                         polling-delay-passive = <100>; /* milliseconds */
 462                         polling-delay = <5000>; /* milliseconds */
 463
 464                         thermal-sensors = <&tsadc 1>;
 465
 466                         trips {
 467                                 cpu_alert0: cpu_alert0 {
 468                                         temperature = <70000>; /* millicelsius */
 469                                         hysteresis = <2000>; /* millicelsius */
 470                                         type = "passive";
 471                                 };
 472                                 cpu_alert1: cpu_alert1 {
 473                                         temperature = <75000>; /* millicelsius */
 474                                         hysteresis = <2000>; /* millicelsius */
 475                                         type = "passive";
 476                                 };
 477                                 cpu_crit: cpu_crit {
 478                                         temperature = <90000>; /* millicelsius */
 479                                         hysteresis = <2000>; /* millicelsius */
 480                                         type = "critical";
 481                                 };
 482                         };
 483
 484                         cooling-maps {
 485                                 map0 {
 486                                         trip = <&cpu_alert0>;
 487                                         cooling-device =
 488                                                 <&cpu0 THERMAL_NO_LIMIT 6>;
 489                                 };
 490                                 map1 {
 491                                         trip = <&cpu_alert1>;
 492                                         cooling-device =
 493                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 494                                 };
 495                         };
 496                 };
 497
 498                 gpu_thermal: gpu_thermal {
 499                         polling-delay-passive = <100>; /* milliseconds */
 500                         polling-delay = <5000>; /* milliseconds */
 501
 502                         thermal-sensors = <&tsadc 2>;
 503
 504                         trips {
 505                                 gpu_alert0: gpu_alert0 {
 506                                         temperature = <70000>; /* millicelsius */
 507                                         hysteresis = <2000>; /* millicelsius */
 508                                         type = "passive";
 509                                 };
 510                                 gpu_crit: gpu_crit {
 511                                         temperature = <90000>; /* millicelsius */
 512                                         hysteresis = <2000>; /* millicelsius */
 513                                         type = "critical";
 514                                 };
 515                         };
 516
 517                         cooling-maps {
 518                                 map0 {
 519                                         trip = <&gpu_alert0>;
 520                                         cooling-device =
 521                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 522                                 };
 523                         };
 524                 };
 525         };
 526
 527         tsadc: tsadc@ff280000 {
 528                 compatible = "rockchip,rk3288-tsadc";
 529                 reg = <0xff280000 0x100>;
 530                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 531                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 532                 clock-names = "tsadc", "apb_pclk";
 533                 resets = <&cru SRST_TSADC>;
 534                 reset-names = "tsadc-apb";
 535                 pinctrl-names = "init", "default", "sleep";
 536                 pinctrl-0 = <&otp_gpio>;
 537                 pinctrl-1 = <&otp_out>;
 538                 pinctrl-2 = <&otp_gpio>;
 539                 #thermal-sensor-cells = <1>;
 540                 rockchip,hw-tshut-temp = <95000>;
 541                 status = "disabled";
 542         };
 543
 544         gmac: ethernet@ff290000 {
 545                 compatible = "rockchip,rk3288-gmac";
 546                 reg = <0xff290000 0x10000>;
 547                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
 548                                 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 549                 interrupt-names = "macirq", "eth_wake_irq";
 550                 rockchip,grf = <&grf>;
 551                 clocks = <&cru SCLK_MAC>,
 552                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 553                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 554                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 555                 clock-names = "stmmaceth",
 556                         "mac_clk_rx", "mac_clk_tx",
 557                         "clk_mac_ref", "clk_mac_refout",
 558                         "aclk_mac", "pclk_mac";
 559                 resets = <&cru SRST_MAC>;
 560                 reset-names = "stmmaceth";
 561                 status = "disabled";
 562         };
 563
 564         usb_host0_ehci: usb@ff500000 {
 565                 compatible = "generic-ehci";
 566                 reg = <0xff500000 0x100>;
 567                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 568                 clocks = <&cru HCLK_USBHOST0>;
 569                 clock-names = "usbhost";
 570                 phys = <&usbphy1>;
 571                 phy-names = "usb";
 572                 status = "disabled";
 573         };
 574
 575         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 576
 577         usb_host1: usb@ff540000 {
 578                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 579                                 "snps,dwc2";
 580                 reg = <0xff540000 0x40000>;
 581                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 582                 clocks = <&cru HCLK_USBHOST1>;
 583                 clock-names = "otg";
 584                 dr_mode = "host";
 585                 phys = <&usbphy2>;
 586                 phy-names = "usb2-phy";
 587                 status = "disabled";
 588         };
 589
 590         usb_otg: usb@ff580000 {
 591                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 592                                 "snps,dwc2";
 593                 reg = <0xff580000 0x40000>;
 594                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 595                 clocks = <&cru HCLK_OTG0>;
 596                 clock-names = "otg";
 597                 dr_mode = "otg";
 598                 g-np-tx-fifo-size = <16>;
 599                 g-rx-fifo-size = <275>;
 600                 g-tx-fifo-size = <256 128 128 64 64 32>;
 601                 phys = <&usbphy0>;
 602                 phy-names = "usb2-phy";
 603                 status = "disabled";
 604         };
 605
 606         usb_hsic: usb@ff5c0000 {
 607                 compatible = "generic-ehci";
 608                 reg = <0xff5c0000 0x100>;
 609                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 610                 clocks = <&cru HCLK_HSIC>;
 611                 clock-names = "usbhost";
 612                 status = "disabled";
 613         };
 614
 615         i2c0: i2c@ff650000 {
 616                 compatible = "rockchip,rk3288-i2c";
 617                 reg = <0xff650000 0x1000>;
 618                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 619                 #address-cells = <1>;
 620                 #size-cells = <0>;
 621                 clock-names = "i2c";
 622                 clocks = <&cru PCLK_I2C0>;
 623                 pinctrl-names = "default";
 624                 pinctrl-0 = <&i2c0_xfer>;
 625                 status = "disabled";
 626         };
 627
 628         i2c2: i2c@ff660000 {
 629                 compatible = "rockchip,rk3288-i2c";
 630                 reg = <0xff660000 0x1000>;
 631                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 632                 #address-cells = <1>;
 633                 #size-cells = <0>;
 634                 clock-names = "i2c";
 635                 clocks = <&cru PCLK_I2C2>;
 636                 pinctrl-names = "default";
 637                 pinctrl-0 = <&i2c2_xfer>;
 638                 status = "disabled";
 639         };
 640
 641         pwm0: pwm@ff680000 {
 642                 compatible = "rockchip,rk3288-pwm";
 643                 reg = <0xff680000 0x10>;
 644                 #pwm-cells = <3>;
 645                 pinctrl-names = "default";
 646                 pinctrl-0 = <&pwm0_pin>;
 647                 clocks = <&cru PCLK_PWM>;
 648                 clock-names = "pwm";
 649                 status = "disabled";
 650         };
 651
 652         pwm1: pwm@ff680010 {
 653                 compatible = "rockchip,rk3288-pwm";
 654                 reg = <0xff680010 0x10>;
 655                 #pwm-cells = <3>;
 656                 pinctrl-names = "default";
 657                 pinctrl-0 = <&pwm1_pin>;
 658                 clocks = <&cru PCLK_PWM>;
 659                 clock-names = "pwm";
 660                 status = "disabled";
 661         };
 662
 663         pwm2: pwm@ff680020 {
 664                 compatible = "rockchip,rk3288-pwm";
 665                 reg = <0xff680020 0x10>;
 666                 #pwm-cells = <3>;
 667                 pinctrl-names = "default";
 668                 pinctrl-0 = <&pwm2_pin>;
 669                 clocks = <&cru PCLK_PWM>;
 670                 clock-names = "pwm";
 671                 status = "disabled";
 672         };
 673
 674         pwm3: pwm@ff680030 {
 675                 compatible = "rockchip,rk3288-pwm";
 676                 reg = <0xff680030 0x10>;
 677                 #pwm-cells = <2>;
 678                 pinctrl-names = "default";
 679                 pinctrl-0 = <&pwm3_pin>;
 680                 clocks = <&cru PCLK_PWM>;
 681                 clock-names = "pwm";
 682                 status = "disabled";
 683         };
 684
 685         bus_intmem@ff700000 {
 686                 compatible = "mmio-sram";
 687                 reg = <0xff700000 0x18000>;
 688                 #address-cells = <1>;
 689                 #size-cells = <1>;
 690                 ranges = <0 0xff700000 0x18000>;
 691                 smp-sram@0 {
 692                         compatible = "rockchip,rk3066-smp-sram";
 693                         reg = <0x00 0x10>;
 694                 };
 695         };
 696
 697         sram@ff720000 {
 698                 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
 699                 reg = <0xff720000 0x1000>;
 700         };
 701
 702         pmu: power-management@ff730000 {
 703                 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
 704                 reg = <0xff730000 0x100>;
 705
 706                 power: power-controller {
 707                         compatible = "rockchip,rk3288-power-controller";
 708                         #power-domain-cells = <1>;
 709                         #address-cells = <1>;
 710                         #size-cells = <0>;
 711
 712                         assigned-clocks = <&cru SCLK_EDP_24M>;
 713                         assigned-clock-parents = <&xin24m>;
 714
 715                         /*
 716                          * Note: Although SCLK_* are the working clocks
 717                          * of device without including on the NOC, needed for
 718                          * synchronous reset.
 719                          *
 720                          * The clocks on the which NOC:
 721                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 722                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 723                          * ACLK_RGA is on ACLK_RGA_NIU.
 724                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 725                          *
 726                          * Which clock are device clocks:
 727                          *      clocks          devices
 728                          *      *_IEP           IEP:Image Enhancement Processor
 729                          *      *_ISP           ISP:Image Signal Processing
 730                          *      *_VIP           VIP:Video Input Processor
 731                          *      *_VOP*          VOP:Visual Output Processor
 732                          *      *_RGA           RGA
 733                          *      *_EDP*          EDP
 734                          *      *_LVDS_*        LVDS
 735                          *      *_HDMI          HDMI
 736                          *      *_MIPI_*        MIPI
 737                          */
 738                         pd_vio@RK3288_PD_VIO {
 739                                 reg = <RK3288_PD_VIO>;
 740                                 clocks = <&cru ACLK_IEP>,
 741                                          <&cru ACLK_ISP>,
 742                                          <&cru ACLK_RGA>,
 743                                          <&cru ACLK_VIP>,
 744                                          <&cru ACLK_VOP0>,
 745                                          <&cru ACLK_VOP1>,
 746                                          <&cru DCLK_VOP0>,
 747                                          <&cru DCLK_VOP1>,
 748                                          <&cru HCLK_IEP>,
 749                                          <&cru HCLK_ISP>,
 750                                          <&cru HCLK_RGA>,
 751                                          <&cru HCLK_VIP>,
 752                                          <&cru HCLK_VOP0>,
 753                                          <&cru HCLK_VOP1>,
 754                                          <&cru PCLK_EDP_CTRL>,
 755                                          <&cru PCLK_HDMI_CTRL>,
 756                                          <&cru PCLK_LVDS_PHY>,
 757                                          <&cru PCLK_MIPI_CSI>,
 758                                          <&cru PCLK_MIPI_DSI0>,
 759                                          <&cru PCLK_MIPI_DSI1>,
 760                                          <&cru SCLK_EDP_24M>,
 761                                          <&cru SCLK_EDP>,
 762                                          <&cru SCLK_ISP_JPE>,
 763                                          <&cru SCLK_ISP>,
 764                                          <&cru SCLK_RGA>;
 765                                 pm_qos = <&qos_vio0_iep>,
 766                                          <&qos_vio1_vop>,
 767                                          <&qos_vio1_isp_w0>,
 768                                          <&qos_vio1_isp_w1>,
 769                                          <&qos_vio0_vop>,
 770                                          <&qos_vio0_vip>,
 771                                          <&qos_vio2_rga_r>,
 772                                          <&qos_vio2_rga_w>,
 773                                          <&qos_vio1_isp_r>;
 774                         };
 775
 776                         /*
 777                          * Note: The following 3 are HEVC(H.265) clocks,
 778                          * and on the ACLK_HEVC_NIU (NOC).
 779                          */
 780                         pd_hevc@RK3288_PD_HEVC {
 781                                 reg = <RK3288_PD_HEVC>;
 782                                 clocks = <&cru ACLK_HEVC>,
 783                                          <&cru SCLK_HEVC_CABAC>,
 784                                          <&cru SCLK_HEVC_CORE>;
 785                                 pm_qos = <&qos_hevc_r>,
 786                                          <&qos_hevc_w>;
 787                         };
 788
 789                         /*
 790                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 791                          * (video endecoder & decoder) clocks that on the
 792                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 793                          */
 794                         pd_video@RK3288_PD_VIDEO {
 795                                 reg = <RK3288_PD_VIDEO>;
 796                                 clocks = <&cru ACLK_VCODEC>,
 797                                          <&cru HCLK_VCODEC>;
 798                                 pm_qos = <&qos_video>;
 799                         };
 800
 801                         /*
 802                          * Note: ACLK_GPU is the GPU clock,
 803                          * and on the ACLK_GPU_NIU (NOC).
 804                          */
 805                         pd_gpu@RK3288_PD_GPU {
 806                                 reg = <RK3288_PD_GPU>;
 807                                 clocks = <&cru ACLK_GPU>;
 808                                 pm_qos = <&qos_gpu_r>,
 809                                          <&qos_gpu_w>;
 810                         };
 811                 };
 812
 813                 reboot-mode {
 814                         compatible = "syscon-reboot-mode";
 815                         offset = <0x94>;
 816                         mode-normal = <BOOT_NORMAL>;
 817                         mode-recovery = <BOOT_RECOVERY>;
 818                         mode-bootloader = <BOOT_FASTBOOT>;
 819                         mode-loader = <BOOT_BL_DOWNLOAD>;
 820                 };
 821         };
 822
 823         sgrf: syscon@ff740000 {
 824                 compatible = "rockchip,rk3288-sgrf", "syscon";
 825                 reg = <0xff740000 0x1000>;
 826         };
 827
 828         cru: clock-controller@ff760000 {
 829                 compatible = "rockchip,rk3288-cru";
 830                 reg = <0xff760000 0x1000>;
 831                 rockchip,grf = <&grf>;
 832                 #clock-cells = <1>;
 833                 #reset-cells = <1>;
 834                 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 835                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
 836                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
 837                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
 838                                   <&cru PCLK_PERI>;
 839                 assigned-clock-rates = <594000000>, <400000000>,
 840                                        <500000000>, <300000000>,
 841                                        <150000000>, <75000000>,
 842                                        <300000000>, <150000000>,
 843                                        <75000000>;
 844         };
 845
 846         grf: syscon@ff770000 {
 847                 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
 848                 reg = <0xff770000 0x1000>;
 849
 850                 edp_phy: edp-phy {
 851                         compatible = "rockchip,rk3288-dp-phy";
 852                         clocks = <&cru SCLK_EDP_24M>;
 853                         clock-names = "24m";
 854                         #phy-cells = <0>;
 855                         status = "disabled";
 856                 };
 857
 858                 io_domains: io-domains {
 859                         compatible = "rockchip,rk3288-io-voltage-domain";
 860                         status = "disabled";
 861                 };
 862
 863                 usbphy: usbphy {
 864                         compatible = "rockchip,rk3288-usb-phy";
 865                         #address-cells = <1>;
 866                         #size-cells = <0>;
 867                         status = "disabled";
 868
 869                         usbphy0: usb-phy@320 {
 870                                 #phy-cells = <0>;
 871                                 reg = <0x320>;
 872                                 clocks = <&cru SCLK_OTGPHY0>;
 873                                 clock-names = "phyclk";
 874                                 #clock-cells = <0>;
 875                         };
 876
 877                         usbphy1: usb-phy@334 {
 878                                 #phy-cells = <0>;
 879                                 reg = <0x334>;
 880                                 clocks = <&cru SCLK_OTGPHY1>;
 881                                 clock-names = "phyclk";
 882                                 #clock-cells = <0>;
 883                         };
 884
 885                         usbphy2: usb-phy@348 {
 886                                 #phy-cells = <0>;
 887                                 reg = <0x348>;
 888                                 clocks = <&cru SCLK_OTGPHY2>;
 889                                 clock-names = "phyclk";
 890                                 #clock-cells = <0>;
 891                         };
 892                 };
 893         };
 894
 895         wdt: watchdog@ff800000 {
 896                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
 897                 reg = <0xff800000 0x100>;
 898                 clocks = <&cru PCLK_WDT>;
 899                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 900                 status = "disabled";
 901         };
 902
 903         spdif: sound@ff88b0000 {
 904                 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
 905                 reg = <0xff8b0000 0x10000>;
 906                 #sound-dai-cells = <0>;
 907                 clock-names = "hclk", "mclk";
 908                 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
 909                 dmas = <&dmac_bus_s 3>;
 910                 dma-names = "tx";
 911                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 912                 pinctrl-names = "default";
 913                 pinctrl-0 = <&spdif_tx>;
 914                 rockchip,grf = <&grf>;
 915                 status = "disabled";
 916         };
 917
 918         i2s: i2s@ff890000 {
 919                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
 920                 reg = <0xff890000 0x10000>;
 921                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 922                 #address-cells = <1>;
 923                 #size-cells = <0>;
 924                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
 925                 dma-names = "tx", "rx";
 926                 clock-names = "i2s_hclk", "i2s_clk";
 927                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
 928                 pinctrl-names = "default";
 929                 pinctrl-0 = <&i2s0_bus>;
 930                 rockchip,playback-channels = <8>;
 931                 rockchip,capture-channels = <2>;
 932                 status = "disabled";
 933         };
 934
 935         crypto: cypto-controller@ff8a0000 {
 936                 compatible = "rockchip,rk3288-crypto";
 937                 reg = <0xff8a0000 0x4000>;
 938                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 939                 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
 940                          <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
 941                 clock-names = "aclk", "hclk", "sclk", "apb_pclk";
 942                 resets = <&cru SRST_CRYPTO>;
 943                 reset-names = "crypto-rst";
 944                 status = "okay";
 945         };
 946
 947         vopb: vop@ff930000 {
 948                 compatible = "rockchip,rk3288-vop";
 949                 reg = <0xff930000 0x19c>;
 950                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 951                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
 952                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 953                 power-domains = <&power RK3288_PD_VIO>;
 954                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
 955                 reset-names = "axi", "ahb", "dclk";
 956                 iommus = <&vopb_mmu>;
 957                 status = "disabled";
 958
 959                 vopb_out: port {
 960                         #address-cells = <1>;
 961                         #size-cells = <0>;
 962
 963                         vopb_out_hdmi: endpoint@0 {
 964                                 reg = <0>;
 965                                 remote-endpoint = <&hdmi_in_vopb>;
 966                         };
 967
 968                         vopb_out_edp: endpoint@1 {
 969                                 reg = <1>;
 970                                 remote-endpoint = <&edp_in_vopb>;
 971                         };
 972
 973                         vopb_out_mipi: endpoint@2 {
 974                                 reg = <2>;
 975                                 remote-endpoint = <&mipi_in_vopb>;
 976                         };
 977                 };
 978         };
 979
 980         vopb_mmu: iommu@ff930300 {
 981                 compatible = "rockchip,iommu";
 982                 reg = <0xff930300 0x100>;
 983                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 984                 interrupt-names = "vopb_mmu";
 985                 power-domains = <&power RK3288_PD_VIO>;
 986                 #iommu-cells = <0>;
 987                 status = "disabled";
 988         };
 989
 990         vopl: vop@ff940000 {
 991                 compatible = "rockchip,rk3288-vop";
 992                 reg = <0xff940000 0x19c>;
 993                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 994                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
 995                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 996                 power-domains = <&power RK3288_PD_VIO>;
 997                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
 998                 reset-names = "axi", "ahb", "dclk";
 999                 iommus = <&vopl_mmu>;
1000                 status = "disabled";
1001
1002                 vopl_out: port {
1003                         #address-cells = <1>;
1004                         #size-cells = <0>;
1005
1006                         vopl_out_hdmi: endpoint@0 {
1007                                 reg = <0>;
1008                                 remote-endpoint = <&hdmi_in_vopl>;
1009                         };
1010
1011                         vopl_out_edp: endpoint@1 {
1012                                 reg = <1>;
1013                                 remote-endpoint = <&edp_in_vopl>;
1014                         };
1015
1016                         vopl_out_mipi: endpoint@2 {
1017                                 reg = <2>;
1018                                 remote-endpoint = <&mipi_in_vopl>;
1019                         };
1020                 };
1021         };
1022
1023         vopl_mmu: iommu@ff940300 {
1024                 compatible = "rockchip,iommu";
1025                 reg = <0xff940300 0x100>;
1026                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1027                 interrupt-names = "vopl_mmu";
1028                 power-domains = <&power RK3288_PD_VIO>;
1029                 #iommu-cells = <0>;
1030                 status = "disabled";
1031         };
1032
1033         mipi_dsi: mipi@ff960000 {
1034                 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1035                 reg = <0xff960000 0x4000>;
1036                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1037                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1038                 clock-names = "ref", "pclk";
1039                 power-domains = <&power RK3288_PD_VIO>;
1040                 rockchip,grf = <&grf>;
1041                 #address-cells = <1>;
1042                 #size-cells = <0>;
1043                 status = "disabled";
1044
1045                 ports {
1046                         mipi_in: port {
1047                                 #address-cells = <1>;
1048                                 #size-cells = <0>;
1049                                 mipi_in_vopb: endpoint@0 {
1050                                         reg = <0>;
1051                                         remote-endpoint = <&vopb_out_mipi>;
1052                                 };
1053                                 mipi_in_vopl: endpoint@1 {
1054                                         reg = <1>;
1055                                         remote-endpoint = <&vopl_out_mipi>;
1056                                 };
1057                         };
1058                 };
1059         };
1060
1061         edp: dp@ff970000 {
1062                 compatible = "rockchip,rk3288-dp";
1063                 reg = <0xff970000 0x4000>;
1064                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1065                 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1066                 clock-names = "dp", "pclk";
1067                 phys = <&edp_phy>;
1068                 phy-names = "dp";
1069                 resets = <&cru SRST_EDP>;
1070                 reset-names = "dp";
1071                 rockchip,grf = <&grf>;
1072                 status = "disabled";
1073
1074                 ports {
1075                         #address-cells = <1>;
1076                         #size-cells = <0>;
1077                         edp_in: port@0 {
1078                                 reg = <0>;
1079                                 #address-cells = <1>;
1080                                 #size-cells = <0>;
1081                                 edp_in_vopb: endpoint@0 {
1082                                         reg = <0>;
1083                                         remote-endpoint = <&vopb_out_edp>;
1084                                 };
1085                                 edp_in_vopl: endpoint@1 {
1086                                         reg = <1>;
1087                                         remote-endpoint = <&vopl_out_edp>;
1088                                 };
1089                         };
1090                 };
1091         };
1092
1093         hdmi: hdmi@ff980000 {
1094                 compatible = "rockchip,rk3288-dw-hdmi";
1095                 reg = <0xff980000 0x20000>;
1096                 reg-io-width = <4>;
1097                 rockchip,grf = <&grf>;
1098                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1099                 clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
1100                 clock-names = "iahb", "isfr";
1101                 power-domains = <&power RK3288_PD_VIO>;
1102                 status = "disabled";
1103
1104                 ports {
1105                         hdmi_in: port {
1106                                 #address-cells = <1>;
1107                                 #size-cells = <0>;
1108                                 hdmi_in_vopb: endpoint@0 {
1109                                         reg = <0>;
1110                                         remote-endpoint = <&vopb_out_hdmi>;
1111                                 };
1112                                 hdmi_in_vopl: endpoint@1 {
1113                                         reg = <1>;
1114                                         remote-endpoint = <&vopl_out_hdmi>;
1115                                 };
1116                         };
1117                 };
1118         };
1119
1120         qos_gpu_r: qos@ffaa0000 {
1121                 compatible = "syscon";
1122                 reg = <0xffaa0000 0x20>;
1123         };
1124
1125         qos_gpu_w: qos@ffaa0080 {
1126                 compatible = "syscon";
1127                 reg = <0xffaa0080 0x20>;
1128         };
1129
1130         qos_vio1_vop: qos@ffad0000 {
1131                 compatible = "syscon";
1132                 reg = <0xffad0000 0x20>;
1133         };
1134
1135         qos_vio1_isp_w0: qos@ffad0100 {
1136                 compatible = "syscon";
1137                 reg = <0xffad0100 0x20>;
1138         };
1139
1140         qos_vio1_isp_w1: qos@ffad0180 {
1141                 compatible = "syscon";
1142                 reg = <0xffad0180 0x20>;
1143         };
1144
1145         qos_vio0_vop: qos@ffad0400 {
1146                 compatible = "syscon";
1147                 reg = <0xffad0400 0x20>;
1148         };
1149
1150         qos_vio0_vip: qos@ffad0480 {
1151                 compatible = "syscon";
1152                 reg = <0xffad0480 0x20>;
1153         };
1154
1155         qos_vio0_iep: qos@ffad0500 {
1156                 compatible = "syscon";
1157                 reg = <0xffad0500 0x20>;
1158         };
1159
1160         qos_vio2_rga_r: qos@ffad0800 {
1161                 compatible = "syscon";
1162                 reg = <0xffad0800 0x20>;
1163         };
1164
1165         qos_vio2_rga_w: qos@ffad0880 {
1166                 compatible = "syscon";
1167                 reg = <0xffad0880 0x20>;
1168         };
1169
1170         qos_vio1_isp_r: qos@ffad0900 {
1171                 compatible = "syscon";
1172                 reg = <0xffad0900 0x20>;
1173         };
1174
1175         qos_video: qos@ffae0000 {
1176                 compatible = "syscon";
1177                 reg = <0xffae0000 0x20>;
1178         };
1179
1180         qos_hevc_r: qos@ffaf0000 {
1181                 compatible = "syscon";
1182                 reg = <0xffaf0000 0x20>;
1183         };
1184
1185         qos_hevc_w: qos@ffaf0080 {
1186                 compatible = "syscon";
1187                 reg = <0xffaf0080 0x20>;
1188         };
1189
1190         gic: interrupt-controller@ffc01000 {
1191                 compatible = "arm,gic-400";
1192                 interrupt-controller;
1193                 #interrupt-cells = <3>;
1194                 #address-cells = <0>;
1195
1196                 reg = <0xffc01000 0x1000>,
1197                       <0xffc02000 0x2000>,
1198                       <0xffc04000 0x2000>,
1199                       <0xffc06000 0x2000>;
1200                 interrupts = <GIC_PPI 9 0xf04>;
1201         };
1202
1203         efuse: efuse@ffb40000 {
1204                 compatible = "rockchip,rk3288-efuse";
1205                 reg = <0xffb40000 0x20>;
1206                 #address-cells = <1>;
1207                 #size-cells = <1>;
1208                 clocks = <&cru PCLK_EFUSE256>;
1209                 clock-names = "pclk_efuse";
1210
1211                 cpu_leakage: cpu_leakage@17 {
1212                         reg = <0x17 0x1>;
1213                 };
1214         };
1215
1216         pinctrl: pinctrl {
1217                 compatible = "rockchip,rk3288-pinctrl";
1218                 rockchip,grf = <&grf>;
1219                 rockchip,pmu = <&pmu>;
1220                 #address-cells = <1>;
1221                 #size-cells = <1>;
1222                 ranges;
1223
1224                 gpio0: gpio0@ff750000 {
1225                         compatible = "rockchip,gpio-bank";
1226                         reg =   <0xff750000 0x100>;
1227                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1228                         clocks = <&cru PCLK_GPIO0>;
1229
1230                         gpio-controller;
1231                         #gpio-cells = <2>;
1232
1233                         interrupt-controller;
1234                         #interrupt-cells = <2>;
1235                 };
1236
1237                 gpio1: gpio1@ff780000 {
1238                         compatible = "rockchip,gpio-bank";
1239                         reg = <0xff780000 0x100>;
1240                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1241                         clocks = <&cru PCLK_GPIO1>;
1242
1243                         gpio-controller;
1244                         #gpio-cells = <2>;
1245
1246                         interrupt-controller;
1247                         #interrupt-cells = <2>;
1248                 };
1249
1250                 gpio2: gpio2@ff790000 {
1251                         compatible = "rockchip,gpio-bank";
1252                         reg = <0xff790000 0x100>;
1253                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1254                         clocks = <&cru PCLK_GPIO2>;
1255
1256                         gpio-controller;
1257                         #gpio-cells = <2>;
1258
1259                         interrupt-controller;
1260                         #interrupt-cells = <2>;
1261                 };
1262
1263                 gpio3: gpio3@ff7a0000 {
1264                         compatible = "rockchip,gpio-bank";
1265                         reg = <0xff7a0000 0x100>;
1266                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1267                         clocks = <&cru PCLK_GPIO3>;
1268
1269                         gpio-controller;
1270                         #gpio-cells = <2>;
1271
1272                         interrupt-controller;
1273                         #interrupt-cells = <2>;
1274                 };
1275
1276                 gpio4: gpio4@ff7b0000 {
1277                         compatible = "rockchip,gpio-bank";
1278                         reg = <0xff7b0000 0x100>;
1279                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1280                         clocks = <&cru PCLK_GPIO4>;
1281
1282                         gpio-controller;
1283                         #gpio-cells = <2>;
1284
1285                         interrupt-controller;
1286                         #interrupt-cells = <2>;
1287                 };
1288
1289                 gpio5: gpio5@ff7c0000 {
1290                         compatible = "rockchip,gpio-bank";
1291                         reg = <0xff7c0000 0x100>;
1292                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1293                         clocks = <&cru PCLK_GPIO5>;
1294
1295                         gpio-controller;
1296                         #gpio-cells = <2>;
1297
1298                         interrupt-controller;
1299                         #interrupt-cells = <2>;
1300                 };
1301
1302                 gpio6: gpio6@ff7d0000 {
1303                         compatible = "rockchip,gpio-bank";
1304                         reg = <0xff7d0000 0x100>;
1305                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1306                         clocks = <&cru PCLK_GPIO6>;
1307
1308                         gpio-controller;
1309                         #gpio-cells = <2>;
1310
1311                         interrupt-controller;
1312                         #interrupt-cells = <2>;
1313                 };
1314
1315                 gpio7: gpio7@ff7e0000 {
1316                         compatible = "rockchip,gpio-bank";
1317                         reg = <0xff7e0000 0x100>;
1318                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1319                         clocks = <&cru PCLK_GPIO7>;
1320
1321                         gpio-controller;
1322                         #gpio-cells = <2>;
1323
1324                         interrupt-controller;
1325                         #interrupt-cells = <2>;
1326                 };
1327
1328                 gpio8: gpio8@ff7f0000 {
1329                         compatible = "rockchip,gpio-bank";
1330                         reg = <0xff7f0000 0x100>;
1331                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1332                         clocks = <&cru PCLK_GPIO8>;
1333
1334                         gpio-controller;
1335                         #gpio-cells = <2>;
1336
1337                         interrupt-controller;
1338                         #interrupt-cells = <2>;
1339                 };
1340
1341                 hdmi {
1342                         hdmi_ddc: hdmi-ddc {
1343                                 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1344                                                 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1345                         };
1346                 };
1347
1348                 pcfg_pull_up: pcfg-pull-up {
1349                         bias-pull-up;
1350                 };
1351
1352                 pcfg_pull_down: pcfg-pull-down {
1353                         bias-pull-down;
1354                 };
1355
1356                 pcfg_pull_none: pcfg-pull-none {
1357                         bias-disable;
1358                 };
1359
1360                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1361                         bias-disable;
1362                         drive-strength = <12>;
1363                 };
1364
1365                 sleep {
1366                         global_pwroff: global-pwroff {
1367                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1368                         };
1369
1370                         ddrio_pwroff: ddrio-pwroff {
1371                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1372                         };
1373
1374                         ddr0_retention: ddr0-retention {
1375                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1376                         };
1377
1378                         ddr1_retention: ddr1-retention {
1379                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1380                         };
1381                 };
1382
1383                 edp {
1384                         edp_hpd: edp-hpd {
1385                                 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
1386                         };
1387                 };
1388
1389                 i2c0 {
1390                         i2c0_xfer: i2c0-xfer {
1391                                 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1392                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1393                         };
1394                 };
1395
1396                 i2c1 {
1397                         i2c1_xfer: i2c1-xfer {
1398                                 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1399                                                 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1400                         };
1401                 };
1402
1403                 i2c2 {
1404                         i2c2_xfer: i2c2-xfer {
1405                                 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1406                                                 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1407                         };
1408                 };
1409
1410                 i2c3 {
1411                         i2c3_xfer: i2c3-xfer {
1412                                 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1413                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1414                         };
1415                 };
1416
1417                 i2c4 {
1418                         i2c4_xfer: i2c4-xfer {
1419                                 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1420                                                 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1421                         };
1422                 };
1423
1424                 i2c5 {
1425                         i2c5_xfer: i2c5-xfer {
1426                                 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1427                                                 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1428                         };
1429                 };
1430
1431                 i2s0 {
1432                         i2s0_bus: i2s0-bus {
1433                                 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1434                                                 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1435                                                 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1436                                                 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1437                                                 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1438                                                 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1439                         };
1440                 };
1441
1442                 sdmmc {
1443                         sdmmc_clk: sdmmc-clk {
1444                                 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1445                         };
1446
1447                         sdmmc_cmd: sdmmc-cmd {
1448                                 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1449                         };
1450
1451                         sdmmc_cd: sdmmc-cd {
1452                                 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1453                         };
1454
1455                         sdmmc_bus1: sdmmc-bus1 {
1456                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1457                         };
1458
1459                         sdmmc_bus4: sdmmc-bus4 {
1460                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1461                                                 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1462                                                 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1463                                                 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1464                         };
1465                 };
1466
1467                 sdio0 {
1468                         sdio0_bus1: sdio0-bus1 {
1469                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1470                         };
1471
1472                         sdio0_bus4: sdio0-bus4 {
1473                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1474                                                 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1475                                                 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1476                                                 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1477                         };
1478
1479                         sdio0_cmd: sdio0-cmd {
1480                                 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1481                         };
1482
1483                         sdio0_clk: sdio0-clk {
1484                                 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1485                         };
1486
1487                         sdio0_cd: sdio0-cd {
1488                                 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1489                         };
1490
1491                         sdio0_wp: sdio0-wp {
1492                                 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1493                         };
1494
1495                         sdio0_pwr: sdio0-pwr {
1496                                 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1497                         };
1498
1499                         sdio0_bkpwr: sdio0-bkpwr {
1500                                 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1501                         };
1502
1503                         sdio0_int: sdio0-int {
1504                                 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1505                         };
1506                 };
1507
1508                 sdio1 {
1509                         sdio1_bus1: sdio1-bus1 {
1510                                 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1511                         };
1512
1513                         sdio1_bus4: sdio1-bus4 {
1514                                 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1515                                                 <3 25 4 &pcfg_pull_up>,
1516                                                 <3 26 4 &pcfg_pull_up>,
1517                                                 <3 27 4 &pcfg_pull_up>;
1518                         };
1519
1520                         sdio1_cd: sdio1-cd {
1521                                 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1522                         };
1523
1524                         sdio1_wp: sdio1-wp {
1525                                 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1526                         };
1527
1528                         sdio1_bkpwr: sdio1-bkpwr {
1529                                 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1530                         };
1531
1532                         sdio1_int: sdio1-int {
1533                                 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1534                         };
1535
1536                         sdio1_cmd: sdio1-cmd {
1537                                 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1538                         };
1539
1540                         sdio1_clk: sdio1-clk {
1541                                 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1542                         };
1543
1544                         sdio1_pwr: sdio1-pwr {
1545                                 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1546                         };
1547                 };
1548
1549                 emmc {
1550                         emmc_clk: emmc-clk {
1551                                 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1552                         };
1553
1554                         emmc_cmd: emmc-cmd {
1555                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1556                         };
1557
1558                         emmc_pwr: emmc-pwr {
1559                                 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1560                         };
1561
1562                         emmc_bus1: emmc-bus1 {
1563                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1564                         };
1565
1566                         emmc_bus4: emmc-bus4 {
1567                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1568                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1569                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1570                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1571                         };
1572
1573                         emmc_bus8: emmc-bus8 {
1574                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1575                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1576                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1577                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1578                                                 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1579                                                 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1580                                                 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1581                                                 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1582                         };
1583                 };
1584
1585                 spi0 {
1586                         spi0_clk: spi0-clk {
1587                                 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1588                         };
1589                         spi0_cs0: spi0-cs0 {
1590                                 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1591                         };
1592                         spi0_tx: spi0-tx {
1593                                 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1594                         };
1595                         spi0_rx: spi0-rx {
1596                                 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1597                         };
1598                         spi0_cs1: spi0-cs1 {
1599                                 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1600                         };
1601                 };
1602                 spi1 {
1603                         spi1_clk: spi1-clk {
1604                                 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1605                         };
1606                         spi1_cs0: spi1-cs0 {
1607                                 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1608                         };
1609                         spi1_rx: spi1-rx {
1610                                 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1611                         };
1612                         spi1_tx: spi1-tx {
1613                                 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1614                         };
1615                 };
1616
1617                 spi2 {
1618                         spi2_cs1: spi2-cs1 {
1619                                 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1620                         };
1621                         spi2_clk: spi2-clk {
1622                                 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1623                         };
1624                         spi2_cs0: spi2-cs0 {
1625                                 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1626                         };
1627                         spi2_rx: spi2-rx {
1628                                 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1629                         };
1630                         spi2_tx: spi2-tx {
1631                                 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1632                         };
1633                 };
1634
1635                 uart0 {
1636                         uart0_xfer: uart0-xfer {
1637                                 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1638                                                 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1639                         };
1640
1641                         uart0_cts: uart0-cts {
1642                                 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1643                         };
1644
1645                         uart0_rts: uart0-rts {
1646                                 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1647                         };
1648                 };
1649
1650                 uart1 {
1651                         uart1_xfer: uart1-xfer {
1652                                 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1653                                                 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1654                         };
1655
1656                         uart1_cts: uart1-cts {
1657                                 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1658                         };
1659
1660                         uart1_rts: uart1-rts {
1661                                 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1662                         };
1663                 };
1664
1665                 uart2 {
1666                         uart2_xfer: uart2-xfer {
1667                                 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1668                                                 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1669                         };
1670                         /* no rts / cts for uart2 */
1671                 };
1672
1673                 uart3 {
1674                         uart3_xfer: uart3-xfer {
1675                                 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1676                                                 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1677                         };
1678
1679                         uart3_cts: uart3-cts {
1680                                 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
1681                         };
1682
1683                         uart3_rts: uart3-rts {
1684                                 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1685                         };
1686                 };
1687
1688                 uart4 {
1689                         uart4_xfer: uart4-xfer {
1690                                 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1691                                                 <5 13 3 &pcfg_pull_none>;
1692                         };
1693
1694                         uart4_cts: uart4-cts {
1695                                 rockchip,pins = <5 14 3 &pcfg_pull_up>;
1696                         };
1697
1698                         uart4_rts: uart4-rts {
1699                                 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1700                         };
1701                 };
1702
1703                 tsadc {
1704                         otp_gpio: otp-gpio {
1705                                 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
1706                         };
1707
1708                         otp_out: otp-out {
1709                                 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1710                         };
1711                 };
1712
1713                 pwm0 {
1714                         pwm0_pin: pwm0-pin {
1715                                 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1716                         };
1717                 };
1718
1719                 pwm1 {
1720                         pwm1_pin: pwm1-pin {
1721                                 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1722                         };
1723                 };
1724
1725                 pwm2 {
1726                         pwm2_pin: pwm2-pin {
1727                                 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1728                         };
1729                 };
1730
1731                 pwm3 {
1732                         pwm3_pin: pwm3-pin {
1733                                 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1734                         };
1735                 };
1736
1737                 gmac {
1738                         rgmii_pins: rgmii-pins {
1739                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1740                                                 <3 31 3 &pcfg_pull_none>,
1741                                                 <3 26 3 &pcfg_pull_none>,
1742                                                 <3 27 3 &pcfg_pull_none>,
1743                                                 <3 28 3 &pcfg_pull_none_12ma>,
1744                                                 <3 29 3 &pcfg_pull_none_12ma>,
1745                                                 <3 24 3 &pcfg_pull_none_12ma>,
1746                                                 <3 25 3 &pcfg_pull_none_12ma>,
1747                                                 <4 0 3 &pcfg_pull_none>,
1748                                                 <4 5 3 &pcfg_pull_none>,
1749                                                 <4 6 3 &pcfg_pull_none>,
1750                                                 <4 9 3 &pcfg_pull_none_12ma>,
1751                                                 <4 4 3 &pcfg_pull_none_12ma>,
1752                                                 <4 1 3 &pcfg_pull_none>,
1753                                                 <4 3 3 &pcfg_pull_none>;
1754                         };
1755
1756                         rmii_pins: rmii-pins {
1757                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1758                                                 <3 31 3 &pcfg_pull_none>,
1759                                                 <3 28 3 &pcfg_pull_none>,
1760                                                 <3 29 3 &pcfg_pull_none>,
1761                                                 <4 0 3 &pcfg_pull_none>,
1762                                                 <4 5 3 &pcfg_pull_none>,
1763                                                 <4 4 3 &pcfg_pull_none>,
1764                                                 <4 1 3 &pcfg_pull_none>,
1765                                                 <4 2 3 &pcfg_pull_none>,
1766                                                 <4 3 3 &pcfg_pull_none>;
1767                         };
1768                 };
1769
1770                 spdif {
1771                         spdif_tx: spdif-tx {
1772                                 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
1773                         };
1774                 };
1775         };
1776 };