arch/arm/boot/dts/stih418-clock.dtsi

   1 /*
   2  * Copyright (C) 2015 STMicroelectronics R&D Limited
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 #include <dt-bindings/clock/stih418-clks.h>
   9 / {
  10         clocks {
  11                 #address-cells = <1>;
  12                 #size-cells = <1>;
  13                 ranges;
  14
  15                 compatible = "st,stih418-clk", "simple-bus";
  16
  17                 /*
  18                  * Fixed 30MHz oscillator inputs to SoC
  19                  */
  20                 clk_sysin: clk-sysin {
  21                         #clock-cells = <0>;
  22                         compatible = "fixed-clock";
  23                         clock-frequency = <30000000>;
  24                         clock-output-names = "CLK_SYSIN";
  25                 };
  26
  27                 /*
  28                  * ARM Peripheral clock for timers
  29                  */
  30                 arm_periph_clk: clk-m-a9-periphs {
  31                         #clock-cells = <0>;
  32                         compatible = "fixed-factor-clock";
  33                         clocks = <&clk_m_a9>;
  34                         clock-div = <2>;
  35                         clock-mult = <1>;
  36                 };
  37
  38                 /*
  39                  * A9 PLL.
  40                  */
  41                 clockgen-a9@92b0000 {
  42                         compatible = "st,clkgen-c32";
  43                         reg = <0x92b0000 0xffff>;
  44
  45                         clockgen_a9_pll: clockgen-a9-pll {
  46                                 #clock-cells = <1>;
  47                                 compatible = "st,stih418-clkgen-plla9";
  48
  49                                 clocks = <&clk_sysin>;
  50
  51                                 clock-output-names = "clockgen-a9-pll-odf";
  52                         };
  53                 };
  54
  55                 /*
  56                  * ARM CPU related clocks.
  57                  */
  58                 clk_m_a9: clk-m-a9@92b0000 {
  59                         #clock-cells = <0>;
  60                         compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
  61                         reg = <0x92b0000 0x10000>;
  62
  63                         clocks = <&clockgen_a9_pll 0>,
  64                                  <&clockgen_a9_pll 0>,
  65                                  <&clk_s_c0_flexgen 13>,
  66                                  <&clk_m_a9_ext2f_div2>;
  67                 };
  68
  69                 /*
  70                  * ARM Peripheral clock for timers
  71                  */
  72                 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
  73                         #clock-cells = <0>;
  74                         compatible = "fixed-factor-clock";
  75
  76                         clocks = <&clk_s_c0_flexgen 13>;
  77
  78                         clock-output-names = "clk-m-a9-ext2f-div2";
  79
  80                         clock-div = <2>;
  81                         clock-mult = <1>;
  82                 };
  83
  84                 /*
  85                  * Bootloader initialized system infrastructure clock for
  86                  * serial devices.
  87                  */
  88                 clk_ext2f_a9: clockgen-c0@13 {
  89                         #clock-cells = <0>;
  90                         compatible = "fixed-clock";
  91                         clock-frequency = <200000000>;
  92                         clock-output-names = "clk-s-icn-reg-0";
  93                 };
  94
  95                 clockgen-a@090ff000 {
  96                         compatible = "st,clkgen-c32";
  97                         reg = <0x90ff000 0x1000>;
  98
  99                         clk_s_a0_pll: clk-s-a0-pll {
 100                                 #clock-cells = <1>;
 101                                 compatible = "st,clkgen-pll0";
 102
 103                                 clocks = <&clk_sysin>;
 104
 105                                 clock-output-names = "clk-s-a0-pll-ofd-0";
 106                         };
 107
 108                         clk_s_a0_flexgen: clk-s-a0-flexgen {
 109                                 compatible = "st,flexgen";
 110
 111                                 #clock-cells = <1>;
 112
 113                                 clocks = <&clk_s_a0_pll 0>,
 114                                          <&clk_sysin>;
 115
 116                                 clock-output-names = "clk-ic-lmi0",
 117                                                      "clk-ic-lmi1";
 118                         };
 119                 };
 120
 121                 clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
 122                         #clock-cells = <1>;
 123                         compatible = "st,quadfs-pll";
 124                         reg = <0x9103000 0x1000>;
 125
 126                         clocks = <&clk_sysin>;
 127
 128                         clock-output-names = "clk-s-c0-fs0-ch0",
 129                                              "clk-s-c0-fs0-ch1",
 130                                              "clk-s-c0-fs0-ch2",
 131                                              "clk-s-c0-fs0-ch3";
 132                 };
 133
 134                 clk_s_c0: clockgen-c@09103000 {
 135                         compatible = "st,clkgen-c32";
 136                         reg = <0x9103000 0x1000>;
 137
 138                         clk_s_c0_pll0: clk-s-c0-pll0 {
 139                                 #clock-cells = <1>;
 140                                 compatible = "st,clkgen-pll0";
 141
 142                                 clocks = <&clk_sysin>;
 143
 144                                 clock-output-names = "clk-s-c0-pll0-odf-0";
 145                         };
 146
 147                         clk_s_c0_pll1: clk-s-c0-pll1 {
 148                                 #clock-cells = <1>;
 149                                 compatible = "st,clkgen-pll1";
 150
 151                                 clocks = <&clk_sysin>;
 152
 153                                 clock-output-names = "clk-s-c0-pll1-odf-0";
 154                         };
 155
 156                         clk_s_c0_flexgen: clk-s-c0-flexgen {
 157                                 #clock-cells = <1>;
 158                                 compatible = "st,flexgen";
 159
 160                                 clocks = <&clk_s_c0_pll0 0>,
 161                                          <&clk_s_c0_pll1 0>,
 162                                          <&clk_s_c0_quadfs 0>,
 163                                          <&clk_s_c0_quadfs 1>,
 164                                          <&clk_s_c0_quadfs 2>,
 165                                          <&clk_s_c0_quadfs 3>,
 166                                          <&clk_sysin>;
 167
 168                                 clock-output-names = "clk-icn-gpu",
 169                                                      "clk-fdma",
 170                                                      "clk-nand",
 171                                                      "clk-hva",
 172                                                      "clk-proc-stfe",
 173                                                      "clk-tp",
 174                                                      "clk-rx-icn-dmu",
 175                                                      "clk-rx-icn-hva",
 176                                                      "clk-icn-cpu",
 177                                                      "clk-tx-icn-dmu",
 178                                                      "clk-mmc-0",
 179                                                      "clk-mmc-1",
 180                                                      "clk-jpegdec",
 181                                                      "clk-icn-reg",
 182                                                      "clk-proc-bdisp-0",
 183                                                      "clk-proc-bdisp-1",
 184                                                      "clk-pp-dmu",
 185                                                      "clk-vid-dmu",
 186                                                      "clk-dss-lpc",
 187                                                      "clk-st231-aud-0",
 188                                                      "clk-st231-gp-1",
 189                                                      "clk-st231-dmu",
 190                                                      "clk-icn-lmi",
 191                                                      "clk-tx-icn-1",
 192                                                      "clk-icn-sbc",
 193                                                      "clk-stfe-frc2",
 194                                                      "clk-eth-phyref",
 195                                                      "clk-eth-ref-phyclk",
 196                                                      "clk-flash-promip",
 197                                                      "clk-main-disp",
 198                                                      "clk-aux-disp",
 199                                                      "clk-compo-dvp",
 200                                                      "clk-tx-icn-hades",
 201                                                      "clk-rx-icn-hades",
 202                                                      "clk-icn-reg-16",
 203                                                      "clk-pp-hevc",
 204                                                      "clk-clust-hevc",
 205                                                      "clk-hwpe-hevc",
 206                                                      "clk-fc-hevc",
 207                                                      "clk-proc-mixer",
 208                                                      "clk-proc-sc",
 209                                                      "clk-avsp-hevc";
 210                         };
 211                 };
 212
 213                 clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
 214                         #clock-cells = <1>;
 215                         compatible = "st,quadfs";
 216                         reg = <0x9104000 0x1000>;
 217
 218                         clocks = <&clk_sysin>;
 219
 220                         clock-output-names = "clk-s-d0-fs0-ch0",
 221                                              "clk-s-d0-fs0-ch1",
 222                                              "clk-s-d0-fs0-ch2",
 223                                              "clk-s-d0-fs0-ch3";
 224                 };
 225
 226                 clockgen-d0@09104000 {
 227                         compatible = "st,clkgen-c32";
 228                         reg = <0x9104000 0x1000>;
 229
 230                         clk_s_d0_flexgen: clk-s-d0-flexgen {
 231                                 #clock-cells = <1>;
 232                                 compatible = "st,flexgen-audio", "st,flexgen";
 233
 234                                 clocks = <&clk_s_d0_quadfs 0>,
 235                                          <&clk_s_d0_quadfs 1>,
 236                                          <&clk_s_d0_quadfs 2>,
 237                                          <&clk_s_d0_quadfs 3>,
 238                                          <&clk_sysin>;
 239
 240                                 clock-output-names = "clk-pcm-0",
 241                                                      "clk-pcm-1",
 242                                                      "clk-pcm-2",
 243                                                      "clk-spdiff",
 244                                                      "clk-pcmr10-master",
 245                                                      "clk-usb2-phy";
 246                         };
 247                 };
 248
 249                 clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
 250                         #clock-cells = <1>;
 251                         compatible = "st,quadfs";
 252                         reg = <0x9106000 0x1000>;
 253
 254                         clocks = <&clk_sysin>;
 255
 256                         clock-output-names = "clk-s-d2-fs0-ch0",
 257                                              "clk-s-d2-fs0-ch1",
 258                                              "clk-s-d2-fs0-ch2",
 259                                              "clk-s-d2-fs0-ch3";
 260                 };
 261
 262                 clk_tmdsout_hdmi: clk-tmdsout-hdmi {
 263                         #clock-cells = <0>;
 264                         compatible = "fixed-clock";
 265                         clock-frequency = <0>;
 266                 };
 267
 268                 clockgen-d2@x9106000 {
 269                         compatible = "st,clkgen-c32";
 270                         reg = <0x9106000 0x1000>;
 271
 272                         clk_s_d2_flexgen: clk-s-d2-flexgen {
 273                                 #clock-cells = <1>;
 274                                 compatible = "st,flexgen-video", "st,flexgen";
 275
 276                                 clocks = <&clk_s_d2_quadfs 0>,
 277                                          <&clk_s_d2_quadfs 1>,
 278                                          <&clk_s_d2_quadfs 2>,
 279                                          <&clk_s_d2_quadfs 3>,
 280                                          <&clk_sysin>,
 281                                          <&clk_sysin>,
 282                                          <&clk_tmdsout_hdmi>;
 283
 284                                 clock-output-names = "clk-pix-main-disp",
 285                                                      "",
 286                                                      "",
 287                                                      "",
 288                                                      "",
 289                                                      "clk-tmds-hdmi-div2",
 290                                                      "clk-pix-aux-disp",
 291                                                      "clk-denc",
 292                                                      "clk-pix-hddac",
 293                                                      "clk-hddac",
 294                                                      "clk-sddac",
 295                                                      "clk-pix-dvo",
 296                                                      "clk-dvo",
 297                                                      "clk-pix-hdmi",
 298                                                      "clk-tmds-hdmi",
 299                                                      "clk-ref-hdmiphy",
 300                                                      "", "", "", "", "",
 301                                                      "", "", "", "", "",
 302                                                      "", "", "", "", "",
 303                                                      "", "", "", "", "",
 304                                                      "", "", "", "", "",
 305                                                      "", "", "", "", "",
 306                                                      "", "clk-vp9";
 307                         };
 308                 };
 309
 310                 clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
 311                         #clock-cells = <1>;
 312                         compatible = "st,quadfs";
 313                         reg = <0x9107000 0x1000>;
 314
 315                         clocks = <&clk_sysin>;
 316
 317                         clock-output-names = "clk-s-d3-fs0-ch0",
 318                                              "clk-s-d3-fs0-ch1",
 319                                              "clk-s-d3-fs0-ch2",
 320                                              "clk-s-d3-fs0-ch3";
 321                 };
 322
 323                 clockgen-d3@9107000 {
 324                         compatible = "st,clkgen-c32";
 325                         reg = <0x9107000 0x1000>;
 326
 327                         clk_s_d3_flexgen: clk-s-d3-flexgen {
 328                                 #clock-cells = <1>;
 329                                 compatible = "st,flexgen";
 330
 331                                 clocks = <&clk_s_d3_quadfs 0>,
 332                                          <&clk_s_d3_quadfs 1>,
 333                                          <&clk_s_d3_quadfs 2>,
 334                                          <&clk_s_d3_quadfs 3>,
 335                                          <&clk_sysin>;
 336
 337                                 clock-output-names = "clk-stfe-frc1",
 338                                                      "clk-tsout-0",
 339                                                      "clk-tsout-1",
 340                                                      "clk-mchi",
 341                                                      "clk-vsens-compo",
 342                                                      "clk-frc1-remote",
 343                                                      "clk-lpc-0",
 344                                                      "clk-lpc-1";
 345                         };
 346                 };
 347         };
 348 };