| blob | 87b07fbadbbedd209491c3972bdebe4e519a53e4 |
1 /dts-v1/;
3 #include <dt-bindings/input/input.h>
4 #include "tegra20.dtsi"
6 / {
7 model = "Compulab TrimSlice board";
8 compatible = "compulab,trimslice", "nvidia,tegra20";
10 aliases {
11 rtc0 = "/i2c@7000c500/rtc@56";
12 rtc1 = "/rtc@7000e000";
13 serial0 = &uarta;
14 };
16 chosen {
17 stdout-path = "serial0:115200n8";
18 };
20 memory {
21 reg = <0x00000000 0x40000000>;
22 };
24 host1x@50000000 {
25 hdmi@54280000 {
26 status = "okay";
28 vdd-supply = <&hdmi_vdd_reg>;
29 pll-supply = <&hdmi_pll_reg>;
31 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
32 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
33 GPIO_ACTIVE_HIGH>;
34 };
35 };
37 pinmux@70000014 {
38 pinctrl-names = "default";
39 pinctrl-0 = <&state_default>;
41 state_default: pinmux {
42 ata {
43 nvidia,pins = "ata";
44 nvidia,function = "ide";
45 };
46 atb {
47 nvidia,pins = "atb", "gma";
48 nvidia,function = "sdio4";
49 };
50 atc {
51 nvidia,pins = "atc", "gmb";
52 nvidia,function = "nand";
53 };
54 atd {
55 nvidia,pins = "atd", "ate", "gme", "pta";
56 nvidia,function = "gmi";
57 };
58 cdev1 {
59 nvidia,pins = "cdev1";
60 nvidia,function = "plla_out";
61 };
62 cdev2 {
63 nvidia,pins = "cdev2";
64 nvidia,function = "pllp_out4";
65 };
66 crtp {
67 nvidia,pins = "crtp";
68 nvidia,function = "crt";
69 };
70 csus {
71 nvidia,pins = "csus";
72 nvidia,function = "vi_sensor_clk";
73 };
74 dap1 {
75 nvidia,pins = "dap1";
76 nvidia,function = "dap1";
77 };
78 dap2 {
79 nvidia,pins = "dap2";
80 nvidia,function = "dap2";
81 };
82 dap3 {
83 nvidia,pins = "dap3";
84 nvidia,function = "dap3";
85 };
86 dap4 {
87 nvidia,pins = "dap4";
88 nvidia,function = "dap4";
89 };
90 ddc {
91 nvidia,pins = "ddc";
92 nvidia,function = "i2c2";
93 };
94 dta {
95 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
96 nvidia,function = "vi";
97 };
98 dtf {
99 nvidia,pins = "dtf";
100 nvidia,function = "i2c3";
101 };
102 gmc {
103 nvidia,pins = "gmc", "gmd";
104 nvidia,function = "sflash";
105 };
106 gpu {
107 nvidia,pins = "gpu";
108 nvidia,function = "uarta";
109 };
110 gpu7 {
111 nvidia,pins = "gpu7";
112 nvidia,function = "rtck";
113 };
114 gpv {
115 nvidia,pins = "gpv", "slxa", "slxk";
116 nvidia,function = "pcie";
117 };
118 hdint {
119 nvidia,pins = "hdint";
120 nvidia,function = "hdmi";
121 };
122 i2cp {
123 nvidia,pins = "i2cp";
124 nvidia,function = "i2cp";
125 };
126 irrx {
127 nvidia,pins = "irrx", "irtx";
128 nvidia,function = "uartb";
129 };
130 kbca {
131 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
132 "kbce", "kbcf";
133 nvidia,function = "kbc";
134 };
135 lcsn {
136 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
137 "ld3", "ld4", "ld5", "ld6", "ld7",
138 "ld8", "ld9", "ld10", "ld11", "ld12",
139 "ld13", "ld14", "ld15", "ld16", "ld17",
140 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
141 "lhs", "lm0", "lm1", "lpp", "lpw0",
142 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
143 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
144 "lvs";
145 nvidia,function = "displaya";
146 };
147 owc {
148 nvidia,pins = "owc", "uac";
149 nvidia,function = "rsvd2";
150 };
151 pmc {
152 nvidia,pins = "pmc";
153 nvidia,function = "pwr_on";
154 };
155 rm {
156 nvidia,pins = "rm";
157 nvidia,function = "i2c1";
158 };
159 sdb {
160 nvidia,pins = "sdb", "sdc", "sdd";
161 nvidia,function = "pwm";
162 };
163 sdio1 {
164 nvidia,pins = "sdio1";
165 nvidia,function = "sdio1";
166 };
167 slxc {
168 nvidia,pins = "slxc", "slxd";
169 nvidia,function = "sdio3";
170 };
171 spdi {
172 nvidia,pins = "spdi", "spdo";
173 nvidia,function = "spdif";
174 };
175 spia {
176 nvidia,pins = "spia", "spib", "spic";
177 nvidia,function = "spi2";
178 };
179 spid {
180 nvidia,pins = "spid", "spie", "spif";
181 nvidia,function = "spi1";
182 };
183 spig {
184 nvidia,pins = "spig", "spih";
185 nvidia,function = "spi2_alt";
186 };
187 uaa {
188 nvidia,pins = "uaa", "uab", "uda";
189 nvidia,function = "ulpi";
190 };
191 uad {
192 nvidia,pins = "uad";
193 nvidia,function = "irda";
194 };
195 uca {
196 nvidia,pins = "uca", "ucb";
197 nvidia,function = "uartc";
198 };
199 conf_ata {
200 nvidia,pins = "ata", "atc", "atd", "ate",
201 "crtp", "dap2", "dap3", "dap4", "dta",
202 "dtb", "dtc", "dtd", "dte", "gmb",
203 "gme", "i2cp", "pta", "slxc", "slxd",
204 "spdi", "spdo", "uda";
205 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
206 nvidia,tristate = <TEGRA_PIN_ENABLE>;
207 };
208 conf_atb {
209 nvidia,pins = "atb", "cdev1", "cdev2", "dap1",
210 "gma", "gmc", "gmd", "gpu", "gpu7",
211 "gpv", "sdio1", "slxa", "slxk", "uac";
212 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
213 nvidia,tristate = <TEGRA_PIN_DISABLE>;
214 };
215 conf_ck32 {
216 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
217 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
218 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
219 };
220 conf_csus {
221 nvidia,pins = "csus", "spia", "spib",
222 "spid", "spif";
223 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
224 nvidia,tristate = <TEGRA_PIN_ENABLE>;
225 };
226 conf_ddc {
227 nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd";
228 nvidia,pull = <TEGRA_PIN_PULL_UP>;
229 nvidia,tristate = <TEGRA_PIN_DISABLE>;
230 };
231 conf_hdint {
232 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
233 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
234 "lvp0", "pmc";
235 nvidia,tristate = <TEGRA_PIN_ENABLE>;
236 };
237 conf_irrx {
238 nvidia,pins = "irrx", "irtx", "kbca", "kbcb",
239 "kbcc", "kbcd", "kbce", "kbcf", "owc",
240 "spic", "spie", "spig", "spih", "uaa",
241 "uab", "uad", "uca", "ucb";
242 nvidia,pull = <TEGRA_PIN_PULL_UP>;
243 nvidia,tristate = <TEGRA_PIN_ENABLE>;
244 };
245 conf_lc {
246 nvidia,pins = "lc", "ls";
247 nvidia,pull = <TEGRA_PIN_PULL_UP>;
248 };
249 conf_ld0 {
250 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
251 "ld5", "ld6", "ld7", "ld8", "ld9",
252 "ld10", "ld11", "ld12", "ld13", "ld14",
253 "ld15", "ld16", "ld17", "ldi", "lhp0",
254 "lhp1", "lhp2", "lhs", "lm0", "lpp",
255 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
256 "lvs", "sdb";
257 nvidia,tristate = <TEGRA_PIN_DISABLE>;
258 };
259 conf_ld17_0 {
260 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
261 "ld23_22";
262 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
263 };
264 conf_spif {
265 nvidia,pins = "spif";
266 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
267 nvidia,tristate = <TEGRA_PIN_DISABLE>;
268 };
269 };
270 };
272 i2s@70002800 {
273 status = "okay";
274 };
276 serial@70006000 {
277 status = "okay";
278 };
280 dvi_ddc: i2c@7000c000 {
281 status = "okay";
282 clock-frequency = <100000>;
283 };
285 spi@7000c380 {
286 status = "okay";
287 spi-max-frequency = <48000000>;
288 spi-flash@0 {
289 compatible = "winbond,w25q80bl";
290 reg = <0>;
291 spi-max-frequency = <48000000>;
292 };
293 };
295 hdmi_ddc: i2c@7000c400 {
296 status = "okay";
297 clock-frequency = <100000>;
298 };
300 i2c@7000c500 {
301 status = "okay";
302 clock-frequency = <400000>;
304 codec: codec@1a {
305 compatible = "ti,tlv320aic23";
306 reg = <0x1a>;
307 };
309 rtc@56 {
310 compatible = "emmicro,em3027";
311 reg = <0x56>;
312 };
313 };
315 pmc@7000e400 {
316 nvidia,suspend-mode = <1>;
317 nvidia,cpu-pwr-good-time = <5000>;
318 nvidia,cpu-pwr-off-time = <5000>;
319 nvidia,core-pwr-good-time = <3845 3845>;
320 nvidia,core-pwr-off-time = <3875>;
321 nvidia,sys-clock-req-active-high;
322 };
324 pcie-controller@80003000 {
325 status = "okay";
327 avdd-pex-supply = <&pci_vdd_reg>;
328 vdd-pex-supply = <&pci_vdd_reg>;
329 avdd-pex-pll-supply = <&pci_vdd_reg>;
330 avdd-plle-supply = <&pci_vdd_reg>;
331 vddio-pex-clk-supply = <&pci_clk_reg>;
333 pci@1,0 {
334 status = "okay";
335 };
336 };
338 usb@c5000000 {
339 status = "okay";
340 };
342 usb-phy@c5000000 {
343 status = "okay";
344 vbus-supply = <&vbus_reg>;
345 };
347 usb@c5004000 {
348 status = "okay";
349 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
350 GPIO_ACTIVE_LOW>;
351 };
353 usb-phy@c5004000 {
354 status = "okay";
355 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
356 GPIO_ACTIVE_LOW>;
357 };
359 usb@c5008000 {
360 status = "okay";
361 };
363 usb-phy@c5008000 {
364 status = "okay";
365 };
367 sdhci@c8000000 {
368 status = "okay";
369 broken-cd;
370 bus-width = <4>;
371 };
373 sdhci@c8000600 {
374 status = "okay";
375 cd-gpios = <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_LOW>;
376 wp-gpios = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
377 bus-width = <4>;
378 };
380 clocks {
381 compatible = "simple-bus";
382 #address-cells = <1>;
383 #size-cells = <0>;
385 clk32k_in: clock@0 {
386 compatible = "fixed-clock";
387 reg = <0>;
388 #clock-cells = <0>;
389 clock-frequency = <32768>;
390 };
391 };
393 gpio-keys {
394 compatible = "gpio-keys";
396 power {
397 label = "Power";
398 gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>;
399 linux,code = <KEY_POWER>;
400 wakeup-source;
401 };
402 };
404 poweroff {
405 compatible = "gpio-poweroff";
406 gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>;
407 };
409 regulators {
410 compatible = "simple-bus";
411 #address-cells = <1>;
412 #size-cells = <0>;
414 hdmi_vdd_reg: regulator@0 {
415 compatible = "regulator-fixed";
416 reg = <0>;
417 regulator-name = "avdd_hdmi";
418 regulator-min-microvolt = <3300000>;
419 regulator-max-microvolt = <3300000>;
420 regulator-always-on;
421 };
423 hdmi_pll_reg: regulator@1 {
424 compatible = "regulator-fixed";
425 reg = <1>;
426 regulator-name = "avdd_hdmi_pll";
427 regulator-min-microvolt = <1800000>;
428 regulator-max-microvolt = <1800000>;
429 regulator-always-on;
430 };
432 vbus_reg: regulator@2 {
433 compatible = "regulator-fixed";
434 reg = <2>;
435 regulator-name = "usb1_vbus";
436 regulator-min-microvolt = <5000000>;
437 regulator-max-microvolt = <5000000>;
438 enable-active-high;
439 gpio = <&gpio TEGRA_GPIO(V, 2) 0>;
440 regulator-always-on;
441 regulator-boot-on;
442 };
444 pci_clk_reg: regulator@3 {
445 compatible = "regulator-fixed";
446 reg = <3>;
447 regulator-name = "pci_clk";
448 regulator-min-microvolt = <3300000>;
449 regulator-max-microvolt = <3300000>;
450 regulator-always-on;
451 };
453 pci_vdd_reg: regulator@4 {
454 compatible = "regulator-fixed";
455 reg = <4>;
456 regulator-name = "pci_vdd";
457 regulator-min-microvolt = <1050000>;
458 regulator-max-microvolt = <1050000>;
459 regulator-always-on;
460 };
461 };
463 sound {
464 compatible = "nvidia,tegra-audio-trimslice";
465 nvidia,i2s-controller = <&tegra_i2s1>;
466 nvidia,audio-codec = <&codec>;
468 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
469 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
470 <&tegra_car TEGRA20_CLK_CDEV1>;
471 clock-names = "pll_a", "pll_a_out0", "mclk";
472 };
473 };