| blob | 15f4fd3f469561caa7fba30fed8c6a10c18c6668 |
1 /*
2 * ARM Ltd. Versatile Express
3 *
4 * CoreTile Express A15x2 (version with Test Chip 1)
5 * Cortex-A15 MPCore (V2P-CA15)
6 *
7 * HBI-0237A
8 */
10 /dts-v1/;
12 / {
13 model = "V2P-CA15";
14 arm,hbi = <0x237>;
15 arm,vexpress,site = <0xf>;
16 compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress";
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
21 chosen { };
23 aliases {
24 serial0 = &v2m_serial0;
25 serial1 = &v2m_serial1;
26 serial2 = &v2m_serial2;
27 serial3 = &v2m_serial3;
28 i2c0 = &v2m_i2c_dvi;
29 i2c1 = &v2m_i2c_pcie;
30 };
32 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
36 cpu@0 {
37 device_type = "cpu";
38 compatible = "arm,cortex-a15";
39 reg = <0>;
40 };
42 cpu@1 {
43 device_type = "cpu";
44 compatible = "arm,cortex-a15";
45 reg = <1>;
46 };
47 };
49 memory@80000000 {
50 device_type = "memory";
51 reg = <0 0x80000000 0 0x40000000>;
52 };
54 hdlcd@2b000000 {
55 compatible = "arm,hdlcd";
56 reg = <0 0x2b000000 0 0x1000>;
57 interrupts = <0 85 4>;
58 clocks = <&hdlcd_clk>;
59 clock-names = "pxlclk";
60 };
62 memory-controller@2b0a0000 {
63 compatible = "arm,pl341", "arm,primecell";
64 reg = <0 0x2b0a0000 0 0x1000>;
65 clocks = <&sys_pll>;
66 clock-names = "apb_pclk";
67 };
69 wdt@2b060000 {
70 compatible = "arm,sp805", "arm,primecell";
71 status = "disabled";
72 reg = <0 0x2b060000 0 0x1000>;
73 interrupts = <0 98 4>;
74 clocks = <&sys_pll>;
75 clock-names = "apb_pclk";
76 };
78 gic: interrupt-controller@2c001000 {
79 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
80 #interrupt-cells = <3>;
81 #address-cells = <0>;
82 interrupt-controller;
83 reg = <0 0x2c001000 0 0x1000>,
84 <0 0x2c002000 0 0x2000>,
85 <0 0x2c004000 0 0x2000>,
86 <0 0x2c006000 0 0x2000>;
87 interrupts = <1 9 0xf04>;
88 };
90 memory-controller@7ffd0000 {
91 compatible = "arm,pl354", "arm,primecell";
92 reg = <0 0x7ffd0000 0 0x1000>;
93 interrupts = <0 86 4>,
94 <0 87 4>;
95 clocks = <&sys_pll>;
96 clock-names = "apb_pclk";
97 };
99 dma@7ffb0000 {
100 compatible = "arm,pl330", "arm,primecell";
101 reg = <0 0x7ffb0000 0 0x1000>;
102 interrupts = <0 92 4>,
103 <0 88 4>,
104 <0 89 4>,
105 <0 90 4>,
106 <0 91 4>;
107 clocks = <&sys_pll>;
108 clock-names = "apb_pclk";
109 };
111 timer {
112 compatible = "arm,armv7-timer";
113 interrupts = <1 13 0xf08>,
114 <1 14 0xf08>,
115 <1 11 0xf08>,
116 <1 10 0xf08>;
117 };
119 pmu {
120 compatible = "arm,cortex-a15-pmu";
121 interrupts = <0 68 4>,
122 <0 69 4>;
123 };
125 dcc {
126 compatible = "arm,vexpress,config-bus";
127 arm,vexpress,config-bridge = <&v2m_sysreg>;
129 oscclk0 {
130 /* CPU PLL reference clock */
131 compatible = "arm,vexpress-osc";
132 arm,vexpress-sysreg,func = <1 0>;
133 freq-range = <50000000 60000000>;
134 #clock-cells = <0>;
135 clock-output-names = "oscclk0";
136 };
138 oscclk4 {
139 /* Multiplexed AXI master clock */
140 compatible = "arm,vexpress-osc";
141 arm,vexpress-sysreg,func = <1 4>;
142 freq-range = <20000000 40000000>;
143 #clock-cells = <0>;
144 clock-output-names = "oscclk4";
145 };
147 hdlcd_clk: oscclk5 {
148 /* HDLCD PLL reference clock */
149 compatible = "arm,vexpress-osc";
150 arm,vexpress-sysreg,func = <1 5>;
151 freq-range = <23750000 165000000>;
152 #clock-cells = <0>;
153 clock-output-names = "oscclk5";
154 };
156 smbclk: oscclk6 {
157 /* SMB clock */
158 compatible = "arm,vexpress-osc";
159 arm,vexpress-sysreg,func = <1 6>;
160 freq-range = <20000000 50000000>;
161 #clock-cells = <0>;
162 clock-output-names = "oscclk6";
163 };
165 sys_pll: oscclk7 {
166 /* SYS PLL reference clock */
167 compatible = "arm,vexpress-osc";
168 arm,vexpress-sysreg,func = <1 7>;
169 freq-range = <20000000 60000000>;
170 #clock-cells = <0>;
171 clock-output-names = "oscclk7";
172 };
174 oscclk8 {
175 /* DDR2 PLL reference clock */
176 compatible = "arm,vexpress-osc";
177 arm,vexpress-sysreg,func = <1 8>;
178 freq-range = <40000000 40000000>;
179 #clock-cells = <0>;
180 clock-output-names = "oscclk8";
181 };
183 volt-cores {
184 /* CPU core voltage */
185 compatible = "arm,vexpress-volt";
186 arm,vexpress-sysreg,func = <2 0>;
187 regulator-name = "Cores";
188 regulator-min-microvolt = <800000>;
189 regulator-max-microvolt = <1050000>;
190 regulator-always-on;
191 label = "Cores";
192 };
194 amp-cores {
195 /* Total current for the two cores */
196 compatible = "arm,vexpress-amp";
197 arm,vexpress-sysreg,func = <3 0>;
198 label = "Cores";
199 };
201 temp-dcc {
202 /* DCC internal temperature */
203 compatible = "arm,vexpress-temp";
204 arm,vexpress-sysreg,func = <4 0>;
205 label = "DCC";
206 };
208 power-cores {
209 /* Total power */
210 compatible = "arm,vexpress-power";
211 arm,vexpress-sysreg,func = <12 0>;
212 label = "Cores";
213 };
215 energy {
216 /* Total energy */
217 compatible = "arm,vexpress-energy";
218 arm,vexpress-sysreg,func = <13 0>;
219 label = "Cores";
220 };
221 };
223 smb@08000000 {
224 compatible = "simple-bus";
226 #address-cells = <2>;
227 #size-cells = <1>;
228 ranges = <0 0 0 0x08000000 0x04000000>,
229 <1 0 0 0x14000000 0x04000000>,
230 <2 0 0 0x18000000 0x04000000>,
231 <3 0 0 0x1c000000 0x04000000>,
232 <4 0 0 0x0c000000 0x04000000>,
233 <5 0 0 0x10000000 0x04000000>;
235 #interrupt-cells = <1>;
236 interrupt-map-mask = <0 0 63>;
237 interrupt-map = <0 0 0 &gic 0 0 4>,
238 <0 0 1 &gic 0 1 4>,
239 <0 0 2 &gic 0 2 4>,
240 <0 0 3 &gic 0 3 4>,
241 <0 0 4 &gic 0 4 4>,
242 <0 0 5 &gic 0 5 4>,
243 <0 0 6 &gic 0 6 4>,
244 <0 0 7 &gic 0 7 4>,
245 <0 0 8 &gic 0 8 4>,
246 <0 0 9 &gic 0 9 4>,
247 <0 0 10 &gic 0 10 4>,
248 <0 0 11 &gic 0 11 4>,
249 <0 0 12 &gic 0 12 4>,
250 <0 0 13 &gic 0 13 4>,
251 <0 0 14 &gic 0 14 4>,
252 <0 0 15 &gic 0 15 4>,
253 <0 0 16 &gic 0 16 4>,
254 <0 0 17 &gic 0 17 4>,
255 <0 0 18 &gic 0 18 4>,
256 <0 0 19 &gic 0 19 4>,
257 <0 0 20 &gic 0 20 4>,
258 <0 0 21 &gic 0 21 4>,
259 <0 0 22 &gic 0 22 4>,
260 <0 0 23 &gic 0 23 4>,
261 <0 0 24 &gic 0 24 4>,
262 <0 0 25 &gic 0 25 4>,
263 <0 0 26 &gic 0 26 4>,
264 <0 0 27 &gic 0 27 4>,
265 <0 0 28 &gic 0 28 4>,
266 <0 0 29 &gic 0 29 4>,
267 <0 0 30 &gic 0 30 4>,
268 <0 0 31 &gic 0 31 4>,
269 <0 0 32 &gic 0 32 4>,
270 <0 0 33 &gic 0 33 4>,
271 <0 0 34 &gic 0 34 4>,
272 <0 0 35 &gic 0 35 4>,
273 <0 0 36 &gic 0 36 4>,
274 <0 0 37 &gic 0 37 4>,
275 <0 0 38 &gic 0 38 4>,
276 <0 0 39 &gic 0 39 4>,
277 <0 0 40 &gic 0 40 4>,
278 <0 0 41 &gic 0 41 4>,
279 <0 0 42 &gic 0 42 4>;
281 /include/ "vexpress-v2m-rs1.dtsi"
282 };
284 site2: hsb@40000000 {
285 compatible = "simple-bus";
286 #address-cells = <1>;
287 #size-cells = <1>;
288 ranges = <0 0 0x40000000 0x3fef0000>;
289 #interrupt-cells = <1>;
290 interrupt-map-mask = <0 3>;
291 interrupt-map = <0 0 &gic 0 36 4>,
292 <0 1 &gic 0 37 4>,
293 <0 2 &gic 0 38 4>,
294 <0 3 &gic 0 39 4>;
295 };
296 };