arch/arm/boot/dts/vf610-zii-dev-rev-b.dts

   1 /*
   2  * Copyright (C) 2015, 2016 Zodiac Inflight Innovations
   3  *
   4  * Based on an original 'vf610-twr.dts' which is Copyright 2015,
   5  * Freescale Semiconductor, Inc.
   6  *
   7  * This file is dual-licensed: you can use it either under the terms
   8  * of the GPL or the X11 license, at your option. Note that this dual
   9  * licensing only applies to this file, and not this project as a
  10  * whole.
  11  *
  12  *  a) This file is free software; you can redistribute it and/or
  13  *     modify it under the terms of the GNU General Public License
  14  *     version 2 as published by the Free Software Foundation.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 /dts-v1/;
  46 #include "vf610-zii-dev.dtsi"
  47
  48 / {
  49         model = "ZII VF610 Development Board, Rev B";
  50         compatible = "zii,vf610dev-b", "zii,vf610dev", "fsl,vf610";
  51
  52         mdio-mux {
  53                 compatible = "mdio-mux-gpio";
  54                 pinctrl-0 = <&pinctrl_mdio_mux>;
  55                 pinctrl-names = "default";
  56                 gpios = <&gpio0 8  GPIO_ACTIVE_HIGH
  57                          &gpio0 9  GPIO_ACTIVE_HIGH
  58                          &gpio0 24 GPIO_ACTIVE_HIGH
  59                          &gpio0 25 GPIO_ACTIVE_HIGH>;
  60                 mdio-parent-bus = <&mdio1>;
  61                 #address-cells = <1>;
  62                 #size-cells = <0>;
  63
  64                 mdio_mux_1: mdio@1 {
  65                         reg = <1>;
  66                         #address-cells = <1>;
  67                         #size-cells = <0>;
  68
  69                         switch0: switch@0 {
  70                                 compatible = "marvell,mv88e6085";
  71                                 pinctrl-0 = <&pinctrl_gpio_switch0>;
  72                                 pinctrl-names = "default";
  73                                 #address-cells = <1>;
  74                                 #size-cells = <0>;
  75                                 reg = <0>;
  76                                 dsa,member = <0 0>;
  77                                 interrupt-parent = <&gpio0>;
  78                                 interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
  79                                 interrupt-controller;
  80                                 #interrupt-cells = <2>;
  81
  82                                 ports {
  83                                         #address-cells = <1>;
  84                                         #size-cells = <0>;
  85
  86                                         port@0 {
  87                                                 reg = <0>;
  88                                                 label = "lan0";
  89                                                 phy-handle = <&switch0phy0>;
  90                                         };
  91
  92                                         port@1 {
  93                                                 reg = <1>;
  94                                                 label = "lan1";
  95                                                 phy-handle = <&switch0phy1>;
  96                                         };
  97
  98                                         port@2 {
  99                                                 reg = <2>;
 100                                                 label = "lan2";
 101                                                 phy-handle = <&switch0phy2>;
 102                                         };
 103
 104                                         switch0port5: port@5 {
 105                                                 reg = <5>;
 106                                                 label = "dsa";
 107                                                 phy-mode = "rgmii-txid";
 108                                                 link = <&switch1port6
 109                                                         &switch2port9>;
 110                                                 fixed-link {
 111                                                         speed = <1000>;
 112                                                         full-duplex;
 113                                                 };
 114                                         };
 115
 116                                         port@6 {
 117                                                 reg = <6>;
 118                                                 label = "cpu";
 119                                                 ethernet = <&fec1>;
 120
 121                                                 fixed-link {
 122                                                         speed = <100>;
 123                                                         full-duplex;
 124                                                 };
 125                                         };
 126                                 };
 127                                 mdio {
 128                                         #address-cells = <1>;
 129                                         #size-cells = <0>;
 130                                         switch0phy0: switch0phy0@0 {
 131                                                 reg = <0>;
 132                                                 interrupt-parent = <&switch0>;
 133                                                 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
 134                                         };
 135                                         switch0phy1: switch1phy0@1 {
 136                                                 reg = <1>;
 137                                                 interrupt-parent = <&switch0>;
 138                                                 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
 139                                         };
 140                                         switch0phy2: switch1phy0@2 {
 141                                                 reg = <2>;
 142                                                 interrupt-parent = <&switch0>;
 143                                                 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
 144                                         };
 145                                 };
 146                         };
 147                 };
 148
 149                 mdio_mux_2: mdio@2 {
 150                         reg = <2>;
 151                         #address-cells = <1>;
 152                         #size-cells = <0>;
 153
 154                         switch1: switch@0 {
 155                                 compatible = "marvell,mv88e6085";
 156                                 pinctrl-0 = <&pinctrl_gpio_switch1>;
 157                                 pinctrl-names = "default";
 158                                 #address-cells = <1>;
 159                                 #size-cells = <0>;
 160                                 reg = <0>;
 161                                 dsa,member = <0 1>;
 162                                 interrupt-parent = <&gpio0>;
 163                                 interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
 164                                 interrupt-controller;
 165                                 #interrupt-cells = <2>;
 166
 167                                 ports {
 168                                         #address-cells = <1>;
 169                                         #size-cells = <0>;
 170
 171                                         port@0 {
 172                                                 reg = <0>;
 173                                                 label = "lan3";
 174                                                 phy-handle = <&switch1phy0>;
 175                                         };
 176
 177                                         port@1 {
 178                                                 reg = <1>;
 179                                                 label = "lan4";
 180                                                 phy-handle = <&switch1phy1>;
 181                                         };
 182
 183                                         port@2 {
 184                                                 reg = <2>;
 185                                                 label = "lan5";
 186                                                 phy-handle = <&switch1phy2>;
 187                                         };
 188
 189                                         switch1port5: port@5 {
 190                                                 reg = <5>;
 191                                                 label = "dsa";
 192                                                 link = <&switch2port9>;
 193                                                 phy-mode = "rgmii-txid";
 194
 195                                                 fixed-link {
 196                                                         speed = <1000>;
 197                                                         full-duplex;
 198                                                 };
 199                                         };
 200
 201                                         switch1port6: port@6 {
 202                                                 reg = <6>;
 203                                                 label = "dsa";
 204                                                 phy-mode = "rgmii-txid";
 205                                                 link = <&switch0port5>;
 206                                                 fixed-link {
 207                                                         speed = <1000>;
 208                                                         full-duplex;
 209                                                 };
 210                                         };
 211                                 };
 212                                 mdio {
 213                                         #address-cells = <1>;
 214                                         #size-cells = <0>;
 215
 216                                         switch1phy0: switch1phy0@0 {
 217                                                 reg = <0>;
 218                                                 interrupt-parent = <&switch1>;
 219                                                 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
 220                                         };
 221
 222                                         switch1phy1: switch1phy0@1 {
 223                                                 reg = <1>;
 224                                                 interrupt-parent = <&switch1>;
 225                                                 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
 226                                         };
 227
 228                                         switch1phy2: switch1phy0@2 {
 229                                                 reg = <2>;
 230                                                 interrupt-parent = <&switch1>;
 231                                                 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
 232                                         };
 233                                 };
 234                         };
 235                 };
 236
 237                 mdio_mux_4: mdio@4 {
 238                         #address-cells = <1>;
 239                         #size-cells = <0>;
 240                         reg = <4>;
 241
 242                         switch2: switch2@0 {
 243                                 compatible = "marvell,mv88e6085";
 244                                 #address-cells = <1>;
 245                                 #size-cells = <0>;
 246                                 reg = <0>;
 247                                 dsa,member = <0 2>;
 248
 249                                 ports {
 250                                         #address-cells = <1>;
 251                                         #size-cells = <0>;
 252
 253                                         port@0 {
 254                                                 reg = <0>;
 255                                                 label = "lan6";
 256                                         };
 257
 258                                         port@1 {
 259                                                 reg = <1>;
 260                                                 label = "lan7";
 261                                         };
 262
 263                                         port@2 {
 264                                                 reg = <2>;
 265                                                 label = "lan8";
 266                                         };
 267
 268                                         port@3 {
 269                                                 reg = <3>;
 270                                                 label = "optical3";
 271
 272                                                 fixed-link {
 273                                                         speed = <1000>;
 274                                                         full-duplex;
 275                                                         link-gpios = <&gpio6 2
 276                                                               GPIO_ACTIVE_HIGH>;
 277                                                 };
 278                                         };
 279
 280                                         port@4 {
 281                                                 reg = <4>;
 282                                                 label = "optical4";
 283
 284                                                 fixed-link {
 285                                                         speed = <1000>;
 286                                                         full-duplex;
 287                                                         link-gpios = <&gpio6 3
 288                                                               GPIO_ACTIVE_HIGH>;
 289                                                 };
 290                                         };
 291
 292                                         switch2port9: port@9 {
 293                                                 reg = <9>;
 294                                                 label = "dsa";
 295                                                 phy-mode = "rgmii-txid";
 296                                                 link = <&switch1port5
 297                                                         &switch0port5>;
 298
 299                                                 fixed-link {
 300                                                         speed = <1000>;
 301                                                         full-duplex;
 302                                                 };
 303                                         };
 304                                 };
 305                         };
 306                 };
 307
 308                 mdio_mux_8: mdio@8 {
 309                         reg = <8>;
 310                         #address-cells = <1>;
 311                         #size-cells = <0>;
 312                 };
 313         };
 314
 315         spi0 {
 316                 compatible = "spi-gpio";
 317                 pinctrl-0 = <&pinctrl_gpio_spi0>;
 318                 pinctrl-names = "default";
 319                 #address-cells = <1>;
 320                 #size-cells = <0>;
 321                 gpio-sck  = <&gpio1 12 GPIO_ACTIVE_HIGH>;
 322                 gpio-mosi = <&gpio1 11 GPIO_ACTIVE_HIGH>;
 323                 gpio-miso = <&gpio1 10 GPIO_ACTIVE_HIGH>;
 324                 cs-gpios  = <&gpio1  9 GPIO_ACTIVE_HIGH
 325                              &gpio1  8 GPIO_ACTIVE_HIGH>;
 326                 num-chipselects = <2>;
 327
 328                 m25p128@0 {
 329                         compatible = "m25p128", "jedec,spi-nor";
 330                         #address-cells = <1>;
 331                         #size-cells = <1>;
 332                         reg = <0>;
 333                         spi-max-frequency = <1000000>;
 334                 };
 335
 336                 at93c46d@1 {
 337                         compatible = "atmel,at93c46d";
 338                         pinctrl-0 = <&pinctrl_gpio_e6185_eeprom_sel>;
 339                         pinctrl-names = "default";
 340                         #address-cells = <0>;
 341                         #size-cells = <0>;
 342                         reg = <1>;
 343                         spi-max-frequency = <500000>;
 344                         spi-cs-high;
 345                         data-size = <16>;
 346                         select-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;
 347                 };
 348         };
 349 };
 350
 351 &i2c0 {
 352         clock-frequency = <100000>;
 353         pinctrl-names = "default";
 354         pinctrl-0 = <&pinctrl_i2c0>;
 355         status = "okay";
 356
 357         gpio5: pca9554@20 {
 358                 compatible = "nxp,pca9554";
 359                 reg = <0x20>;
 360                 gpio-controller;
 361                 #gpio-cells = <2>;
 362
 363         };
 364
 365         gpio6: pca9554@22 {
 366                 compatible = "nxp,pca9554";
 367                 pinctrl-names = "default";
 368                 pinctrl-0 = <&pinctrl_pca9554_22>;
 369                 reg = <0x22>;
 370                 gpio-controller;
 371                 #gpio-cells = <2>;
 372                 interrupt-parent = <&gpio2>;
 373                 interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
 374         };
 375 };
 376
 377 &i2c2 {
 378         clock-frequency = <100000>;
 379         pinctrl-names = "default";
 380         pinctrl-0 = <&pinctrl_i2c2>;
 381         status = "okay";
 382
 383         tca9548@70 {
 384                 compatible = "nxp,pca9548";
 385                 pinctrl-0 = <&pinctrl_i2c_mux_reset>;
 386                 pinctrl-names = "default";
 387                 #address-cells = <1>;
 388                 #size-cells = <0>;
 389                 reg = <0x70>;
 390                 reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
 391
 392                 i2c@0 {
 393                         #address-cells = <1>;
 394                         #size-cells = <0>;
 395                         reg = <0>;
 396
 397                         sfp1: at24c04@50 {
 398                                 compatible = "atmel,24c02";
 399                                 reg = <0x50>;
 400                         };
 401                 };
 402
 403                 i2c@1 {
 404                         #address-cells = <1>;
 405                         #size-cells = <0>;
 406                         reg = <1>;
 407
 408                         sfp2: at24c04@50 {
 409                                 compatible = "atmel,24c02";
 410                                 reg = <0x50>;
 411                         };
 412                 };
 413
 414                 i2c@2 {
 415                         #address-cells = <1>;
 416                         #size-cells = <0>;
 417                         reg = <2>;
 418
 419                         sfp3: at24c04@50 {
 420                                 compatible = "atmel,24c02";
 421                                 reg = <0x50>;
 422                         };
 423                 };
 424
 425                 i2c@3 {
 426                         #address-cells = <1>;
 427                         #size-cells = <0>;
 428                         reg = <3>;
 429
 430                         sfp4: at24c04@50 {
 431                                 compatible = "atmel,24c02";
 432                                 reg = <0x50>;
 433                         };
 434                 };
 435
 436                 i2c@4 {
 437                         #address-cells = <1>;
 438                         #size-cells = <0>;
 439                         reg = <4>;
 440                 };
 441         };
 442 };
 443
 444
 445 &iomuxc {
 446         pinctrl_gpio_e6185_eeprom_sel: pinctrl-gpio-e6185-eeprom-spi0 {
 447                 fsl,pins = <
 448                         VF610_PAD_PTE27__GPIO_132       0x33e2
 449                 >;
 450         };
 451
 452         pinctrl_gpio_spi0: pinctrl-gpio-spi0 {
 453                 fsl,pins = <
 454                         VF610_PAD_PTB22__GPIO_44        0x33e2
 455                         VF610_PAD_PTB21__GPIO_43        0x33e2
 456                         VF610_PAD_PTB20__GPIO_42        0x33e1
 457                         VF610_PAD_PTB19__GPIO_41        0x33e2
 458                         VF610_PAD_PTB18__GPIO_40        0x33e2
 459                 >;
 460         };
 461
 462         pinctrl_gpio_switch0: pinctrl-gpio-switch0 {
 463                 fsl,pins = <
 464                         VF610_PAD_PTB5__GPIO_27         0x219d
 465                 >;
 466         };
 467
 468         pinctrl_gpio_switch1: pinctrl-gpio-switch1 {
 469                 fsl,pins = <
 470                         VF610_PAD_PTB4__GPIO_26         0x219d
 471                 >;
 472         };
 473
 474         pinctrl_mdio_mux: pinctrl-mdio-mux {
 475                 fsl,pins = <
 476                         VF610_PAD_PTA18__GPIO_8         0x31c2
 477                         VF610_PAD_PTA19__GPIO_9         0x31c2
 478                         VF610_PAD_PTB2__GPIO_24         0x31c2
 479                         VF610_PAD_PTB3__GPIO_25         0x31c2
 480                 >;
 481         };
 482
 483         pinctrl_pca9554_22: pinctrl-pca95540-22 {
 484                 fsl,pins = <
 485                         VF610_PAD_PTB28__GPIO_98        0x219d
 486                 >;
 487         };
 488 };