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x86/mm/pat: Don't report PAT on CPUs that don't support it
[linux/fpc-iii.git] / arch / arm / kvm / coproc.c
blobc3ed6bd5ddf35aeb558f1129f06fff333dc6552c
1 /*
2 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
3 * Authors: Rusty Russell <rusty@rustcorp.com.au>
4 * Christoffer Dall <c.dall@virtualopensystems.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License, version 2, as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
18 */
19
20 #include <linux/bsearch.h>
21 #include <linux/mm.h>
22 #include <linux/kvm_host.h>
23 #include <linux/uaccess.h>
24 #include <asm/kvm_arm.h>
25 #include <asm/kvm_host.h>
26 #include <asm/kvm_emulate.h>
27 #include <asm/kvm_coproc.h>
28 #include <asm/kvm_mmu.h>
29 #include <asm/cacheflush.h>
30 #include <asm/cputype.h>
31 #include <trace/events/kvm.h>
32 #include <asm/vfp.h>
33 #include "../vfp/vfpinstr.h"
34
35 #include "trace.h"
36 #include "coproc.h"
37
38
39 /******************************************************************************
40 * Co-processor emulation
41 *****************************************************************************/
42
43 /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
44 static u32 cache_levels;
45
46 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
47 #define CSSELR_MAX 12
48
49 /*
50 * kvm_vcpu_arch.cp15 holds cp15 registers as an array of u32, but some
51 * of cp15 registers can be viewed either as couple of two u32 registers
52 * or one u64 register. Current u64 register encoding is that least
53 * significant u32 word is followed by most significant u32 word.
54 */
55 static inline void vcpu_cp15_reg64_set(struct kvm_vcpu *vcpu,
56 const struct coproc_reg *r,
57 u64 val)
58 {
59 vcpu_cp15(vcpu, r->reg) = val & 0xffffffff;
60 vcpu_cp15(vcpu, r->reg + 1) = val >> 32;
61 }
62
63 static inline u64 vcpu_cp15_reg64_get(struct kvm_vcpu *vcpu,
64 const struct coproc_reg *r)
65 {
66 u64 val;
67
68 val = vcpu_cp15(vcpu, r->reg + 1);
69 val = val << 32;
70 val = val | vcpu_cp15(vcpu, r->reg);
71 return val;
72 }
73
74 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu, struct kvm_run *run)
75 {
76 kvm_inject_undefined(vcpu);
77 return 1;
78 }
79
80 int kvm_handle_cp_0_13_access(struct kvm_vcpu *vcpu, struct kvm_run *run)
81 {
82 /*
83 * We can get here, if the host has been built without VFPv3 support,
84 * but the guest attempted a floating point operation.
85 */
86 kvm_inject_undefined(vcpu);
87 return 1;
88 }
89
90 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run)
91 {
92 kvm_inject_undefined(vcpu);
93 return 1;
94 }
95
96 static void reset_mpidr(struct kvm_vcpu *vcpu, const struct coproc_reg *r)
97 {
98 /*
99 * Compute guest MPIDR. We build a virtual cluster out of the
100 * vcpu_id, but we read the 'U' bit from the underlying
101 * hardware directly.
102 */
103 vcpu_cp15(vcpu, c0_MPIDR) = ((read_cpuid_mpidr() & MPIDR_SMP_BITMASK) |
104 ((vcpu->vcpu_id >> 2) << MPIDR_LEVEL_BITS) |
105 (vcpu->vcpu_id & 3));
106 }
107
108 /* TRM entries A7:4.3.31 A15:4.3.28 - RO WI */
109 static bool access_actlr(struct kvm_vcpu *vcpu,
110 const struct coproc_params *p,
111 const struct coproc_reg *r)
112 {
113 if (p->is_write)
114 return ignore_write(vcpu, p);
115
116 *vcpu_reg(vcpu, p->Rt1) = vcpu_cp15(vcpu, c1_ACTLR);
117 return true;
118 }
119
120 /* TRM entries A7:4.3.56, A15:4.3.60 - R/O. */
121 static bool access_cbar(struct kvm_vcpu *vcpu,
122 const struct coproc_params *p,
123 const struct coproc_reg *r)
124 {
125 if (p->is_write)
126 return write_to_read_only(vcpu, p);
127 return read_zero(vcpu, p);
128 }
129
130 /* TRM entries A7:4.3.49, A15:4.3.48 - R/O WI */
131 static bool access_l2ctlr(struct kvm_vcpu *vcpu,
132 const struct coproc_params *p,
133 const struct coproc_reg *r)
134 {
135 if (p->is_write)
136 return ignore_write(vcpu, p);
137
138 *vcpu_reg(vcpu, p->Rt1) = vcpu_cp15(vcpu, c9_L2CTLR);
139 return true;
140 }
141
142 static void reset_l2ctlr(struct kvm_vcpu *vcpu, const struct coproc_reg *r)
143 {
144 u32 l2ctlr, ncores;
145
146 asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr));
147 l2ctlr &= ~(3 << 24);
148 ncores = atomic_read(&vcpu->kvm->online_vcpus) - 1;
149 /* How many cores in the current cluster and the next ones */
150 ncores -= (vcpu->vcpu_id & ~3);
151 /* Cap it to the maximum number of cores in a single cluster */
152 ncores = min(ncores, 3U);
153 l2ctlr |= (ncores & 3) << 24;
154
155 vcpu_cp15(vcpu, c9_L2CTLR) = l2ctlr;
156 }
157
158 static void reset_actlr(struct kvm_vcpu *vcpu, const struct coproc_reg *r)
159 {
160 u32 actlr;
161
162 /* ACTLR contains SMP bit: make sure you create all cpus first! */
163 asm volatile("mrc p15, 0, %0, c1, c0, 1\n" : "=r" (actlr));
164 /* Make the SMP bit consistent with the guest configuration */
165 if (atomic_read(&vcpu->kvm->online_vcpus) > 1)
166 actlr |= 1U << 6;
167 else
168 actlr &= ~(1U << 6);
169
170 vcpu_cp15(vcpu, c1_ACTLR) = actlr;
171 }
172
173 /*
174 * TRM entries: A7:4.3.50, A15:4.3.49
175 * R/O WI (even if NSACR.NS_L2ERR, a write of 1 is ignored).
176 */
177 static bool access_l2ectlr(struct kvm_vcpu *vcpu,
178 const struct coproc_params *p,
179 const struct coproc_reg *r)
180 {
181 if (p->is_write)
182 return ignore_write(vcpu, p);
183
184 *vcpu_reg(vcpu, p->Rt1) = 0;
185 return true;
186 }
187
188 /*
189 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
190 */
191 static bool access_dcsw(struct kvm_vcpu *vcpu,
192 const struct coproc_params *p,
193 const struct coproc_reg *r)
194 {
195 if (!p->is_write)
196 return read_from_write_only(vcpu, p);
197
198 kvm_set_way_flush(vcpu);
199 return true;
200 }
201
202 /*
203 * Generic accessor for VM registers. Only called as long as HCR_TVM
204 * is set. If the guest enables the MMU, we stop trapping the VM
205 * sys_regs and leave it in complete control of the caches.
206 *
207 * Used by the cpu-specific code.
208 */
209 bool access_vm_reg(struct kvm_vcpu *vcpu,
210 const struct coproc_params *p,
211 const struct coproc_reg *r)
212 {
213 bool was_enabled = vcpu_has_cache_enabled(vcpu);
214
215 BUG_ON(!p->is_write);
216
217 vcpu_cp15(vcpu, r->reg) = *vcpu_reg(vcpu, p->Rt1);
218 if (p->is_64bit)
219 vcpu_cp15(vcpu, r->reg + 1) = *vcpu_reg(vcpu, p->Rt2);
220
221 kvm_toggle_cache(vcpu, was_enabled);
222 return true;
223 }
224
225 static bool access_gic_sgi(struct kvm_vcpu *vcpu,
226 const struct coproc_params *p,
227 const struct coproc_reg *r)
228 {
229 u64 reg;
230
231 if (!p->is_write)
232 return read_from_write_only(vcpu, p);
233
234 reg = (u64)*vcpu_reg(vcpu, p->Rt2) << 32;
235 reg |= *vcpu_reg(vcpu, p->Rt1) ;
236
237 vgic_v3_dispatch_sgi(vcpu, reg);
238
239 return true;
240 }
241
242 static bool access_gic_sre(struct kvm_vcpu *vcpu,
243 const struct coproc_params *p,
244 const struct coproc_reg *r)
245 {
246 if (p->is_write)
247 return ignore_write(vcpu, p);
248
249 *vcpu_reg(vcpu, p->Rt1) = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre;
250
251 return true;
252 }
253
254 /*
255 * We could trap ID_DFR0 and tell the guest we don't support performance
256 * monitoring. Unfortunately the patch to make the kernel check ID_DFR0 was
257 * NAKed, so it will read the PMCR anyway.
258 *
259 * Therefore we tell the guest we have 0 counters. Unfortunately, we
260 * must always support PMCCNTR (the cycle counter): we just RAZ/WI for
261 * all PM registers, which doesn't crash the guest kernel at least.
262 */
263 static bool pm_fake(struct kvm_vcpu *vcpu,
264 const struct coproc_params *p,
265 const struct coproc_reg *r)
266 {
267 if (p->is_write)
268 return ignore_write(vcpu, p);
269 else
270 return read_zero(vcpu, p);
271 }
272
273 #define access_pmcr pm_fake
274 #define access_pmcntenset pm_fake
275 #define access_pmcntenclr pm_fake
276 #define access_pmovsr pm_fake
277 #define access_pmselr pm_fake
278 #define access_pmceid0 pm_fake
279 #define access_pmceid1 pm_fake
280 #define access_pmccntr pm_fake
281 #define access_pmxevtyper pm_fake
282 #define access_pmxevcntr pm_fake
283 #define access_pmuserenr pm_fake
284 #define access_pmintenset pm_fake
285 #define access_pmintenclr pm_fake
286
287 /* Architected CP15 registers.
288 * CRn denotes the primary register number, but is copied to the CRm in the
289 * user space API for 64-bit register access in line with the terminology used
290 * in the ARM ARM.
291 * Important: Must be sorted ascending by CRn, CRM, Op1, Op2 and with 64-bit
292 * registers preceding 32-bit ones.
293 */
294 static const struct coproc_reg cp15_regs[] = {
295 /* MPIDR: we use VMPIDR for guest access. */
296 { CRn( 0), CRm( 0), Op1( 0), Op2( 5), is32,
297 NULL, reset_mpidr, c0_MPIDR },
298
299 /* CSSELR: swapped by interrupt.S. */
300 { CRn( 0), CRm( 0), Op1( 2), Op2( 0), is32,
301 NULL, reset_unknown, c0_CSSELR },
302
303 /* ACTLR: trapped by HCR.TAC bit. */
304 { CRn( 1), CRm( 0), Op1( 0), Op2( 1), is32,
305 access_actlr, reset_actlr, c1_ACTLR },
306
307 /* CPACR: swapped by interrupt.S. */
308 { CRn( 1), CRm( 0), Op1( 0), Op2( 2), is32,
309 NULL, reset_val, c1_CPACR, 0x00000000 },
310
311 /* TTBR0/TTBR1/TTBCR: swapped by interrupt.S. */
312 { CRm64( 2), Op1( 0), is64, access_vm_reg, reset_unknown64, c2_TTBR0 },
313 { CRn(2), CRm( 0), Op1( 0), Op2( 0), is32,
314 access_vm_reg, reset_unknown, c2_TTBR0 },
315 { CRn(2), CRm( 0), Op1( 0), Op2( 1), is32,
316 access_vm_reg, reset_unknown, c2_TTBR1 },
317 { CRn( 2), CRm( 0), Op1( 0), Op2( 2), is32,
318 access_vm_reg, reset_val, c2_TTBCR, 0x00000000 },
319 { CRm64( 2), Op1( 1), is64, access_vm_reg, reset_unknown64, c2_TTBR1 },
320
321
322 /* DACR: swapped by interrupt.S. */
323 { CRn( 3), CRm( 0), Op1( 0), Op2( 0), is32,
324 access_vm_reg, reset_unknown, c3_DACR },
325
326 /* DFSR/IFSR/ADFSR/AIFSR: swapped by interrupt.S. */
327 { CRn( 5), CRm( 0), Op1( 0), Op2( 0), is32,
328 access_vm_reg, reset_unknown, c5_DFSR },
329 { CRn( 5), CRm( 0), Op1( 0), Op2( 1), is32,
330 access_vm_reg, reset_unknown, c5_IFSR },
331 { CRn( 5), CRm( 1), Op1( 0), Op2( 0), is32,
332 access_vm_reg, reset_unknown, c5_ADFSR },
333 { CRn( 5), CRm( 1), Op1( 0), Op2( 1), is32,
334 access_vm_reg, reset_unknown, c5_AIFSR },
335
336 /* DFAR/IFAR: swapped by interrupt.S. */
337 { CRn( 6), CRm( 0), Op1( 0), Op2( 0), is32,
338 access_vm_reg, reset_unknown, c6_DFAR },
339 { CRn( 6), CRm( 0), Op1( 0), Op2( 2), is32,
340 access_vm_reg, reset_unknown, c6_IFAR },
341
342 /* PAR swapped by interrupt.S */
343 { CRm64( 7), Op1( 0), is64, NULL, reset_unknown64, c7_PAR },
344
345 /*
346 * DC{C,I,CI}SW operations:
347 */
348 { CRn( 7), CRm( 6), Op1( 0), Op2( 2), is32, access_dcsw},
349 { CRn( 7), CRm(10), Op1( 0), Op2( 2), is32, access_dcsw},
350 { CRn( 7), CRm(14), Op1( 0), Op2( 2), is32, access_dcsw},
351 /*
352 * L2CTLR access (guest wants to know #CPUs).
353 */
354 { CRn( 9), CRm( 0), Op1( 1), Op2( 2), is32,
355 access_l2ctlr, reset_l2ctlr, c9_L2CTLR },
356 { CRn( 9), CRm( 0), Op1( 1), Op2( 3), is32, access_l2ectlr},
357
358 /*
359 * Dummy performance monitor implementation.
360 */
361 { CRn( 9), CRm(12), Op1( 0), Op2( 0), is32, access_pmcr},
362 { CRn( 9), CRm(12), Op1( 0), Op2( 1), is32, access_pmcntenset},
363 { CRn( 9), CRm(12), Op1( 0), Op2( 2), is32, access_pmcntenclr},
364 { CRn( 9), CRm(12), Op1( 0), Op2( 3), is32, access_pmovsr},
365 { CRn( 9), CRm(12), Op1( 0), Op2( 5), is32, access_pmselr},
366 { CRn( 9), CRm(12), Op1( 0), Op2( 6), is32, access_pmceid0},
367 { CRn( 9), CRm(12), Op1( 0), Op2( 7), is32, access_pmceid1},
368 { CRn( 9), CRm(13), Op1( 0), Op2( 0), is32, access_pmccntr},
369 { CRn( 9), CRm(13), Op1( 0), Op2( 1), is32, access_pmxevtyper},
370 { CRn( 9), CRm(13), Op1( 0), Op2( 2), is32, access_pmxevcntr},
371 { CRn( 9), CRm(14), Op1( 0), Op2( 0), is32, access_pmuserenr},
372 { CRn( 9), CRm(14), Op1( 0), Op2( 1), is32, access_pmintenset},
373 { CRn( 9), CRm(14), Op1( 0), Op2( 2), is32, access_pmintenclr},
374
375 /* PRRR/NMRR (aka MAIR0/MAIR1): swapped by interrupt.S. */
376 { CRn(10), CRm( 2), Op1( 0), Op2( 0), is32,
377 access_vm_reg, reset_unknown, c10_PRRR},
378 { CRn(10), CRm( 2), Op1( 0), Op2( 1), is32,
379 access_vm_reg, reset_unknown, c10_NMRR},
380
381 /* AMAIR0/AMAIR1: swapped by interrupt.S. */
382 { CRn(10), CRm( 3), Op1( 0), Op2( 0), is32,
383 access_vm_reg, reset_unknown, c10_AMAIR0},
384 { CRn(10), CRm( 3), Op1( 0), Op2( 1), is32,
385 access_vm_reg, reset_unknown, c10_AMAIR1},
386
387 /* ICC_SGI1R */
388 { CRm64(12), Op1( 0), is64, access_gic_sgi},
389
390 /* VBAR: swapped by interrupt.S. */
391 { CRn(12), CRm( 0), Op1( 0), Op2( 0), is32,
392 NULL, reset_val, c12_VBAR, 0x00000000 },
393
394 /* ICC_SRE */
395 { CRn(12), CRm(12), Op1( 0), Op2(5), is32, access_gic_sre },
396
397 /* CONTEXTIDR/TPIDRURW/TPIDRURO/TPIDRPRW: swapped by interrupt.S. */
398 { CRn(13), CRm( 0), Op1( 0), Op2( 1), is32,
399 access_vm_reg, reset_val, c13_CID, 0x00000000 },
400 { CRn(13), CRm( 0), Op1( 0), Op2( 2), is32,
401 NULL, reset_unknown, c13_TID_URW },
402 { CRn(13), CRm( 0), Op1( 0), Op2( 3), is32,
403 NULL, reset_unknown, c13_TID_URO },
404 { CRn(13), CRm( 0), Op1( 0), Op2( 4), is32,
405 NULL, reset_unknown, c13_TID_PRIV },
406
407 /* CNTKCTL: swapped by interrupt.S. */
408 { CRn(14), CRm( 1), Op1( 0), Op2( 0), is32,
409 NULL, reset_val, c14_CNTKCTL, 0x00000000 },
410
411 /* The Configuration Base Address Register. */
412 { CRn(15), CRm( 0), Op1( 4), Op2( 0), is32, access_cbar},
413 };
414
415 static int check_reg_table(const struct coproc_reg *table, unsigned int n)
416 {
417 unsigned int i;
418
419 for (i = 1; i < n; i++) {
420 if (cmp_reg(&table[i-1], &table[i]) >= 0) {
421 kvm_err("reg table %p out of order (%d)\n", table, i - 1);
422 return 1;
423 }
424 }
425
426 return 0;
427 }
428
429 /* Target specific emulation tables */
430 static struct kvm_coproc_target_table *target_tables[KVM_ARM_NUM_TARGETS];
431
432 void kvm_register_target_coproc_table(struct kvm_coproc_target_table *table)
433 {
434 BUG_ON(check_reg_table(table->table, table->num));
435 target_tables[table->target] = table;
436 }
437
438 /* Get specific register table for this target. */
439 static const struct coproc_reg *get_target_table(unsigned target, size_t *num)
440 {
441 struct kvm_coproc_target_table *table;
442
443 table = target_tables[target];
444 *num = table->num;
445 return table->table;
446 }
447
448 #define reg_to_match_value(x) \
449 ({ \
450 unsigned long val; \
451 val = (x)->CRn << 11; \
452 val |= (x)->CRm << 7; \
453 val |= (x)->Op1 << 4; \
454 val |= (x)->Op2 << 1; \
455 val |= !(x)->is_64bit; \
456 val; \
457 })
458
459 static int match_reg(const void *key, const void *elt)
460 {
461 const unsigned long pval = (unsigned long)key;
462 const struct coproc_reg *r = elt;
463
464 return pval - reg_to_match_value(r);
465 }
466
467 static const struct coproc_reg *find_reg(const struct coproc_params *params,
468 const struct coproc_reg table[],
469 unsigned int num)
470 {
471 unsigned long pval = reg_to_match_value(params);
472
473 return bsearch((void *)pval, table, num, sizeof(table[0]), match_reg);
474 }
475
476 static int emulate_cp15(struct kvm_vcpu *vcpu,
477 const struct coproc_params *params)
478 {
479 size_t num;
480 const struct coproc_reg *table, *r;
481
482 trace_kvm_emulate_cp15_imp(params->Op1, params->Rt1, params->CRn,
483 params->CRm, params->Op2, params->is_write);
484
485 table = get_target_table(vcpu->arch.target, &num);
486
487 /* Search target-specific then generic table. */
488 r = find_reg(params, table, num);
489 if (!r)
490 r = find_reg(params, cp15_regs, ARRAY_SIZE(cp15_regs));
491
492 if (likely(r)) {
493 /* If we don't have an accessor, we should never get here! */
494 BUG_ON(!r->access);
495
496 if (likely(r->access(vcpu, params, r))) {
497 /* Skip instruction, since it was emulated */
498 kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
499 return 1;
500 }
501 /* If access function fails, it should complain. */
502 } else {
503 kvm_err("Unsupported guest CP15 access at: %08lx\n",
504 *vcpu_pc(vcpu));
505 print_cp_instr(params);
506 }
507 kvm_inject_undefined(vcpu);
508 return 1;
509 }
510
511 static struct coproc_params decode_64bit_hsr(struct kvm_vcpu *vcpu)
512 {
513 struct coproc_params params;
514
515 params.CRn = (kvm_vcpu_get_hsr(vcpu) >> 1) & 0xf;
516 params.Rt1 = (kvm_vcpu_get_hsr(vcpu) >> 5) & 0xf;
517 params.is_write = ((kvm_vcpu_get_hsr(vcpu) & 1) == 0);
518 params.is_64bit = true;
519
520 params.Op1 = (kvm_vcpu_get_hsr(vcpu) >> 16) & 0xf;
521 params.Op2 = 0;
522 params.Rt2 = (kvm_vcpu_get_hsr(vcpu) >> 10) & 0xf;
523 params.CRm = 0;
524
525 return params;
526 }
527
528 /**
529 * kvm_handle_cp15_64 -- handles a mrrc/mcrr trap on a guest CP15 access
530 * @vcpu: The VCPU pointer
531 * @run: The kvm_run struct
532 */
533 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
534 {
535 struct coproc_params params = decode_64bit_hsr(vcpu);
536
537 return emulate_cp15(vcpu, &params);
538 }
539
540 /**
541 * kvm_handle_cp14_64 -- handles a mrrc/mcrr trap on a guest CP14 access
542 * @vcpu: The VCPU pointer
543 * @run: The kvm_run struct
544 */
545 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
546 {
547 struct coproc_params params = decode_64bit_hsr(vcpu);
548
549 /* raz_wi cp14 */
550 pm_fake(vcpu, &params, NULL);
551
552 /* handled */
553 kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
554 return 1;
555 }
556
557 static void reset_coproc_regs(struct kvm_vcpu *vcpu,
558 const struct coproc_reg *table, size_t num)
559 {
560 unsigned long i;
561
562 for (i = 0; i < num; i++)
563 if (table[i].reset)
564 table[i].reset(vcpu, &table[i]);
565 }
566
567 static struct coproc_params decode_32bit_hsr(struct kvm_vcpu *vcpu)
568 {
569 struct coproc_params params;
570
571 params.CRm = (kvm_vcpu_get_hsr(vcpu) >> 1) & 0xf;
572 params.Rt1 = (kvm_vcpu_get_hsr(vcpu) >> 5) & 0xf;
573 params.is_write = ((kvm_vcpu_get_hsr(vcpu) & 1) == 0);
574 params.is_64bit = false;
575
576 params.CRn = (kvm_vcpu_get_hsr(vcpu) >> 10) & 0xf;
577 params.Op1 = (kvm_vcpu_get_hsr(vcpu) >> 14) & 0x7;
578 params.Op2 = (kvm_vcpu_get_hsr(vcpu) >> 17) & 0x7;
579 params.Rt2 = 0;
580
581 return params;
582 }
583
584 /**
585 * kvm_handle_cp15_32 -- handles a mrc/mcr trap on a guest CP15 access
586 * @vcpu: The VCPU pointer
587 * @run: The kvm_run struct
588 */
589 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
590 {
591 struct coproc_params params = decode_32bit_hsr(vcpu);
592 return emulate_cp15(vcpu, &params);
593 }
594
595 /**
596 * kvm_handle_cp14_32 -- handles a mrc/mcr trap on a guest CP14 access
597 * @vcpu: The VCPU pointer
598 * @run: The kvm_run struct
599 */
600 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
601 {
602 struct coproc_params params = decode_32bit_hsr(vcpu);
603
604 /* raz_wi cp14 */
605 pm_fake(vcpu, &params, NULL);
606
607 /* handled */
608 kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
609 return 1;
610 }
611
612 /******************************************************************************
613 * Userspace API
614 *****************************************************************************/
615
616 static bool index_to_params(u64 id, struct coproc_params *params)
617 {
618 switch (id & KVM_REG_SIZE_MASK) {
619 case KVM_REG_SIZE_U32:
620 /* Any unused index bits means it's not valid. */
621 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
622 | KVM_REG_ARM_COPROC_MASK
623 | KVM_REG_ARM_32_CRN_MASK
624 | KVM_REG_ARM_CRM_MASK
625 | KVM_REG_ARM_OPC1_MASK
626 | KVM_REG_ARM_32_OPC2_MASK))
627 return false;
628
629 params->is_64bit = false;
630 params->CRn = ((id & KVM_REG_ARM_32_CRN_MASK)
631 >> KVM_REG_ARM_32_CRN_SHIFT);
632 params->CRm = ((id & KVM_REG_ARM_CRM_MASK)
633 >> KVM_REG_ARM_CRM_SHIFT);
634 params->Op1 = ((id & KVM_REG_ARM_OPC1_MASK)
635 >> KVM_REG_ARM_OPC1_SHIFT);
636 params->Op2 = ((id & KVM_REG_ARM_32_OPC2_MASK)
637 >> KVM_REG_ARM_32_OPC2_SHIFT);
638 return true;
639 case KVM_REG_SIZE_U64:
640 /* Any unused index bits means it's not valid. */
641 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
642 | KVM_REG_ARM_COPROC_MASK
643 | KVM_REG_ARM_CRM_MASK
644 | KVM_REG_ARM_OPC1_MASK))
645 return false;
646 params->is_64bit = true;
647 /* CRm to CRn: see cp15_to_index for details */
648 params->CRn = ((id & KVM_REG_ARM_CRM_MASK)
649 >> KVM_REG_ARM_CRM_SHIFT);
650 params->Op1 = ((id & KVM_REG_ARM_OPC1_MASK)
651 >> KVM_REG_ARM_OPC1_SHIFT);
652 params->Op2 = 0;
653 params->CRm = 0;
654 return true;
655 default:
656 return false;
657 }
658 }
659
660 /* Decode an index value, and find the cp15 coproc_reg entry. */
661 static const struct coproc_reg *index_to_coproc_reg(struct kvm_vcpu *vcpu,
662 u64 id)
663 {
664 size_t num;
665 const struct coproc_reg *table, *r;
666 struct coproc_params params;
667
668 /* We only do cp15 for now. */
669 if ((id & KVM_REG_ARM_COPROC_MASK) >> KVM_REG_ARM_COPROC_SHIFT != 15)
670 return NULL;
671
672 if (!index_to_params(id, &params))
673 return NULL;
674
675 table = get_target_table(vcpu->arch.target, &num);
676 r = find_reg(&params, table, num);
677 if (!r)
678 r = find_reg(&params, cp15_regs, ARRAY_SIZE(cp15_regs));
679
680 /* Not saved in the cp15 array? */
681 if (r && !r->reg)
682 r = NULL;
683
684 return r;
685 }
686
687 /*
688 * These are the invariant cp15 registers: we let the guest see the host
689 * versions of these, so they're part of the guest state.
690 *
691 * A future CPU may provide a mechanism to present different values to
692 * the guest, or a future kvm may trap them.
693 */
694 /* Unfortunately, there's no register-argument for mrc, so generate. */
695 #define FUNCTION_FOR32(crn, crm, op1, op2, name) \
696 static void get_##name(struct kvm_vcpu *v, \
697 const struct coproc_reg *r) \
698 { \
699 u32 val; \
700 \
701 asm volatile("mrc p15, " __stringify(op1) \
702 ", %0, c" __stringify(crn) \
703 ", c" __stringify(crm) \
704 ", " __stringify(op2) "\n" : "=r" (val)); \
705 ((struct coproc_reg *)r)->val = val; \
706 }
707
708 FUNCTION_FOR32(0, 0, 0, 0, MIDR)
709 FUNCTION_FOR32(0, 0, 0, 1, CTR)
710 FUNCTION_FOR32(0, 0, 0, 2, TCMTR)
711 FUNCTION_FOR32(0, 0, 0, 3, TLBTR)
712 FUNCTION_FOR32(0, 0, 0, 6, REVIDR)
713 FUNCTION_FOR32(0, 1, 0, 0, ID_PFR0)
714 FUNCTION_FOR32(0, 1, 0, 1, ID_PFR1)
715 FUNCTION_FOR32(0, 1, 0, 2, ID_DFR0)
716 FUNCTION_FOR32(0, 1, 0, 3, ID_AFR0)
717 FUNCTION_FOR32(0, 1, 0, 4, ID_MMFR0)
718 FUNCTION_FOR32(0, 1, 0, 5, ID_MMFR1)
719 FUNCTION_FOR32(0, 1, 0, 6, ID_MMFR2)
720 FUNCTION_FOR32(0, 1, 0, 7, ID_MMFR3)
721 FUNCTION_FOR32(0, 2, 0, 0, ID_ISAR0)
722 FUNCTION_FOR32(0, 2, 0, 1, ID_ISAR1)
723 FUNCTION_FOR32(0, 2, 0, 2, ID_ISAR2)
724 FUNCTION_FOR32(0, 2, 0, 3, ID_ISAR3)
725 FUNCTION_FOR32(0, 2, 0, 4, ID_ISAR4)
726 FUNCTION_FOR32(0, 2, 0, 5, ID_ISAR5)
727 FUNCTION_FOR32(0, 0, 1, 1, CLIDR)
728 FUNCTION_FOR32(0, 0, 1, 7, AIDR)
729
730 /* ->val is filled in by kvm_invariant_coproc_table_init() */
731 static struct coproc_reg invariant_cp15[] = {
732 { CRn( 0), CRm( 0), Op1( 0), Op2( 0), is32, NULL, get_MIDR },
733 { CRn( 0), CRm( 0), Op1( 0), Op2( 1), is32, NULL, get_CTR },
734 { CRn( 0), CRm( 0), Op1( 0), Op2( 2), is32, NULL, get_TCMTR },
735 { CRn( 0), CRm( 0), Op1( 0), Op2( 3), is32, NULL, get_TLBTR },
736 { CRn( 0), CRm( 0), Op1( 0), Op2( 6), is32, NULL, get_REVIDR },
737
738 { CRn( 0), CRm( 0), Op1( 1), Op2( 1), is32, NULL, get_CLIDR },
739 { CRn( 0), CRm( 0), Op1( 1), Op2( 7), is32, NULL, get_AIDR },
740
741 { CRn( 0), CRm( 1), Op1( 0), Op2( 0), is32, NULL, get_ID_PFR0 },
742 { CRn( 0), CRm( 1), Op1( 0), Op2( 1), is32, NULL, get_ID_PFR1 },
743 { CRn( 0), CRm( 1), Op1( 0), Op2( 2), is32, NULL, get_ID_DFR0 },
744 { CRn( 0), CRm( 1), Op1( 0), Op2( 3), is32, NULL, get_ID_AFR0 },
745 { CRn( 0), CRm( 1), Op1( 0), Op2( 4), is32, NULL, get_ID_MMFR0 },
746 { CRn( 0), CRm( 1), Op1( 0), Op2( 5), is32, NULL, get_ID_MMFR1 },
747 { CRn( 0), CRm( 1), Op1( 0), Op2( 6), is32, NULL, get_ID_MMFR2 },
748 { CRn( 0), CRm( 1), Op1( 0), Op2( 7), is32, NULL, get_ID_MMFR3 },
749
750 { CRn( 0), CRm( 2), Op1( 0), Op2( 0), is32, NULL, get_ID_ISAR0 },
751 { CRn( 0), CRm( 2), Op1( 0), Op2( 1), is32, NULL, get_ID_ISAR1 },
752 { CRn( 0), CRm( 2), Op1( 0), Op2( 2), is32, NULL, get_ID_ISAR2 },
753 { CRn( 0), CRm( 2), Op1( 0), Op2( 3), is32, NULL, get_ID_ISAR3 },
754 { CRn( 0), CRm( 2), Op1( 0), Op2( 4), is32, NULL, get_ID_ISAR4 },
755 { CRn( 0), CRm( 2), Op1( 0), Op2( 5), is32, NULL, get_ID_ISAR5 },
756 };
757
758 /*
759 * Reads a register value from a userspace address to a kernel
760 * variable. Make sure that register size matches sizeof(*__val).
761 */
762 static int reg_from_user(void *val, const void __user *uaddr, u64 id)
763 {
764 if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0)
765 return -EFAULT;
766 return 0;
767 }
768
769 /*
770 * Writes a register value to a userspace address from a kernel variable.
771 * Make sure that register size matches sizeof(*__val).
772 */
773 static int reg_to_user(void __user *uaddr, const void *val, u64 id)
774 {
775 if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0)
776 return -EFAULT;
777 return 0;
778 }
779
780 static int get_invariant_cp15(u64 id, void __user *uaddr)
781 {
782 struct coproc_params params;
783 const struct coproc_reg *r;
784 int ret;
785
786 if (!index_to_params(id, &params))
787 return -ENOENT;
788
789 r = find_reg(&params, invariant_cp15, ARRAY_SIZE(invariant_cp15));
790 if (!r)
791 return -ENOENT;
792
793 ret = -ENOENT;
794 if (KVM_REG_SIZE(id) == 4) {
795 u32 val = r->val;
796
797 ret = reg_to_user(uaddr, &val, id);
798 } else if (KVM_REG_SIZE(id) == 8) {
799 ret = reg_to_user(uaddr, &r->val, id);
800 }
801 return ret;
802 }
803
804 static int set_invariant_cp15(u64 id, void __user *uaddr)
805 {
806 struct coproc_params params;
807 const struct coproc_reg *r;
808 int err;
809 u64 val;
810
811 if (!index_to_params(id, &params))
812 return -ENOENT;
813 r = find_reg(&params, invariant_cp15, ARRAY_SIZE(invariant_cp15));
814 if (!r)
815 return -ENOENT;
816
817 err = -ENOENT;
818 if (KVM_REG_SIZE(id) == 4) {
819 u32 val32;
820
821 err = reg_from_user(&val32, uaddr, id);
822 if (!err)
823 val = val32;
824 } else if (KVM_REG_SIZE(id) == 8) {
825 err = reg_from_user(&val, uaddr, id);
826 }
827 if (err)
828 return err;
829
830 /* This is what we mean by invariant: you can't change it. */
831 if (r->val != val)
832 return -EINVAL;
833
834 return 0;
835 }
836
837 static bool is_valid_cache(u32 val)
838 {
839 u32 level, ctype;
840
841 if (val >= CSSELR_MAX)
842 return false;
843
844 /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */
845 level = (val >> 1);
846 ctype = (cache_levels >> (level * 3)) & 7;
847
848 switch (ctype) {
849 case 0: /* No cache */
850 return false;
851 case 1: /* Instruction cache only */
852 return (val & 1);
853 case 2: /* Data cache only */
854 case 4: /* Unified cache */
855 return !(val & 1);
856 case 3: /* Separate instruction and data caches */
857 return true;
858 default: /* Reserved: we can't know instruction or data. */
859 return false;
860 }
861 }
862
863 /* Which cache CCSIDR represents depends on CSSELR value. */
864 static u32 get_ccsidr(u32 csselr)
865 {
866 u32 ccsidr;
867
868 /* Make sure noone else changes CSSELR during this! */
869 local_irq_disable();
870 /* Put value into CSSELR */
871 asm volatile("mcr p15, 2, %0, c0, c0, 0" : : "r" (csselr));
872 isb();
873 /* Read result out of CCSIDR */
874 asm volatile("mrc p15, 1, %0, c0, c0, 0" : "=r" (ccsidr));
875 local_irq_enable();
876
877 return ccsidr;
878 }
879
880 static int demux_c15_get(u64 id, void __user *uaddr)
881 {
882 u32 val;
883 u32 __user *uval = uaddr;
884
885 /* Fail if we have unknown bits set. */
886 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
887 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
888 return -ENOENT;
889
890 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
891 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
892 if (KVM_REG_SIZE(id) != 4)
893 return -ENOENT;
894 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
895 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
896 if (!is_valid_cache(val))
897 return -ENOENT;
898
899 return put_user(get_ccsidr(val), uval);
900 default:
901 return -ENOENT;
902 }
903 }
904
905 static int demux_c15_set(u64 id, void __user *uaddr)
906 {
907 u32 val, newval;
908 u32 __user *uval = uaddr;
909
910 /* Fail if we have unknown bits set. */
911 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
912 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
913 return -ENOENT;
914
915 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
916 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
917 if (KVM_REG_SIZE(id) != 4)
918 return -ENOENT;
919 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
920 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
921 if (!is_valid_cache(val))
922 return -ENOENT;
923
924 if (get_user(newval, uval))
925 return -EFAULT;
926
927 /* This is also invariant: you can't change it. */
928 if (newval != get_ccsidr(val))
929 return -EINVAL;
930 return 0;
931 default:
932 return -ENOENT;
933 }
934 }
935
936 #ifdef CONFIG_VFPv3
937 static const int vfp_sysregs[] = { KVM_REG_ARM_VFP_FPEXC,
938 KVM_REG_ARM_VFP_FPSCR,
939 KVM_REG_ARM_VFP_FPINST,
940 KVM_REG_ARM_VFP_FPINST2,
941 KVM_REG_ARM_VFP_MVFR0,
942 KVM_REG_ARM_VFP_MVFR1,
943 KVM_REG_ARM_VFP_FPSID };
944
945 static unsigned int num_fp_regs(void)
946 {
947 if (((fmrx(MVFR0) & MVFR0_A_SIMD_MASK) >> MVFR0_A_SIMD_BIT) == 2)
948 return 32;
949 else
950 return 16;
951 }
952
953 static unsigned int num_vfp_regs(void)
954 {
955 /* Normal FP regs + control regs. */
956 return num_fp_regs() + ARRAY_SIZE(vfp_sysregs);
957 }
958
959 static int copy_vfp_regids(u64 __user *uindices)
960 {
961 unsigned int i;
962 const u64 u32reg = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP;
963 const u64 u64reg = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP;
964
965 for (i = 0; i < num_fp_regs(); i++) {
966 if (put_user((u64reg | KVM_REG_ARM_VFP_BASE_REG) + i,
967 uindices))
968 return -EFAULT;
969 uindices++;
970 }
971
972 for (i = 0; i < ARRAY_SIZE(vfp_sysregs); i++) {
973 if (put_user(u32reg | vfp_sysregs[i], uindices))
974 return -EFAULT;
975 uindices++;
976 }
977
978 return num_vfp_regs();
979 }
980
981 static int vfp_get_reg(const struct kvm_vcpu *vcpu, u64 id, void __user *uaddr)
982 {
983 u32 vfpid = (id & KVM_REG_ARM_VFP_MASK);
984 u32 val;
985
986 /* Fail if we have unknown bits set. */
987 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
988 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
989 return -ENOENT;
990
991 if (vfpid < num_fp_regs()) {
992 if (KVM_REG_SIZE(id) != 8)
993 return -ENOENT;
994 return reg_to_user(uaddr, &vcpu->arch.ctxt.vfp.fpregs[vfpid],
995 id);
996 }
997
998 /* FP control registers are all 32 bit. */
999 if (KVM_REG_SIZE(id) != 4)
1000 return -ENOENT;
1001
1002 switch (vfpid) {
1003 case KVM_REG_ARM_VFP_FPEXC:
1004 return reg_to_user(uaddr, &vcpu->arch.ctxt.vfp.fpexc, id);
1005 case KVM_REG_ARM_VFP_FPSCR:
1006 return reg_to_user(uaddr, &vcpu->arch.ctxt.vfp.fpscr, id);
1007 case KVM_REG_ARM_VFP_FPINST:
1008 return reg_to_user(uaddr, &vcpu->arch.ctxt.vfp.fpinst, id);
1009 case KVM_REG_ARM_VFP_FPINST2:
1010 return reg_to_user(uaddr, &vcpu->arch.ctxt.vfp.fpinst2, id);
1011 case KVM_REG_ARM_VFP_MVFR0:
1012 val = fmrx(MVFR0);
1013 return reg_to_user(uaddr, &val, id);
1014 case KVM_REG_ARM_VFP_MVFR1:
1015 val = fmrx(MVFR1);
1016 return reg_to_user(uaddr, &val, id);
1017 case KVM_REG_ARM_VFP_FPSID:
1018 val = fmrx(FPSID);
1019 return reg_to_user(uaddr, &val, id);
1020 default:
1021 return -ENOENT;
1022 }
1023 }
1024
1025 static int vfp_set_reg(struct kvm_vcpu *vcpu, u64 id, const void __user *uaddr)
1026 {
1027 u32 vfpid = (id & KVM_REG_ARM_VFP_MASK);
1028 u32 val;
1029
1030 /* Fail if we have unknown bits set. */
1031 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
1032 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
1033 return -ENOENT;
1034
1035 if (vfpid < num_fp_regs()) {
1036 if (KVM_REG_SIZE(id) != 8)
1037 return -ENOENT;
1038 return reg_from_user(&vcpu->arch.ctxt.vfp.fpregs[vfpid],
1039 uaddr, id);
1040 }
1041
1042 /* FP control registers are all 32 bit. */
1043 if (KVM_REG_SIZE(id) != 4)
1044 return -ENOENT;
1045
1046 switch (vfpid) {
1047 case KVM_REG_ARM_VFP_FPEXC:
1048 return reg_from_user(&vcpu->arch.ctxt.vfp.fpexc, uaddr, id);
1049 case KVM_REG_ARM_VFP_FPSCR:
1050 return reg_from_user(&vcpu->arch.ctxt.vfp.fpscr, uaddr, id);
1051 case KVM_REG_ARM_VFP_FPINST:
1052 return reg_from_user(&vcpu->arch.ctxt.vfp.fpinst, uaddr, id);
1053 case KVM_REG_ARM_VFP_FPINST2:
1054 return reg_from_user(&vcpu->arch.ctxt.vfp.fpinst2, uaddr, id);
1055 /* These are invariant. */
1056 case KVM_REG_ARM_VFP_MVFR0:
1057 if (reg_from_user(&val, uaddr, id))
1058 return -EFAULT;
1059 if (val != fmrx(MVFR0))
1060 return -EINVAL;
1061 return 0;
1062 case KVM_REG_ARM_VFP_MVFR1:
1063 if (reg_from_user(&val, uaddr, id))
1064 return -EFAULT;
1065 if (val != fmrx(MVFR1))
1066 return -EINVAL;
1067 return 0;
1068 case KVM_REG_ARM_VFP_FPSID:
1069 if (reg_from_user(&val, uaddr, id))
1070 return -EFAULT;
1071 if (val != fmrx(FPSID))
1072 return -EINVAL;
1073 return 0;
1074 default:
1075 return -ENOENT;
1076 }
1077 }
1078 #else /* !CONFIG_VFPv3 */
1079 static unsigned int num_vfp_regs(void)
1080 {
1081 return 0;
1082 }
1083
1084 static int copy_vfp_regids(u64 __user *uindices)
1085 {
1086 return 0;
1087 }
1088
1089 static int vfp_get_reg(const struct kvm_vcpu *vcpu, u64 id, void __user *uaddr)
1090 {
1091 return -ENOENT;
1092 }
1093
1094 static int vfp_set_reg(struct kvm_vcpu *vcpu, u64 id, const void __user *uaddr)
1095 {
1096 return -ENOENT;
1097 }
1098 #endif /* !CONFIG_VFPv3 */
1099
1100 int kvm_arm_coproc_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
1101 {
1102 const struct coproc_reg *r;
1103 void __user *uaddr = (void __user *)(long)reg->addr;
1104 int ret;
1105
1106 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
1107 return demux_c15_get(reg->id, uaddr);
1108
1109 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_VFP)
1110 return vfp_get_reg(vcpu, reg->id, uaddr);
1111
1112 r = index_to_coproc_reg(vcpu, reg->id);
1113 if (!r)
1114 return get_invariant_cp15(reg->id, uaddr);
1115
1116 ret = -ENOENT;
1117 if (KVM_REG_SIZE(reg->id) == 8) {
1118 u64 val;
1119
1120 val = vcpu_cp15_reg64_get(vcpu, r);
1121 ret = reg_to_user(uaddr, &val, reg->id);
1122 } else if (KVM_REG_SIZE(reg->id) == 4) {
1123 ret = reg_to_user(uaddr, &vcpu_cp15(vcpu, r->reg), reg->id);
1124 }
1125
1126 return ret;
1127 }
1128
1129 int kvm_arm_coproc_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
1130 {
1131 const struct coproc_reg *r;
1132 void __user *uaddr = (void __user *)(long)reg->addr;
1133 int ret;
1134
1135 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
1136 return demux_c15_set(reg->id, uaddr);
1137
1138 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_VFP)
1139 return vfp_set_reg(vcpu, reg->id, uaddr);
1140
1141 r = index_to_coproc_reg(vcpu, reg->id);
1142 if (!r)
1143 return set_invariant_cp15(reg->id, uaddr);
1144
1145 ret = -ENOENT;
1146 if (KVM_REG_SIZE(reg->id) == 8) {
1147 u64 val;
1148
1149 ret = reg_from_user(&val, uaddr, reg->id);
1150 if (!ret)
1151 vcpu_cp15_reg64_set(vcpu, r, val);
1152 } else if (KVM_REG_SIZE(reg->id) == 4) {
1153 ret = reg_from_user(&vcpu_cp15(vcpu, r->reg), uaddr, reg->id);
1154 }
1155
1156 return ret;
1157 }
1158
1159 static unsigned int num_demux_regs(void)
1160 {
1161 unsigned int i, count = 0;
1162
1163 for (i = 0; i < CSSELR_MAX; i++)
1164 if (is_valid_cache(i))
1165 count++;
1166
1167 return count;
1168 }
1169
1170 static int write_demux_regids(u64 __user *uindices)
1171 {
1172 u64 val = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
1173 unsigned int i;
1174
1175 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
1176 for (i = 0; i < CSSELR_MAX; i++) {
1177 if (!is_valid_cache(i))
1178 continue;
1179 if (put_user(val | i, uindices))
1180 return -EFAULT;
1181 uindices++;
1182 }
1183 return 0;
1184 }
1185
1186 static u64 cp15_to_index(const struct coproc_reg *reg)
1187 {
1188 u64 val = KVM_REG_ARM | (15 << KVM_REG_ARM_COPROC_SHIFT);
1189 if (reg->is_64bit) {
1190 val |= KVM_REG_SIZE_U64;
1191 val |= (reg->Op1 << KVM_REG_ARM_OPC1_SHIFT);
1192 /*
1193 * CRn always denotes the primary coproc. reg. nr. for the
1194 * in-kernel representation, but the user space API uses the
1195 * CRm for the encoding, because it is modelled after the
1196 * MRRC/MCRR instructions: see the ARM ARM rev. c page
1197 * B3-1445
1198 */
1199 val |= (reg->CRn << KVM_REG_ARM_CRM_SHIFT);
1200 } else {
1201 val |= KVM_REG_SIZE_U32;
1202 val |= (reg->Op1 << KVM_REG_ARM_OPC1_SHIFT);
1203 val |= (reg->Op2 << KVM_REG_ARM_32_OPC2_SHIFT);
1204 val |= (reg->CRm << KVM_REG_ARM_CRM_SHIFT);
1205 val |= (reg->CRn << KVM_REG_ARM_32_CRN_SHIFT);
1206 }
1207 return val;
1208 }
1209
1210 static bool copy_reg_to_user(const struct coproc_reg *reg, u64 __user **uind)
1211 {
1212 if (!*uind)
1213 return true;
1214
1215 if (put_user(cp15_to_index(reg), *uind))
1216 return false;
1217
1218 (*uind)++;
1219 return true;
1220 }
1221
1222 /* Assumed ordered tables, see kvm_coproc_table_init. */
1223 static int walk_cp15(struct kvm_vcpu *vcpu, u64 __user *uind)
1224 {
1225 const struct coproc_reg *i1, *i2, *end1, *end2;
1226 unsigned int total = 0;
1227 size_t num;
1228
1229 /* We check for duplicates here, to allow arch-specific overrides. */
1230 i1 = get_target_table(vcpu->arch.target, &num);
1231 end1 = i1 + num;
1232 i2 = cp15_regs;
1233 end2 = cp15_regs + ARRAY_SIZE(cp15_regs);
1234
1235 BUG_ON(i1 == end1 || i2 == end2);
1236
1237 /* Walk carefully, as both tables may refer to the same register. */
1238 while (i1 || i2) {
1239 int cmp = cmp_reg(i1, i2);
1240 /* target-specific overrides generic entry. */
1241 if (cmp <= 0) {
1242 /* Ignore registers we trap but don't save. */
1243 if (i1->reg) {
1244 if (!copy_reg_to_user(i1, &uind))
1245 return -EFAULT;
1246 total++;
1247 }
1248 } else {
1249 /* Ignore registers we trap but don't save. */
1250 if (i2->reg) {
1251 if (!copy_reg_to_user(i2, &uind))
1252 return -EFAULT;
1253 total++;
1254 }
1255 }
1256
1257 if (cmp <= 0 && ++i1 == end1)
1258 i1 = NULL;
1259 if (cmp >= 0 && ++i2 == end2)
1260 i2 = NULL;
1261 }
1262 return total;
1263 }
1264
1265 unsigned long kvm_arm_num_coproc_regs(struct kvm_vcpu *vcpu)
1266 {
1267 return ARRAY_SIZE(invariant_cp15)
1268 + num_demux_regs()
1269 + num_vfp_regs()
1270 + walk_cp15(vcpu, (u64 __user *)NULL);
1271 }
1272
1273 int kvm_arm_copy_coproc_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
1274 {
1275 unsigned int i;
1276 int err;
1277
1278 /* Then give them all the invariant registers' indices. */
1279 for (i = 0; i < ARRAY_SIZE(invariant_cp15); i++) {
1280 if (put_user(cp15_to_index(&invariant_cp15[i]), uindices))
1281 return -EFAULT;
1282 uindices++;
1283 }
1284
1285 err = walk_cp15(vcpu, uindices);
1286 if (err < 0)
1287 return err;
1288 uindices += err;
1289
1290 err = copy_vfp_regids(uindices);
1291 if (err < 0)
1292 return err;
1293 uindices += err;
1294
1295 return write_demux_regids(uindices);
1296 }
1297
1298 void kvm_coproc_table_init(void)
1299 {
1300 unsigned int i;
1301
1302 /* Make sure tables are unique and in order. */
1303 BUG_ON(check_reg_table(cp15_regs, ARRAY_SIZE(cp15_regs)));
1304 BUG_ON(check_reg_table(invariant_cp15, ARRAY_SIZE(invariant_cp15)));
1305
1306 /* We abuse the reset function to overwrite the table itself. */
1307 for (i = 0; i < ARRAY_SIZE(invariant_cp15); i++)
1308 invariant_cp15[i].reset(NULL, &invariant_cp15[i]);
1309
1310 /*
1311 * CLIDR format is awkward, so clean it up. See ARM B4.1.20:
1312 *
1313 * If software reads the Cache Type fields from Ctype1
1314 * upwards, once it has seen a value of 0b000, no caches
1315 * exist at further-out levels of the hierarchy. So, for
1316 * example, if Ctype3 is the first Cache Type field with a
1317 * value of 0b000, the values of Ctype4 to Ctype7 must be
1318 * ignored.
1319 */
1320 asm volatile("mrc p15, 1, %0, c0, c0, 1" : "=r" (cache_levels));
1321 for (i = 0; i < 7; i++)
1322 if (((cache_levels >> (i*3)) & 7) == 0)
1323 break;
1324 /* Clear all higher bits. */
1325 cache_levels &= (1 << (i*3))-1;
1326 }
1327
1328 /**
1329 * kvm_reset_coprocs - sets cp15 registers to reset value
1330 * @vcpu: The VCPU pointer
1331 *
1332 * This function finds the right table above and sets the registers on the
1333 * virtual CPU struct to their architecturally defined reset values.
1334 */
1335 void kvm_reset_coprocs(struct kvm_vcpu *vcpu)
1336 {
1337 size_t num;
1338 const struct coproc_reg *table;
1339
1340 /* Catch someone adding a register without putting in reset entry. */
1341 memset(vcpu->arch.ctxt.cp15, 0x42, sizeof(vcpu->arch.ctxt.cp15));
1342
1343 /* Generic chip reset first (so target could override). */
1344 reset_coproc_regs(vcpu, cp15_regs, ARRAY_SIZE(cp15_regs));
1345
1346 table = get_target_table(vcpu->arch.target, &num);
1347 reset_coproc_regs(vcpu, table, num);
1348
1349 for (num = 1; num < NR_CP15_REGS; num++)
1350 if (vcpu_cp15(vcpu, num) == 0x42424242)
1351 panic("Didn't reset vcpu_cp15(vcpu, %zi)", num);
1352 }
Linux with added FPC-III support