arch/arm/mach-davinci/asp.h

   1 /*
   2  * TI DaVinci Audio definitions
   3  */
   4 #ifndef __ASM_ARCH_DAVINCI_ASP_H
   5 #define __ASM_ARCH_DAVINCI_ASP_H
   6
   7 /* Bases of dm644x and dm355 register banks */
   8 #define DAVINCI_ASP0_BASE       0x01E02000
   9 #define DAVINCI_ASP1_BASE       0x01E04000
  10
  11 /* Bases of dm365 register banks */
  12 #define DAVINCI_DM365_ASP0_BASE 0x01D02000
  13
  14 /* Bases of dm646x register banks */
  15 #define DAVINCI_DM646X_MCASP0_REG_BASE          0x01D01000
  16 #define DAVINCI_DM646X_MCASP1_REG_BASE          0x01D01800
  17
  18 /* Bases of da850/da830 McASP0  register banks */
  19 #define DAVINCI_DA8XX_MCASP0_REG_BASE   0x01D00000
  20
  21 /* Bases of da830 McASP1 register banks */
  22 #define DAVINCI_DA830_MCASP1_REG_BASE   0x01D04000
  23
  24 /* Bases of da830 McASP2 register banks */
  25 #define DAVINCI_DA830_MCASP2_REG_BASE   0x01D08000
  26
  27 /* EDMA channels of dm644x and dm355 */
  28 #define DAVINCI_DMA_ASP0_TX     2
  29 #define DAVINCI_DMA_ASP0_RX     3
  30 #define DAVINCI_DMA_ASP1_TX     8
  31 #define DAVINCI_DMA_ASP1_RX     9
  32
  33 /* EDMA channels of dm646x */
  34 #define DAVINCI_DM646X_DMA_MCASP0_AXEVT0        6
  35 #define DAVINCI_DM646X_DMA_MCASP0_AREVT0        9
  36 #define DAVINCI_DM646X_DMA_MCASP1_AXEVT1        12
  37
  38 /* EDMA channels of da850/da830 McASP0 */
  39 #define DAVINCI_DA8XX_DMA_MCASP0_AREVT  0
  40 #define DAVINCI_DA8XX_DMA_MCASP0_AXEVT  1
  41
  42 /* EDMA channels of da830 McASP1 */
  43 #define DAVINCI_DA830_DMA_MCASP1_AREVT  2
  44 #define DAVINCI_DA830_DMA_MCASP1_AXEVT  3
  45
  46 /* EDMA channels of da830 McASP2 */
  47 #define DAVINCI_DA830_DMA_MCASP2_AREVT  4
  48 #define DAVINCI_DA830_DMA_MCASP2_AXEVT  5
  49
  50 /* Interrupts */
  51 #define DAVINCI_ASP0_RX_INT     IRQ_MBRINT
  52 #define DAVINCI_ASP0_TX_INT     IRQ_MBXINT
  53 #define DAVINCI_ASP1_RX_INT     IRQ_MBRINT
  54 #define DAVINCI_ASP1_TX_INT     IRQ_MBXINT
  55
  56 #endif /* __ASM_ARCH_DAVINCI_ASP_H */