x86/mm/pat: Don't report PAT on CPUs that don't support it
[linux/fpc-iii.git] / arch / arm / mach-s3c24xx / pll-s3c2410.c
blob7ee4924a543d7ad977fe040a716652cef8c6f357
1 /*
2 * Copyright (c) 2006-2007 Simtec Electronics
3 * http://armlinux.simtec.co.uk/
4 * Ben Dooks <ben@simtec.co.uk>
5 * Vincent Sanders <vince@arm.linux.org.uk>
7 * S3C2410 CPU PLL tables
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #include <linux/types.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/device.h>
28 #include <linux/list.h>
29 #include <linux/clk.h>
30 #include <linux/err.h>
32 #include <plat/cpu.h>
33 #include <plat/cpu-freq-core.h>
35 /* This array should be sorted in ascending order of the frequencies */
36 static struct cpufreq_frequency_table pll_vals_12MHz[] = {
37 { .frequency = 34000000, .driver_data = PLLVAL(82, 2, 3), },
38 { .frequency = 45000000, .driver_data = PLLVAL(82, 1, 3), },
39 { .frequency = 48000000, .driver_data = PLLVAL(120, 2, 3), },
40 { .frequency = 51000000, .driver_data = PLLVAL(161, 3, 3), },
41 { .frequency = 56000000, .driver_data = PLLVAL(142, 2, 3), },
42 { .frequency = 68000000, .driver_data = PLLVAL(82, 2, 2), },
43 { .frequency = 79000000, .driver_data = PLLVAL(71, 1, 2), },
44 { .frequency = 85000000, .driver_data = PLLVAL(105, 2, 2), },
45 { .frequency = 90000000, .driver_data = PLLVAL(112, 2, 2), },
46 { .frequency = 101000000, .driver_data = PLLVAL(127, 2, 2), },
47 { .frequency = 113000000, .driver_data = PLLVAL(105, 1, 2), },
48 { .frequency = 118000000, .driver_data = PLLVAL(150, 2, 2), },
49 { .frequency = 124000000, .driver_data = PLLVAL(116, 1, 2), },
50 { .frequency = 135000000, .driver_data = PLLVAL(82, 2, 1), },
51 { .frequency = 147000000, .driver_data = PLLVAL(90, 2, 1), },
52 { .frequency = 152000000, .driver_data = PLLVAL(68, 1, 1), },
53 { .frequency = 158000000, .driver_data = PLLVAL(71, 1, 1), },
54 { .frequency = 170000000, .driver_data = PLLVAL(77, 1, 1), },
55 { .frequency = 180000000, .driver_data = PLLVAL(82, 1, 1), },
56 { .frequency = 186000000, .driver_data = PLLVAL(85, 1, 1), },
57 { .frequency = 192000000, .driver_data = PLLVAL(88, 1, 1), },
58 { .frequency = 203000000, .driver_data = PLLVAL(161, 3, 1), },
60 /* 2410A extras */
62 { .frequency = 210000000, .driver_data = PLLVAL(132, 2, 1), },
63 { .frequency = 226000000, .driver_data = PLLVAL(105, 1, 1), },
64 { .frequency = 266000000, .driver_data = PLLVAL(125, 1, 1), },
65 { .frequency = 268000000, .driver_data = PLLVAL(126, 1, 1), },
66 { .frequency = 270000000, .driver_data = PLLVAL(127, 1, 1), },
69 static int s3c2410_plls_add(struct device *dev, struct subsys_interface *sif)
71 return s3c_plltab_register(pll_vals_12MHz, ARRAY_SIZE(pll_vals_12MHz));
74 static struct subsys_interface s3c2410_plls_interface = {
75 .name = "s3c2410_plls",
76 .subsys = &s3c2410_subsys,
77 .add_dev = s3c2410_plls_add,
80 static int __init s3c2410_pll_init(void)
82 return subsys_interface_register(&s3c2410_plls_interface);
85 arch_initcall(s3c2410_pll_init);
87 static struct subsys_interface s3c2410a_plls_interface = {
88 .name = "s3c2410a_plls",
89 .subsys = &s3c2410a_subsys,
90 .add_dev = s3c2410_plls_add,
93 static int __init s3c2410a_pll_init(void)
95 return subsys_interface_register(&s3c2410a_plls_interface);
97 arch_initcall(s3c2410a_pll_init);