arch/arm/mach-tegra/cpuidle-tegra20.c

   1 /*
   2  * CPU idle driver for Tegra CPUs
   3  *
   4  * Copyright (c) 2010-2012, NVIDIA Corporation.
   5  * Copyright (c) 2011 Google, Inc.
   6  * Author: Colin Cross <ccross@android.com>
   7  *         Gary King <gking@nvidia.com>
   8  *
   9  * Rework for 3.3 by Peter De Schrijver <pdeschrijver@nvidia.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful, but WITHOUT
  17  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  * more details.
  20  */
  21
  22 #include <linux/clk/tegra.h>
  23 #include <linux/tick.h>
  24 #include <linux/cpuidle.h>
  25 #include <linux/cpu_pm.h>
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28
  29 #include <asm/cpuidle.h>
  30 #include <asm/smp_plat.h>
  31 #include <asm/suspend.h>
  32
  33 #include "cpuidle.h"
  34 #include "flowctrl.h"
  35 #include "iomap.h"
  36 #include "irq.h"
  37 #include "pm.h"
  38 #include "reset.h"
  39 #include "sleep.h"
  40
  41 #ifdef CONFIG_PM_SLEEP
  42 static bool abort_flag;
  43 static atomic_t abort_barrier;
  44 static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev,
  45                                     struct cpuidle_driver *drv,
  46                                     int index);
  47 #define TEGRA20_MAX_STATES 2
  48 #else
  49 #define TEGRA20_MAX_STATES 1
  50 #endif
  51
  52 static struct cpuidle_driver tegra_idle_driver = {
  53         .name = "tegra_idle",
  54         .owner = THIS_MODULE,
  55         .states = {
  56                 ARM_CPUIDLE_WFI_STATE_PWR(600),
  57 #ifdef CONFIG_PM_SLEEP
  58                 {
  59                         .enter            = tegra20_idle_lp2_coupled,
  60                         .exit_latency     = 5000,
  61                         .target_residency = 10000,
  62                         .power_usage      = 0,
  63                         .flags            = CPUIDLE_FLAG_COUPLED,
  64                         .name             = "powered-down",
  65                         .desc             = "CPU power gated",
  66                 },
  67 #endif
  68         },
  69         .state_count = TEGRA20_MAX_STATES,
  70         .safe_state_index = 0,
  71 };
  72
  73 #ifdef CONFIG_PM_SLEEP
  74 #ifdef CONFIG_SMP
  75 static int tegra20_reset_sleeping_cpu_1(void)
  76 {
  77         int ret = 0;
  78
  79         tegra_pen_lock();
  80
  81         if (readb(tegra20_cpu1_resettable_status) == CPU_RESETTABLE)
  82                 tegra20_cpu_shutdown(1);
  83         else
  84                 ret = -EINVAL;
  85
  86         tegra_pen_unlock();
  87
  88         return ret;
  89 }
  90
  91 static void tegra20_wake_cpu1_from_reset(void)
  92 {
  93         tegra_pen_lock();
  94
  95         tegra20_cpu_clear_resettable();
  96
  97         /* enable cpu clock on cpu */
  98         tegra_enable_cpu_clock(1);
  99
 100         /* take the CPU out of reset */
 101         tegra_cpu_out_of_reset(1);
 102
 103         /* unhalt the cpu */
 104         flowctrl_write_cpu_halt(1, 0);
 105
 106         tegra_pen_unlock();
 107 }
 108
 109 static int tegra20_reset_cpu_1(void)
 110 {
 111         if (!cpu_online(1) || !tegra20_reset_sleeping_cpu_1())
 112                 return 0;
 113
 114         tegra20_wake_cpu1_from_reset();
 115         return -EBUSY;
 116 }
 117 #else
 118 static inline void tegra20_wake_cpu1_from_reset(void)
 119 {
 120 }
 121
 122 static inline int tegra20_reset_cpu_1(void)
 123 {
 124         return 0;
 125 }
 126 #endif
 127
 128 static bool tegra20_cpu_cluster_power_down(struct cpuidle_device *dev,
 129                                            struct cpuidle_driver *drv,
 130                                            int index)
 131 {
 132         while (tegra20_cpu_is_resettable_soon())
 133                 cpu_relax();
 134
 135         if (tegra20_reset_cpu_1() || !tegra_cpu_rail_off_ready())
 136                 return false;
 137
 138         tick_broadcast_enter();
 139
 140         tegra_idle_lp2_last();
 141
 142         tick_broadcast_exit();
 143
 144         if (cpu_online(1))
 145                 tegra20_wake_cpu1_from_reset();
 146
 147         return true;
 148 }
 149
 150 #ifdef CONFIG_SMP
 151 static bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev,
 152                                          struct cpuidle_driver *drv,
 153                                          int index)
 154 {
 155         tick_broadcast_enter();
 156
 157         cpu_suspend(0, tegra20_sleep_cpu_secondary_finish);
 158
 159         tegra20_cpu_clear_resettable();
 160
 161         tick_broadcast_exit();
 162
 163         return true;
 164 }
 165 #else
 166 static inline bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev,
 167                                                 struct cpuidle_driver *drv,
 168                                                 int index)
 169 {
 170         return true;
 171 }
 172 #endif
 173
 174 static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev,
 175                                     struct cpuidle_driver *drv,
 176                                     int index)
 177 {
 178         bool entered_lp2 = false;
 179
 180         if (tegra_pending_sgi())
 181                 ACCESS_ONCE(abort_flag) = true;
 182
 183         cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
 184
 185         if (abort_flag) {
 186                 cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
 187                 abort_flag = false;     /* clean flag for next coming */
 188                 return -EINTR;
 189         }
 190
 191         local_fiq_disable();
 192
 193         tegra_set_cpu_in_lp2();
 194         cpu_pm_enter();
 195
 196         if (dev->cpu == 0)
 197                 entered_lp2 = tegra20_cpu_cluster_power_down(dev, drv, index);
 198         else
 199                 entered_lp2 = tegra20_idle_enter_lp2_cpu_1(dev, drv, index);
 200
 201         cpu_pm_exit();
 202         tegra_clear_cpu_in_lp2();
 203
 204         local_fiq_enable();
 205
 206         smp_rmb();
 207
 208         return entered_lp2 ? index : 0;
 209 }
 210 #endif
 211
 212 /*
 213  * Tegra20 HW appears to have a bug such that PCIe device interrupts, whether
 214  * they are legacy IRQs or MSI, are lost when LP2 is enabled. To work around
 215  * this, simply disable LP2 if the PCI driver and DT node are both enabled.
 216  */
 217 void tegra20_cpuidle_pcie_irqs_in_use(void)
 218 {
 219         pr_info_once(
 220                 "Disabling cpuidle LP2 state, since PCIe IRQs are in use\n");
 221         tegra_idle_driver.states[1].disabled = true;
 222 }
 223
 224 int __init tegra20_cpuidle_init(void)
 225 {
 226         return cpuidle_register(&tegra_idle_driver, cpu_possible_mask);
 227 }