| blob | d00d52c9de3e0228c34aeebb0ec86d4b280220f9 |
1 /*
2 * linux/arch/arm/mm/proc-v7.S
3 *
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This is the "shell" of the ARMv7 processor support.
11 */
12 #include <linux/init.h>
13 #include <linux/linkage.h>
14 #include <asm/assembler.h>
15 #include <asm/asm-offsets.h>
16 #include <asm/hwcap.h>
17 #include <asm/pgtable-hwdef.h>
18 #include <asm/pgtable.h>
19 #include <asm/memory.h>
21 #include "proc-macros.S"
23 #ifdef CONFIG_ARM_LPAE
24 #include "proc-v7-3level.S"
25 #else
26 #include "proc-v7-2level.S"
27 #endif
29 ENTRY(cpu_v7_proc_init)
30 ret lr
31 ENDPROC(cpu_v7_proc_init)
33 ENTRY(cpu_v7_proc_fin)
34 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
35 bic r0, r0, #0x1000 @ ...i............
36 bic r0, r0, #0x0006 @ .............ca.
37 mcr p15, 0, r0, c1, c0, 0 @ disable caches
38 ret lr
39 ENDPROC(cpu_v7_proc_fin)
41 /*
42 * cpu_v7_reset(loc)
43 *
44 * Perform a soft reset of the system. Put the CPU into the
45 * same state as it would be if it had been reset, and branch
46 * to what would be the reset vector.
47 *
48 * - loc - location to jump to for soft reset
49 *
50 * This code must be executed using a flat identity mapping with
51 * caches disabled.
52 */
53 .align 5
54 .pushsection .idmap.text, "ax"
55 ENTRY(cpu_v7_reset)
56 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
57 bic r1, r1, #0x1 @ ...............m
58 THUMB( bic r1, r1, #1 << 30 ) @ SCTLR.TE (Thumb exceptions)
59 mcr p15, 0, r1, c1, c0, 0 @ disable MMU
60 isb
61 bx r0
62 ENDPROC(cpu_v7_reset)
63 .popsection
65 /*
66 * cpu_v7_do_idle()
67 *
68 * Idle the processor (eg, wait for interrupt).
69 *
70 * IRQs are already disabled.
71 */
72 ENTRY(cpu_v7_do_idle)
73 dsb @ WFI may enter a low-power mode
74 wfi
75 ret lr
76 ENDPROC(cpu_v7_do_idle)
78 ENTRY(cpu_v7_dcache_clean_area)
79 ALT_SMP(W(nop)) @ MP extensions imply L1 PTW
80 ALT_UP_B(1f)
81 ret lr
82 1: dcache_line_size r2, r3
83 2: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
84 add r0, r0, r2
85 subs r1, r1, r2
86 bhi 2b
87 dsb ishst
88 ret lr
89 ENDPROC(cpu_v7_dcache_clean_area)
91 string cpu_v7_name, "ARMv7 Processor"
92 .align
94 /* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
95 .globl cpu_v7_suspend_size
96 .equ cpu_v7_suspend_size, 4 * 9
97 #ifdef CONFIG_ARM_CPU_SUSPEND
98 ENTRY(cpu_v7_do_suspend)
99 stmfd sp!, {r4 - r11, lr}
100 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
101 mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID
102 stmia r0!, {r4 - r5}
103 #ifdef CONFIG_MMU
104 mrc p15, 0, r6, c3, c0, 0 @ Domain ID
105 #ifdef CONFIG_ARM_LPAE
106 mrrc p15, 1, r5, r7, c2 @ TTB 1
107 #else
108 mrc p15, 0, r7, c2, c0, 1 @ TTB 1
109 #endif
110 mrc p15, 0, r11, c2, c0, 2 @ TTB control register
111 #endif
112 mrc p15, 0, r8, c1, c0, 0 @ Control register
113 mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register
114 mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control
115 stmia r0, {r5 - r11}
116 ldmfd sp!, {r4 - r11, pc}
117 ENDPROC(cpu_v7_do_suspend)
119 ENTRY(cpu_v7_do_resume)
120 mov ip, #0
121 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
122 mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID
123 ldmia r0!, {r4 - r5}
124 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
125 mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID
126 ldmia r0, {r5 - r11}
127 #ifdef CONFIG_MMU
128 mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs
129 mcr p15, 0, r6, c3, c0, 0 @ Domain ID
130 #ifdef CONFIG_ARM_LPAE
131 mcrr p15, 0, r1, ip, c2 @ TTB 0
132 mcrr p15, 1, r5, r7, c2 @ TTB 1
133 #else
134 ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP)
135 ALT_UP(orr r1, r1, #TTB_FLAGS_UP)
136 mcr p15, 0, r1, c2, c0, 0 @ TTB 0
137 mcr p15, 0, r7, c2, c0, 1 @ TTB 1
138 #endif
139 mcr p15, 0, r11, c2, c0, 2 @ TTB control register
140 ldr r4, =PRRR @ PRRR
141 ldr r5, =NMRR @ NMRR
142 mcr p15, 0, r4, c10, c2, 0 @ write PRRR
143 mcr p15, 0, r5, c10, c2, 1 @ write NMRR
144 #endif /* CONFIG_MMU */
145 mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register
146 teq r4, r9 @ Is it already set?
147 mcrne p15, 0, r9, c1, c0, 1 @ No, so write it
148 mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control
149 isb
150 dsb
151 mov r0, r8 @ control register
152 b cpu_resume_mmu
153 ENDPROC(cpu_v7_do_resume)
154 #endif
156 /*
157 * Cortex-A8
158 */
159 globl_equ cpu_ca8_proc_init, cpu_v7_proc_init
160 globl_equ cpu_ca8_proc_fin, cpu_v7_proc_fin
161 globl_equ cpu_ca8_reset, cpu_v7_reset
162 globl_equ cpu_ca8_do_idle, cpu_v7_do_idle
163 globl_equ cpu_ca8_dcache_clean_area, cpu_v7_dcache_clean_area
164 globl_equ cpu_ca8_set_pte_ext, cpu_v7_set_pte_ext
165 globl_equ cpu_ca8_suspend_size, cpu_v7_suspend_size
166 #ifdef CONFIG_ARM_CPU_SUSPEND
167 globl_equ cpu_ca8_do_suspend, cpu_v7_do_suspend
168 globl_equ cpu_ca8_do_resume, cpu_v7_do_resume
169 #endif
171 /*
172 * Cortex-A9 processor functions
173 */
174 globl_equ cpu_ca9mp_proc_init, cpu_v7_proc_init
175 globl_equ cpu_ca9mp_proc_fin, cpu_v7_proc_fin
176 globl_equ cpu_ca9mp_reset, cpu_v7_reset
177 globl_equ cpu_ca9mp_do_idle, cpu_v7_do_idle
178 globl_equ cpu_ca9mp_dcache_clean_area, cpu_v7_dcache_clean_area
179 globl_equ cpu_ca9mp_switch_mm, cpu_v7_switch_mm
180 globl_equ cpu_ca9mp_set_pte_ext, cpu_v7_set_pte_ext
181 .globl cpu_ca9mp_suspend_size
182 .equ cpu_ca9mp_suspend_size, cpu_v7_suspend_size + 4 * 2
183 #ifdef CONFIG_ARM_CPU_SUSPEND
184 ENTRY(cpu_ca9mp_do_suspend)
185 stmfd sp!, {r4 - r5}
186 mrc p15, 0, r4, c15, c0, 1 @ Diagnostic register
187 mrc p15, 0, r5, c15, c0, 0 @ Power register
188 stmia r0!, {r4 - r5}
189 ldmfd sp!, {r4 - r5}
190 b cpu_v7_do_suspend
191 ENDPROC(cpu_ca9mp_do_suspend)
193 ENTRY(cpu_ca9mp_do_resume)
194 ldmia r0!, {r4 - r5}
195 mrc p15, 0, r10, c15, c0, 1 @ Read Diagnostic register
196 teq r4, r10 @ Already restored?
197 mcrne p15, 0, r4, c15, c0, 1 @ No, so restore it
198 mrc p15, 0, r10, c15, c0, 0 @ Read Power register
199 teq r5, r10 @ Already restored?
200 mcrne p15, 0, r5, c15, c0, 0 @ No, so restore it
201 b cpu_v7_do_resume
202 ENDPROC(cpu_ca9mp_do_resume)
203 #endif
205 #ifdef CONFIG_CPU_PJ4B
206 globl_equ cpu_pj4b_switch_mm, cpu_v7_switch_mm
207 globl_equ cpu_pj4b_set_pte_ext, cpu_v7_set_pte_ext
208 globl_equ cpu_pj4b_proc_init, cpu_v7_proc_init
209 globl_equ cpu_pj4b_proc_fin, cpu_v7_proc_fin
210 globl_equ cpu_pj4b_reset, cpu_v7_reset
211 #ifdef CONFIG_PJ4B_ERRATA_4742
212 ENTRY(cpu_pj4b_do_idle)
213 dsb @ WFI may enter a low-power mode
214 wfi
215 dsb @barrier
216 ret lr
217 ENDPROC(cpu_pj4b_do_idle)
218 #else
219 globl_equ cpu_pj4b_do_idle, cpu_v7_do_idle
220 #endif
221 globl_equ cpu_pj4b_dcache_clean_area, cpu_v7_dcache_clean_area
222 #ifdef CONFIG_ARM_CPU_SUSPEND
223 ENTRY(cpu_pj4b_do_suspend)
224 stmfd sp!, {r6 - r10}
225 mrc p15, 1, r6, c15, c1, 0 @ save CP15 - extra features
226 mrc p15, 1, r7, c15, c2, 0 @ save CP15 - Aux Func Modes Ctrl 0
227 mrc p15, 1, r8, c15, c1, 2 @ save CP15 - Aux Debug Modes Ctrl 2
228 mrc p15, 1, r9, c15, c1, 1 @ save CP15 - Aux Debug Modes Ctrl 1
229 mrc p15, 0, r10, c9, c14, 0 @ save CP15 - PMC
230 stmia r0!, {r6 - r10}
231 ldmfd sp!, {r6 - r10}
232 b cpu_v7_do_suspend
233 ENDPROC(cpu_pj4b_do_suspend)
235 ENTRY(cpu_pj4b_do_resume)
236 ldmia r0!, {r6 - r10}
237 mcr p15, 1, r6, c15, c1, 0 @ restore CP15 - extra features
238 mcr p15, 1, r7, c15, c2, 0 @ restore CP15 - Aux Func Modes Ctrl 0
239 mcr p15, 1, r8, c15, c1, 2 @ restore CP15 - Aux Debug Modes Ctrl 2
240 mcr p15, 1, r9, c15, c1, 1 @ restore CP15 - Aux Debug Modes Ctrl 1
241 mcr p15, 0, r10, c9, c14, 0 @ restore CP15 - PMC
242 b cpu_v7_do_resume
243 ENDPROC(cpu_pj4b_do_resume)
244 #endif
245 .globl cpu_pj4b_suspend_size
246 .equ cpu_pj4b_suspend_size, cpu_v7_suspend_size + 4 * 5
248 #endif
250 /*
251 * __v7_setup
252 *
253 * Initialise TLB, Caches, and MMU state ready to switch the MMU
254 * on. Return in r0 the new CP15 C1 control register setting.
255 *
256 * r1, r2, r4, r5, r9, r13 must be preserved - r13 is not a stack
257 * r4: TTBR0 (low word)
258 * r5: TTBR0 (high word if LPAE)
259 * r8: TTBR1
260 * r9: Main ID register
261 *
262 * This should be able to cover all ARMv7 cores.
263 *
264 * It is assumed that:
265 * - cache type register is implemented
266 */
267 __v7_ca5mp_setup:
268 __v7_ca9mp_setup:
269 __v7_cr7mp_setup:
270 mov r10, #(1 << 0) @ Cache/TLB ops broadcasting
271 b 1f
272 __v7_ca7mp_setup:
273 __v7_ca12mp_setup:
274 __v7_ca15mp_setup:
275 __v7_b15mp_setup:
276 __v7_ca17mp_setup:
277 mov r10, #0
278 1: adr r0, __v7_setup_stack_ptr
279 ldr r12, [r0]
280 add r12, r12, r0 @ the local stack
281 stmia r12, {r1-r6, lr} @ v7_invalidate_l1 touches r0-r6
282 bl v7_invalidate_l1
283 ldmia r12, {r1-r6, lr}
284 #ifdef CONFIG_SMP
285 orr r10, r10, #(1 << 6) @ Enable SMP/nAMP mode
286 ALT_SMP(mrc p15, 0, r0, c1, c0, 1)
287 ALT_UP(mov r0, r10) @ fake it for UP
288 orr r10, r10, r0 @ Set required bits
289 teq r10, r0 @ Were they already set?
290 mcrne p15, 0, r10, c1, c0, 1 @ No, update register
291 #endif
292 b __v7_setup_cont
294 /*
295 * Errata:
296 * r0, r10 available for use
297 * r1, r2, r4, r5, r9, r13: must be preserved
298 * r3: contains MIDR rX number in bits 23-20
299 * r6: contains MIDR rXpY as 8-bit XY number
300 * r9: MIDR
301 */
302 __ca8_errata:
303 #if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM)
304 teq r3, #0x00100000 @ only present in r1p*
305 mrceq p15, 0, r0, c1, c0, 1 @ read aux control register
306 orreq r0, r0, #(1 << 6) @ set IBE to 1
307 mcreq p15, 0, r0, c1, c0, 1 @ write aux control register
308 #endif
309 #ifdef CONFIG_ARM_ERRATA_458693
310 teq r6, #0x20 @ only present in r2p0
311 mrceq p15, 0, r0, c1, c0, 1 @ read aux control register
312 orreq r0, r0, #(1 << 5) @ set L1NEON to 1
313 orreq r0, r0, #(1 << 9) @ set PLDNOP to 1
314 mcreq p15, 0, r0, c1, c0, 1 @ write aux control register
315 #endif
316 #ifdef CONFIG_ARM_ERRATA_460075
317 teq r6, #0x20 @ only present in r2p0
318 mrceq p15, 1, r0, c9, c0, 2 @ read L2 cache aux ctrl register
319 tsteq r0, #1 << 22
320 orreq r0, r0, #(1 << 22) @ set the Write Allocate disable bit
321 mcreq p15, 1, r0, c9, c0, 2 @ write the L2 cache aux ctrl register
322 #endif
323 b __errata_finish
325 __ca9_errata:
326 #ifdef CONFIG_ARM_ERRATA_742230
327 cmp r6, #0x22 @ only present up to r2p2
328 mrcle p15, 0, r0, c15, c0, 1 @ read diagnostic register
329 orrle r0, r0, #1 << 4 @ set bit #4
330 mcrle p15, 0, r0, c15, c0, 1 @ write diagnostic register
331 #endif
332 #ifdef CONFIG_ARM_ERRATA_742231
333 teq r6, #0x20 @ present in r2p0
334 teqne r6, #0x21 @ present in r2p1
335 teqne r6, #0x22 @ present in r2p2
336 mrceq p15, 0, r0, c15, c0, 1 @ read diagnostic register
337 orreq r0, r0, #1 << 12 @ set bit #12
338 orreq r0, r0, #1 << 22 @ set bit #22
339 mcreq p15, 0, r0, c15, c0, 1 @ write diagnostic register
340 #endif
341 #ifdef CONFIG_ARM_ERRATA_743622
342 teq r3, #0x00200000 @ only present in r2p*
343 mrceq p15, 0, r0, c15, c0, 1 @ read diagnostic register
344 orreq r0, r0, #1 << 6 @ set bit #6
345 mcreq p15, 0, r0, c15, c0, 1 @ write diagnostic register
346 #endif
347 #if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP)
348 ALT_SMP(cmp r6, #0x30) @ present prior to r3p0
349 ALT_UP_B(1f)
350 mrclt p15, 0, r0, c15, c0, 1 @ read diagnostic register
351 orrlt r0, r0, #1 << 11 @ set bit #11
352 mcrlt p15, 0, r0, c15, c0, 1 @ write diagnostic register
353 1:
354 #endif
355 b __errata_finish
357 __ca15_errata:
358 #ifdef CONFIG_ARM_ERRATA_773022
359 cmp r6, #0x4 @ only present up to r0p4
360 mrcle p15, 0, r0, c1, c0, 1 @ read aux control register
361 orrle r0, r0, #1 << 1 @ disable loop buffer
362 mcrle p15, 0, r0, c1, c0, 1 @ write aux control register
363 #endif
364 b __errata_finish
366 __ca12_errata:
367 #ifdef CONFIG_ARM_ERRATA_818325_852422
368 mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register
369 orr r10, r10, #1 << 12 @ set bit #12
370 mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register
371 #endif
372 #ifdef CONFIG_ARM_ERRATA_821420
373 mrc p15, 0, r10, c15, c0, 2 @ read internal feature reg
374 orr r10, r10, #1 << 1 @ set bit #1
375 mcr p15, 0, r10, c15, c0, 2 @ write internal feature reg
376 #endif
377 #ifdef CONFIG_ARM_ERRATA_825619
378 mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register
379 orr r10, r10, #1 << 24 @ set bit #24
380 mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register
381 #endif
382 b __errata_finish
384 __ca17_errata:
385 #ifdef CONFIG_ARM_ERRATA_852421
386 cmp r6, #0x12 @ only present up to r1p2
387 mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
388 orrle r10, r10, #1 << 24 @ set bit #24
389 mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
390 #endif
391 #ifdef CONFIG_ARM_ERRATA_852423
392 cmp r6, #0x12 @ only present up to r1p2
393 mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
394 orrle r10, r10, #1 << 12 @ set bit #12
395 mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
396 #endif
397 b __errata_finish
399 __v7_pj4b_setup:
400 #ifdef CONFIG_CPU_PJ4B
402 /* Auxiliary Debug Modes Control 1 Register */
403 #define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */
404 #define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */
405 #define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */
407 /* Auxiliary Debug Modes Control 2 Register */
408 #define PJ4B_FAST_LDR (1 << 23) /* Disable fast LDR */
409 #define PJ4B_SNOOP_DATA (1 << 25) /* Do not interleave write and snoop data */
410 #define PJ4B_CWF (1 << 27) /* Disable Critical Word First feature */
411 #define PJ4B_OUTSDNG_NC (1 << 29) /* Disable outstanding non cacheable rqst */
412 #define PJ4B_L1_REP_RR (1 << 30) /* L1 replacement - Strict round robin */
413 #define PJ4B_AUX_DBG_CTRL2 (PJ4B_SNOOP_DATA | PJ4B_CWF |\
414 PJ4B_OUTSDNG_NC | PJ4B_L1_REP_RR)
416 /* Auxiliary Functional Modes Control Register 0 */
417 #define PJ4B_SMP_CFB (1 << 1) /* Set SMP mode. Join the coherency fabric */
418 #define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */
419 #define PJ4B_BROADCAST_CACHE (1 << 8) /* Broadcast Cache and TLB maintenance */
421 /* Auxiliary Debug Modes Control 0 Register */
422 #define PJ4B_WFI_WFE (1 << 22) /* WFI/WFE - serve the DVM and back to idle */
424 /* Auxiliary Debug Modes Control 1 Register */
425 mrc p15, 1, r0, c15, c1, 1
426 orr r0, r0, #PJ4B_CLEAN_LINE
427 orr r0, r0, #PJ4B_INTER_PARITY
428 bic r0, r0, #PJ4B_STATIC_BP
429 mcr p15, 1, r0, c15, c1, 1
431 /* Auxiliary Debug Modes Control 2 Register */
432 mrc p15, 1, r0, c15, c1, 2
433 bic r0, r0, #PJ4B_FAST_LDR
434 orr r0, r0, #PJ4B_AUX_DBG_CTRL2
435 mcr p15, 1, r0, c15, c1, 2
437 /* Auxiliary Functional Modes Control Register 0 */
438 mrc p15, 1, r0, c15, c2, 0
439 #ifdef CONFIG_SMP
440 orr r0, r0, #PJ4B_SMP_CFB
441 #endif
442 orr r0, r0, #PJ4B_L1_PAR_CHK
443 orr r0, r0, #PJ4B_BROADCAST_CACHE
444 mcr p15, 1, r0, c15, c2, 0
446 /* Auxiliary Debug Modes Control 0 Register */
447 mrc p15, 1, r0, c15, c1, 0
448 orr r0, r0, #PJ4B_WFI_WFE
449 mcr p15, 1, r0, c15, c1, 0
451 #endif /* CONFIG_CPU_PJ4B */
453 __v7_setup:
454 adr r0, __v7_setup_stack_ptr
455 ldr r12, [r0]
456 add r12, r12, r0 @ the local stack
457 stmia r12, {r1-r6, lr} @ v7_invalidate_l1 touches r0-r6
458 bl v7_invalidate_l1
459 ldmia r12, {r1-r6, lr}
461 __v7_setup_cont:
462 and r0, r9, #0xff000000 @ ARM?
463 teq r0, #0x41000000
464 bne __errata_finish
465 and r3, r9, #0x00f00000 @ variant
466 and r6, r9, #0x0000000f @ revision
467 orr r6, r6, r3, lsr #20-4 @ combine variant and revision
468 ubfx r0, r9, #4, #12 @ primary part number
470 /* Cortex-A8 Errata */
471 ldr r10, =0x00000c08 @ Cortex-A8 primary part number
472 teq r0, r10
473 beq __ca8_errata
475 /* Cortex-A9 Errata */
476 ldr r10, =0x00000c09 @ Cortex-A9 primary part number
477 teq r0, r10
478 beq __ca9_errata
480 /* Cortex-A12 Errata */
481 ldr r10, =0x00000c0d @ Cortex-A12 primary part number
482 teq r0, r10
483 beq __ca12_errata
485 /* Cortex-A17 Errata */
486 ldr r10, =0x00000c0e @ Cortex-A17 primary part number
487 teq r0, r10
488 beq __ca17_errata
490 /* Cortex-A15 Errata */
491 ldr r10, =0x00000c0f @ Cortex-A15 primary part number
492 teq r0, r10
493 beq __ca15_errata
495 __errata_finish:
496 mov r10, #0
497 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
498 #ifdef CONFIG_MMU
499 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
500 v7_ttb_setup r10, r4, r5, r8, r3 @ TTBCR, TTBRx setup
501 ldr r3, =PRRR @ PRRR
502 ldr r6, =NMRR @ NMRR
503 mcr p15, 0, r3, c10, c2, 0 @ write PRRR
504 mcr p15, 0, r6, c10, c2, 1 @ write NMRR
505 #endif
506 dsb @ Complete invalidations
507 #ifndef CONFIG_ARM_THUMBEE
508 mrc p15, 0, r0, c0, c1, 0 @ read ID_PFR0 for ThumbEE
509 and r0, r0, #(0xf << 12) @ ThumbEE enabled field
510 teq r0, #(1 << 12) @ check if ThumbEE is present
511 bne 1f
512 mov r3, #0
513 mcr p14, 6, r3, c1, c0, 0 @ Initialize TEEHBR to 0
514 mrc p14, 6, r0, c0, c0, 0 @ load TEECR
515 orr r0, r0, #1 @ set the 1st bit in order to
516 mcr p14, 6, r0, c0, c0, 0 @ stop userspace TEEHBR access
517 1:
518 #endif
519 adr r3, v7_crval
520 ldmia r3, {r3, r6}
521 ARM_BE8(orr r6, r6, #1 << 25) @ big-endian page tables
522 #ifdef CONFIG_SWP_EMULATE
523 orr r3, r3, #(1 << 10) @ set SW bit in "clear"
524 bic r6, r6, #(1 << 10) @ clear it in "mmuset"
525 #endif
526 mrc p15, 0, r0, c1, c0, 0 @ read control register
527 bic r0, r0, r3 @ clear bits them
528 orr r0, r0, r6 @ set them
529 THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
530 ret lr @ return to head.S:__ret
532 .align 2
533 __v7_setup_stack_ptr:
534 .word PHYS_RELATIVE(__v7_setup_stack, .)
535 ENDPROC(__v7_setup)
537 .bss
538 .align 2
539 __v7_setup_stack:
540 .space 4 * 7 @ 7 registers
542 __INITDATA
544 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
545 define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
546 #ifndef CONFIG_ARM_LPAE
547 define_processor_functions ca8, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
548 define_processor_functions ca9mp, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
549 #endif
550 #ifdef CONFIG_CPU_PJ4B
551 define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
552 #endif
554 .section ".rodata"
556 string cpu_arch_name, "armv7"
557 string cpu_elf_name, "v7"
558 .align
560 .section ".proc.info.init", #alloc
562 /*
563 * Standard v7 proc info content
564 */
565 .macro __v7_proc name, initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0, proc_fns = v7_processor_functions
566 ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
567 PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags)
568 ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
569 PMD_SECT_AF | PMD_FLAGS_UP | \mm_mmuflags)
570 .long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | \
571 PMD_SECT_AP_READ | PMD_SECT_AF | \io_mmuflags
572 initfn \initfunc, \name
573 .long cpu_arch_name
574 .long cpu_elf_name
575 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \
576 HWCAP_EDSP | HWCAP_TLS | \hwcaps
577 .long cpu_v7_name
578 .long \proc_fns
579 .long v7wbi_tlb_fns
580 .long v6_user_fns
581 .long v7_cache_fns
582 .endm
584 #ifndef CONFIG_ARM_LPAE
585 /*
586 * ARM Ltd. Cortex A5 processor.
587 */
588 .type __v7_ca5mp_proc_info, #object
589 __v7_ca5mp_proc_info:
590 .long 0x410fc050
591 .long 0xff0ffff0
592 __v7_proc __v7_ca5mp_proc_info, __v7_ca5mp_setup
593 .size __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
595 /*
596 * ARM Ltd. Cortex A9 processor.
597 */
598 .type __v7_ca9mp_proc_info, #object
599 __v7_ca9mp_proc_info:
600 .long 0x410fc090
601 .long 0xff0ffff0
602 __v7_proc __v7_ca9mp_proc_info, __v7_ca9mp_setup, proc_fns = ca9mp_processor_functions
603 .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
605 /*
606 * ARM Ltd. Cortex A8 processor.
607 */
608 .type __v7_ca8_proc_info, #object
609 __v7_ca8_proc_info:
610 .long 0x410fc080
611 .long 0xff0ffff0
612 __v7_proc __v7_ca8_proc_info, __v7_setup, proc_fns = ca8_processor_functions
613 .size __v7_ca8_proc_info, . - __v7_ca8_proc_info
615 #endif /* CONFIG_ARM_LPAE */
617 /*
618 * Marvell PJ4B processor.
619 */
620 #ifdef CONFIG_CPU_PJ4B
621 .type __v7_pj4b_proc_info, #object
622 __v7_pj4b_proc_info:
623 .long 0x560f5800
624 .long 0xff0fff00
625 __v7_proc __v7_pj4b_proc_info, __v7_pj4b_setup, proc_fns = pj4b_processor_functions
626 .size __v7_pj4b_proc_info, . - __v7_pj4b_proc_info
627 #endif
629 /*
630 * ARM Ltd. Cortex R7 processor.
631 */
632 .type __v7_cr7mp_proc_info, #object
633 __v7_cr7mp_proc_info:
634 .long 0x410fc170
635 .long 0xff0ffff0
636 __v7_proc __v7_cr7mp_proc_info, __v7_cr7mp_setup
637 .size __v7_cr7mp_proc_info, . - __v7_cr7mp_proc_info
639 /*
640 * ARM Ltd. Cortex A7 processor.
641 */
642 .type __v7_ca7mp_proc_info, #object
643 __v7_ca7mp_proc_info:
644 .long 0x410fc070
645 .long 0xff0ffff0
646 __v7_proc __v7_ca7mp_proc_info, __v7_ca7mp_setup
647 .size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
649 /*
650 * ARM Ltd. Cortex A12 processor.
651 */
652 .type __v7_ca12mp_proc_info, #object
653 __v7_ca12mp_proc_info:
654 .long 0x410fc0d0
655 .long 0xff0ffff0
656 __v7_proc __v7_ca12mp_proc_info, __v7_ca12mp_setup
657 .size __v7_ca12mp_proc_info, . - __v7_ca12mp_proc_info
659 /*
660 * ARM Ltd. Cortex A15 processor.
661 */
662 .type __v7_ca15mp_proc_info, #object
663 __v7_ca15mp_proc_info:
664 .long 0x410fc0f0
665 .long 0xff0ffff0
666 __v7_proc __v7_ca15mp_proc_info, __v7_ca15mp_setup
667 .size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
669 /*
670 * Broadcom Corporation Brahma-B15 processor.
671 */
672 .type __v7_b15mp_proc_info, #object
673 __v7_b15mp_proc_info:
674 .long 0x420f00f0
675 .long 0xff0ffff0
676 __v7_proc __v7_b15mp_proc_info, __v7_b15mp_setup
677 .size __v7_b15mp_proc_info, . - __v7_b15mp_proc_info
679 /*
680 * ARM Ltd. Cortex A17 processor.
681 */
682 .type __v7_ca17mp_proc_info, #object
683 __v7_ca17mp_proc_info:
684 .long 0x410fc0e0
685 .long 0xff0ffff0
686 __v7_proc __v7_ca17mp_proc_info, __v7_ca17mp_setup
687 .size __v7_ca17mp_proc_info, . - __v7_ca17mp_proc_info
689 /*
690 * Qualcomm Inc. Krait processors.
691 */
692 .type __krait_proc_info, #object
693 __krait_proc_info:
694 .long 0x510f0400 @ Required ID value
695 .long 0xff0ffc00 @ Mask for ID
696 /*
697 * Some Krait processors don't indicate support for SDIV and UDIV
698 * instructions in the ARM instruction set, even though they actually
699 * do support them. They also don't indicate support for fused multiply
700 * instructions even though they actually do support them.
701 */
702 __v7_proc __krait_proc_info, __v7_setup, hwcaps = HWCAP_IDIV | HWCAP_VFPv4
703 .size __krait_proc_info, . - __krait_proc_info
705 /*
706 * Match any ARMv7 processor core.
707 */
708 .type __v7_proc_info, #object
709 __v7_proc_info:
710 .long 0x000f0000 @ Required ID value
711 .long 0x000f0000 @ Mask for ID
712 __v7_proc __v7_proc_info, __v7_setup
713 .size __v7_proc_info, . - __v7_proc_info