1 #ifndef __ASM_ALTERNATIVE_H
2 #define __ASM_ALTERNATIVE_H
4 #include <asm/cpucaps.h>
9 #include <linux/init.h>
10 #include <linux/types.h>
11 #include <linux/stddef.h>
12 #include <linux/stringify.h>
15 s32 orig_offset
; /* offset to original instruction */
16 s32 alt_offset
; /* offset to replacement instruction */
17 u16 cpufeature
; /* cpufeature bit set for replacement */
18 u8 orig_len
; /* size of original instruction(s) */
19 u8 alt_len
; /* size of new instruction(s), <= orig_len */
22 void __init
apply_alternatives_all(void);
23 void apply_alternatives(void *start
, size_t length
);
25 #define ALTINSTR_ENTRY(feature) \
26 " .word 661b - .\n" /* label */ \
27 " .word 663f - .\n" /* new instruction */ \
28 " .hword " __stringify(feature) "\n" /* feature bit */ \
29 " .byte 662b-661b\n" /* source len */ \
30 " .byte 664f-663f\n" /* replacement len */
33 * alternative assembly primitive:
35 * If any of these .org directive fail, it means that insn1 and insn2
36 * don't have the same length. This used to be written as
38 * .if ((664b-663b) != (662b-661b))
39 * .error "Alternatives instruction length mismatch"
42 * but most assemblers die if insn1 or insn2 have a .inst. This should
43 * be fixed in a binutils release posterior to 2.25.51.0.2 (anything
44 * containing commit 4e4d08cf7399b606 or c1baaddf8861).
46 #define __ALTERNATIVE_CFG(oldinstr, newinstr, feature, cfg_enabled) \
47 ".if "__stringify(cfg_enabled)" == 1\n" \
51 ".pushsection .altinstructions,\"a\"\n" \
52 ALTINSTR_ENTRY(feature) \
54 ".pushsection .altinstr_replacement, \"a\"\n" \
59 ".org . - (664b-663b) + (662b-661b)\n\t" \
60 ".org . - (662b-661b) + (664b-663b)\n" \
63 #define _ALTERNATIVE_CFG(oldinstr, newinstr, feature, cfg, ...) \
64 __ALTERNATIVE_CFG(oldinstr, newinstr, feature, IS_ENABLED(cfg))
68 #include <asm/assembler.h>
70 .macro altinstruction_entry orig_offset alt_offset feature orig_len alt_len
71 .word \orig_offset
- .
78 .macro alternative_insn insn1
, insn2
, cap
, enable
= 1
81 662: .pushsection
.altinstructions
, "a"
82 altinstruction_entry
661b
, 663f
, \cap
, 662b
-661b
, 664f
-663f
84 .pushsection
.altinstr_replacement
, "ax"
87 .org
. - (664b
-663b
) + (662b
-661b
)
88 .org
. - (662b
-661b
) + (664b
-663b
)
93 * Alternative sequences
95 * The code for the case where the capability is not present will be
96 * assembled and linked as normal. There are no restrictions on this
99 * The code for the case where the capability is present will be
100 * assembled into a special section to be used for dynamic patching.
101 * Code for that case must:
103 * 1. Be exactly the same length (in bytes) as the default code
106 * 2. Not contain a branch target that is used outside of the
107 * alternative sequence it is defined in (branches into an
108 * alternative sequence are not fixed up).
112 * Begin an alternative code sequence.
114 .macro alternative_if_not cap
115 .set
.Lasm_alt_mode
, 0
116 .pushsection
.altinstructions
, "a"
117 altinstruction_entry
661f
, 663f
, \cap
, 662f
-661f
, 664f
-663f
122 .macro alternative_if cap
123 .set
.Lasm_alt_mode
, 1
124 .pushsection
.altinstructions
, "a"
125 altinstruction_entry
663f
, 661f
, \cap
, 664f
-663f
, 662f
-661f
127 .pushsection
.altinstr_replacement
, "ax"
128 .align
2 /* So GAS knows label 661 is suitably aligned */
133 * Provide the other half of the alternative code sequence.
135 .macro alternative_else
137 .if .Lasm_alt_mode
==0
138 .pushsection
.altinstr_replacement
, "ax"
146 * Complete an alternative code sequence.
148 .macro alternative_endif
150 .if .Lasm_alt_mode
==0
153 .org
. - (664b
-663b
) + (662b
-661b
)
154 .org
. - (662b
-661b
) + (664b
-663b
)
158 * Provides a trivial alternative or default sequence consisting solely
159 * of NOPs. The number of NOPs is chosen automatically to match the
162 .macro alternative_else_nop_endif
164 nops (662b
-661b
) / AARCH64_INSN_SIZE
168 #define _ALTERNATIVE_CFG(insn1, insn2, cap, cfg, ...) \
169 alternative_insn insn1, insn2, cap, IS_ENABLED(cfg)
171 .macro user_alt
, label
, oldinstr
, newinstr
, cond
172 9999: alternative_insn
"\oldinstr", "\newinstr", \cond
173 _ASM_EXTABLE
9999b
, \label
177 * Generate the assembly for UAO alternatives with exception table entries.
178 * This is complicated as there is no post-increment or pair versions of the
179 * unprivileged instructions, and USER() only works for single instructions.
181 #ifdef CONFIG_ARM64_UAO
182 .macro uao_ldp l
, reg1
, reg2
, addr
, post_inc
183 alternative_if_not ARM64_HAS_UAO
184 8888: ldp
\reg
1, \reg
2, [\addr
], \post_inc
;
189 ldtr
\reg
2, [\addr
, #8];
190 add
\addr
, \addr
, \post_inc
;
193 _asm_extable
8888b
,\l
;
194 _asm_extable
8889b
,\l
;
197 .macro uao_stp l
, reg1
, reg2
, addr
, post_inc
198 alternative_if_not ARM64_HAS_UAO
199 8888: stp
\reg
1, \reg
2, [\addr
], \post_inc
;
204 sttr
\reg
2, [\addr
, #8];
205 add
\addr
, \addr
, \post_inc
;
208 _asm_extable
8888b
,\l
;
209 _asm_extable
8889b
,\l
;
212 .macro uao_user_alternative l
, inst
, alt_inst
, reg
, addr
, post_inc
213 alternative_if_not ARM64_HAS_UAO
214 8888: \inst
\reg
, [\addr
], \post_inc
;
217 \alt_inst
\reg
, [\addr
];
218 add
\addr
, \addr
, \post_inc
;
221 _asm_extable
8888b
,\l
;
224 .macro uao_ldp l
, reg1
, reg2
, addr
, post_inc
225 USER(\l
, ldp
\reg
1, \reg
2, [\addr
], \post_inc
)
227 .macro uao_stp l
, reg1
, reg2
, addr
, post_inc
228 USER(\l
, stp
\reg
1, \reg
2, [\addr
], \post_inc
)
230 .macro uao_user_alternative l
, inst
, alt_inst
, reg
, addr
, post_inc
231 USER(\l
, \inst
\reg
, [\addr
], \post_inc
)
235 #endif /* __ASSEMBLY__ */
238 * Usage: asm(ALTERNATIVE(oldinstr, newinstr, feature));
240 * Usage: asm(ALTERNATIVE(oldinstr, newinstr, feature, CONFIG_FOO));
241 * N.B. If CONFIG_FOO is specified, but not selected, the whole block
242 * will be omitted, including oldinstr.
244 #define ALTERNATIVE(oldinstr, newinstr, ...) \
245 _ALTERNATIVE_CFG(oldinstr, newinstr, __VA_ARGS__, 1)
247 #endif /* __ASM_ALTERNATIVE_H */