| blob | 4fb6ccd886d11ef219efe411b1f712e31167d943 |
1 /*
2 * Low-level CPU initialisation
3 * Based on arch/arm/kernel/head.S
4 *
5 * Copyright (C) 1994-2002 Russell King
6 * Copyright (C) 2003-2012 ARM Ltd.
7 * Authors: Catalin Marinas <catalin.marinas@arm.com>
8 * Will Deacon <will.deacon@arm.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 */
23 #include <linux/linkage.h>
24 #include <linux/init.h>
25 #include <linux/irqchip/arm-gic-v3.h>
27 #include <asm/assembler.h>
28 #include <asm/boot.h>
29 #include <asm/ptrace.h>
30 #include <asm/asm-offsets.h>
31 #include <asm/cache.h>
32 #include <asm/cputype.h>
33 #include <asm/elf.h>
34 #include <asm/kernel-pgtable.h>
35 #include <asm/kvm_arm.h>
36 #include <asm/memory.h>
37 #include <asm/pgtable-hwdef.h>
38 #include <asm/pgtable.h>
39 #include <asm/page.h>
40 #include <asm/smp.h>
41 #include <asm/sysreg.h>
42 #include <asm/thread_info.h>
43 #include <asm/virt.h>
45 #define __PHYS_OFFSET (KERNEL_START - TEXT_OFFSET)
47 #if (TEXT_OFFSET & 0xfff) != 0
48 #error TEXT_OFFSET must be at least 4KB aligned
49 #elif (PAGE_OFFSET & 0x1fffff) != 0
50 #error PAGE_OFFSET must be at least 2MB aligned
51 #elif TEXT_OFFSET > 0x1fffff
52 #error TEXT_OFFSET must be less than 2MB
53 #endif
55 /*
56 * Kernel startup entry point.
57 * ---------------------------
58 *
59 * The requirements are:
60 * MMU = off, D-cache = off, I-cache = on or off,
61 * x0 = physical address to the FDT blob.
62 *
63 * This code is mostly position independent so you call this at
64 * __pa(PAGE_OFFSET + TEXT_OFFSET).
65 *
66 * Note that the callee-saved registers are used for storing variables
67 * that are useful before the MMU is enabled. The allocations are described
68 * in the entry routines.
69 */
70 __HEAD
71 _head:
72 /*
73 * DO NOT MODIFY. Image header expected by Linux boot-loaders.
74 */
75 #ifdef CONFIG_EFI
76 /*
77 * This add instruction has no meaningful effect except that
78 * its opcode forms the magic "MZ" signature required by UEFI.
79 */
80 add x13, x18, #0x16
81 b stext
82 #else
83 b stext // branch to kernel start, magic
84 .long 0 // reserved
85 #endif
86 le64sym _kernel_offset_le // Image load offset from start of RAM, little-endian
87 le64sym _kernel_size_le // Effective size of kernel image, little-endian
88 le64sym _kernel_flags_le // Informative flags, little-endian
89 .quad 0 // reserved
90 .quad 0 // reserved
91 .quad 0 // reserved
92 .byte 0x41 // Magic number, "ARM\x64"
93 .byte 0x52
94 .byte 0x4d
95 .byte 0x64
96 #ifdef CONFIG_EFI
97 .long pe_header - _head // Offset to the PE header.
98 #else
99 .word 0 // reserved
100 #endif
102 #ifdef CONFIG_EFI
103 .align 3
104 pe_header:
105 .ascii "PE"
106 .short 0
107 coff_header:
108 .short 0xaa64 // AArch64
109 .short 2 // nr_sections
110 .long 0 // TimeDateStamp
111 .long 0 // PointerToSymbolTable
112 .long 1 // NumberOfSymbols
113 .short section_table - optional_header // SizeOfOptionalHeader
114 .short 0x206 // Characteristics.
115 // IMAGE_FILE_DEBUG_STRIPPED |
116 // IMAGE_FILE_EXECUTABLE_IMAGE |
117 // IMAGE_FILE_LINE_NUMS_STRIPPED
118 optional_header:
119 .short 0x20b // PE32+ format
120 .byte 0x02 // MajorLinkerVersion
121 .byte 0x14 // MinorLinkerVersion
122 .long _end - efi_header_end // SizeOfCode
123 .long 0 // SizeOfInitializedData
124 .long 0 // SizeOfUninitializedData
125 .long __efistub_entry - _head // AddressOfEntryPoint
126 .long efi_header_end - _head // BaseOfCode
128 extra_header_fields:
129 .quad 0 // ImageBase
130 .long 0x1000 // SectionAlignment
131 .long PECOFF_FILE_ALIGNMENT // FileAlignment
132 .short 0 // MajorOperatingSystemVersion
133 .short 0 // MinorOperatingSystemVersion
134 .short 0 // MajorImageVersion
135 .short 0 // MinorImageVersion
136 .short 0 // MajorSubsystemVersion
137 .short 0 // MinorSubsystemVersion
138 .long 0 // Win32VersionValue
140 .long _end - _head // SizeOfImage
142 // Everything before the kernel image is considered part of the header
143 .long efi_header_end - _head // SizeOfHeaders
144 .long 0 // CheckSum
145 .short 0xa // Subsystem (EFI application)
146 .short 0 // DllCharacteristics
147 .quad 0 // SizeOfStackReserve
148 .quad 0 // SizeOfStackCommit
149 .quad 0 // SizeOfHeapReserve
150 .quad 0 // SizeOfHeapCommit
151 .long 0 // LoaderFlags
152 .long (section_table - .) / 8 // NumberOfRvaAndSizes
154 .quad 0 // ExportTable
155 .quad 0 // ImportTable
156 .quad 0 // ResourceTable
157 .quad 0 // ExceptionTable
158 .quad 0 // CertificationTable
159 .quad 0 // BaseRelocationTable
161 #ifdef CONFIG_DEBUG_EFI
162 .long efi_debug_table - _head // DebugTable
163 .long efi_debug_table_size
164 #endif
166 // Section table
167 section_table:
169 /*
170 * The EFI application loader requires a relocation section
171 * because EFI applications must be relocatable. This is a
172 * dummy section as far as we are concerned.
173 */
174 .ascii ".reloc"
175 .byte 0
176 .byte 0 // end of 0 padding of section name
177 .long 0
178 .long 0
179 .long 0 // SizeOfRawData
180 .long 0 // PointerToRawData
181 .long 0 // PointerToRelocations
182 .long 0 // PointerToLineNumbers
183 .short 0 // NumberOfRelocations
184 .short 0 // NumberOfLineNumbers
185 .long 0x42100040 // Characteristics (section flags)
188 .ascii ".text"
189 .byte 0
190 .byte 0
191 .byte 0 // end of 0 padding of section name
192 .long _end - efi_header_end // VirtualSize
193 .long efi_header_end - _head // VirtualAddress
194 .long _edata - efi_header_end // SizeOfRawData
195 .long efi_header_end - _head // PointerToRawData
197 .long 0 // PointerToRelocations (0 for executables)
198 .long 0 // PointerToLineNumbers (0 for executables)
199 .short 0 // NumberOfRelocations (0 for executables)
200 .short 0 // NumberOfLineNumbers (0 for executables)
201 .long 0xe0500020 // Characteristics (section flags)
203 #ifdef CONFIG_DEBUG_EFI
204 /*
205 * The debug table is referenced via its Relative Virtual Address (RVA),
206 * which is only defined for those parts of the image that are covered
207 * by a section declaration. Since this header is not covered by any
208 * section, the debug table must be emitted elsewhere. So stick it in
209 * the .init.rodata section instead.
210 *
211 * Note that the EFI debug entry itself may legally have a zero RVA,
212 * which means we can simply put it right after the section headers.
213 */
214 __INITRODATA
216 .align 2
217 efi_debug_table:
218 // EFI_IMAGE_DEBUG_DIRECTORY_ENTRY
219 .long 0 // Characteristics
220 .long 0 // TimeDateStamp
221 .short 0 // MajorVersion
222 .short 0 // MinorVersion
223 .long 2 // Type == EFI_IMAGE_DEBUG_TYPE_CODEVIEW
224 .long efi_debug_entry_size // SizeOfData
225 .long 0 // RVA
226 .long efi_debug_entry - _head // FileOffset
228 .set efi_debug_table_size, . - efi_debug_table
229 .previous
231 efi_debug_entry:
232 // EFI_IMAGE_DEBUG_CODEVIEW_NB10_ENTRY
233 .ascii "NB10" // Signature
234 .long 0 // Unknown
235 .long 0 // Unknown2
236 .long 0 // Unknown3
238 .asciz VMLINUX_PATH
240 .set efi_debug_entry_size, . - efi_debug_entry
241 #endif
243 /*
244 * EFI will load .text onwards at the 4k section alignment
245 * described in the PE/COFF header. To ensure that instruction
246 * sequences using an adrp and a :lo12: immediate will function
247 * correctly at this alignment, we must ensure that .text is
248 * placed at a 4k boundary in the Image to begin with.
249 */
250 .align 12
251 efi_header_end:
252 #endif
254 __INIT
256 /*
257 * The following callee saved general purpose registers are used on the
258 * primary lowlevel boot path:
259 *
260 * Register Scope Purpose
261 * x21 stext() .. start_kernel() FDT pointer passed at boot in x0
262 * x23 stext() .. start_kernel() physical misalignment/KASLR offset
263 * x28 __create_page_tables() callee preserved temp register
264 * x19/x20 __primary_switch() callee preserved temp registers
265 */
266 ENTRY(stext)
267 bl preserve_boot_args
268 bl el2_setup // Drop to EL1, w0=cpu_boot_mode
269 adrp x23, __PHYS_OFFSET
270 and x23, x23, MIN_KIMG_ALIGN - 1 // KASLR offset, defaults to 0
271 bl set_cpu_boot_mode_flag
272 bl __create_page_tables
273 /*
274 * The following calls CPU setup code, see arch/arm64/mm/proc.S for
275 * details.
276 * On return, the CPU will be ready for the MMU to be turned on and
277 * the TCR will have been set.
278 */
279 bl __cpu_setup // initialise processor
280 b __primary_switch
281 ENDPROC(stext)
283 /*
284 * Preserve the arguments passed by the bootloader in x0 .. x3
285 */
286 preserve_boot_args:
287 mov x21, x0 // x21=FDT
289 adr_l x0, boot_args // record the contents of
290 stp x21, x1, [x0] // x0 .. x3 at kernel entry
291 stp x2, x3, [x0, #16]
293 dmb sy // needed before dc ivac with
294 // MMU off
296 add x1, x0, #0x20 // 4 x 8 bytes
297 b __inval_cache_range // tail call
298 ENDPROC(preserve_boot_args)
300 /*
301 * Macro to create a table entry to the next page.
302 *
303 * tbl: page table address
304 * virt: virtual address
305 * shift: #imm page table shift
306 * ptrs: #imm pointers per table page
307 *
308 * Preserves: virt
309 * Corrupts: tmp1, tmp2
310 * Returns: tbl -> next level table page address
311 */
312 .macro create_table_entry, tbl, virt, shift, ptrs, tmp1, tmp2
313 lsr \tmp1, \virt, #\shift
314 and \tmp1, \tmp1, #\ptrs - 1 // table index
315 add \tmp2, \tbl, #PAGE_SIZE
316 orr \tmp2, \tmp2, #PMD_TYPE_TABLE // address of next table and entry type
317 str \tmp2, [\tbl, \tmp1, lsl #3]
318 add \tbl, \tbl, #PAGE_SIZE // next level table page
319 .endm
321 /*
322 * Macro to populate the PGD (and possibily PUD) for the corresponding
323 * block entry in the next level (tbl) for the given virtual address.
324 *
325 * Preserves: tbl, next, virt
326 * Corrupts: tmp1, tmp2
327 */
328 .macro create_pgd_entry, tbl, virt, tmp1, tmp2
329 create_table_entry \tbl, \virt, PGDIR_SHIFT, PTRS_PER_PGD, \tmp1, \tmp2
330 #if SWAPPER_PGTABLE_LEVELS > 3
331 create_table_entry \tbl, \virt, PUD_SHIFT, PTRS_PER_PUD, \tmp1, \tmp2
332 #endif
333 #if SWAPPER_PGTABLE_LEVELS > 2
334 create_table_entry \tbl, \virt, SWAPPER_TABLE_SHIFT, PTRS_PER_PTE, \tmp1, \tmp2
335 #endif
336 .endm
338 /*
339 * Macro to populate block entries in the page table for the start..end
340 * virtual range (inclusive).
341 *
342 * Preserves: tbl, flags
343 * Corrupts: phys, start, end, pstate
344 */
345 .macro create_block_map, tbl, flags, phys, start, end
346 lsr \phys, \phys, #SWAPPER_BLOCK_SHIFT
347 lsr \start, \start, #SWAPPER_BLOCK_SHIFT
348 and \start, \start, #PTRS_PER_PTE - 1 // table index
349 orr \phys, \flags, \phys, lsl #SWAPPER_BLOCK_SHIFT // table entry
350 lsr \end, \end, #SWAPPER_BLOCK_SHIFT
351 and \end, \end, #PTRS_PER_PTE - 1 // table end index
352 9999: str \phys, [\tbl, \start, lsl #3] // store the entry
353 add \start, \start, #1 // next entry
354 add \phys, \phys, #SWAPPER_BLOCK_SIZE // next block
355 cmp \start, \end
356 b.ls 9999b
357 .endm
359 /*
360 * Setup the initial page tables. We only setup the barest amount which is
361 * required to get the kernel running. The following sections are required:
362 * - identity mapping to enable the MMU (low address, TTBR0)
363 * - first few MB of the kernel linear mapping to jump to once the MMU has
364 * been enabled
365 */
366 __create_page_tables:
367 mov x28, lr
369 /*
370 * Invalidate the idmap and swapper page tables to avoid potential
371 * dirty cache lines being evicted.
372 */
373 adrp x0, idmap_pg_dir
374 adrp x1, swapper_pg_dir + SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE
375 bl __inval_cache_range
377 /*
378 * Clear the idmap and swapper page tables.
379 */
380 adrp x0, idmap_pg_dir
381 adrp x6, swapper_pg_dir + SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE
382 1: stp xzr, xzr, [x0], #16
383 stp xzr, xzr, [x0], #16
384 stp xzr, xzr, [x0], #16
385 stp xzr, xzr, [x0], #16
386 cmp x0, x6
387 b.lo 1b
389 mov x7, SWAPPER_MM_MMUFLAGS
391 /*
392 * Create the identity mapping.
393 */
394 adrp x0, idmap_pg_dir
395 adrp x3, __idmap_text_start // __pa(__idmap_text_start)
397 #ifndef CONFIG_ARM64_VA_BITS_48
398 #define EXTRA_SHIFT (PGDIR_SHIFT + PAGE_SHIFT - 3)
399 #define EXTRA_PTRS (1 << (48 - EXTRA_SHIFT))
401 /*
402 * If VA_BITS < 48, it may be too small to allow for an ID mapping to be
403 * created that covers system RAM if that is located sufficiently high
404 * in the physical address space. So for the ID map, use an extended
405 * virtual range in that case, by configuring an additional translation
406 * level.
407 * First, we have to verify our assumption that the current value of
408 * VA_BITS was chosen such that all translation levels are fully
409 * utilised, and that lowering T0SZ will always result in an additional
410 * translation level to be configured.
411 */
412 #if VA_BITS != EXTRA_SHIFT
413 #error "Mismatch between VA_BITS and page size/number of translation levels"
414 #endif
416 /*
417 * Calculate the maximum allowed value for TCR_EL1.T0SZ so that the
418 * entire ID map region can be mapped. As T0SZ == (64 - #bits used),
419 * this number conveniently equals the number of leading zeroes in
420 * the physical address of __idmap_text_end.
421 */
422 adrp x5, __idmap_text_end
423 clz x5, x5
424 cmp x5, TCR_T0SZ(VA_BITS) // default T0SZ small enough?
425 b.ge 1f // .. then skip additional level
427 adr_l x6, idmap_t0sz
428 str x5, [x6]
429 dmb sy
430 dc ivac, x6 // Invalidate potentially stale cache line
432 create_table_entry x0, x3, EXTRA_SHIFT, EXTRA_PTRS, x5, x6
433 1:
434 #endif
436 create_pgd_entry x0, x3, x5, x6
437 mov x5, x3 // __pa(__idmap_text_start)
438 adr_l x6, __idmap_text_end // __pa(__idmap_text_end)
439 create_block_map x0, x7, x3, x5, x6
441 /*
442 * Map the kernel image (starting with PHYS_OFFSET).
443 */
444 adrp x0, swapper_pg_dir
445 mov_q x5, KIMAGE_VADDR + TEXT_OFFSET // compile time __va(_text)
446 add x5, x5, x23 // add KASLR displacement
447 create_pgd_entry x0, x5, x3, x6
448 adrp x6, _end // runtime __pa(_end)
449 adrp x3, _text // runtime __pa(_text)
450 sub x6, x6, x3 // _end - _text
451 add x6, x6, x5 // runtime __va(_end)
452 create_block_map x0, x7, x3, x5, x6
454 /*
455 * Since the page tables have been populated with non-cacheable
456 * accesses (MMU disabled), invalidate the idmap and swapper page
457 * tables again to remove any speculatively loaded cache lines.
458 */
459 adrp x0, idmap_pg_dir
460 adrp x1, swapper_pg_dir + SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE
461 dmb sy
462 bl __inval_cache_range
464 ret x28
465 ENDPROC(__create_page_tables)
466 .ltorg
468 /*
469 * The following fragment of code is executed with the MMU enabled.
470 *
471 * x0 = __PHYS_OFFSET
472 */
473 __primary_switched:
474 adrp x4, init_thread_union
475 add sp, x4, #THREAD_SIZE
476 adr_l x5, init_task
477 msr sp_el0, x5 // Save thread_info
479 adr_l x8, vectors // load VBAR_EL1 with virtual
480 msr vbar_el1, x8 // vector table address
481 isb
483 stp xzr, x30, [sp, #-16]!
484 mov x29, sp
486 str_l x21, __fdt_pointer, x5 // Save FDT pointer
488 ldr_l x4, kimage_vaddr // Save the offset between
489 sub x4, x4, x0 // the kernel virtual and
490 str_l x4, kimage_voffset, x5 // physical mappings
492 // Clear BSS
493 adr_l x0, __bss_start
494 mov x1, xzr
495 adr_l x2, __bss_stop
496 sub x2, x2, x0
497 bl __pi_memset
498 dsb ishst // Make zero page visible to PTW
500 #ifdef CONFIG_KASAN
501 bl kasan_early_init
502 #endif
503 #ifdef CONFIG_RANDOMIZE_BASE
504 tst x23, ~(MIN_KIMG_ALIGN - 1) // already running randomized?
505 b.ne 0f
506 mov x0, x21 // pass FDT address in x0
507 mov x1, x23 // pass modulo offset in x1
508 bl kaslr_early_init // parse FDT for KASLR options
509 cbz x0, 0f // KASLR disabled? just proceed
510 orr x23, x23, x0 // record KASLR offset
511 ldp x29, x30, [sp], #16 // we must enable KASLR, return
512 ret // to __primary_switch()
513 0:
514 #endif
515 b start_kernel
516 ENDPROC(__primary_switched)
518 /*
519 * end early head section, begin head code that is also used for
520 * hotplug and needs to have the same protections as the text region
521 */
522 .section ".idmap.text","ax"
524 ENTRY(kimage_vaddr)
525 .quad _text - TEXT_OFFSET
527 /*
528 * If we're fortunate enough to boot at EL2, ensure that the world is
529 * sane before dropping to EL1.
530 *
531 * Returns either BOOT_CPU_MODE_EL1 or BOOT_CPU_MODE_EL2 in w0 if
532 * booted in EL1 or EL2 respectively.
533 */
534 ENTRY(el2_setup)
535 mrs x0, CurrentEL
536 cmp x0, #CurrentEL_EL2
537 b.ne 1f
538 mrs x0, sctlr_el2
539 CPU_BE( orr x0, x0, #(1 << 25) ) // Set the EE bit for EL2
540 CPU_LE( bic x0, x0, #(1 << 25) ) // Clear the EE bit for EL2
541 msr sctlr_el2, x0
542 b 2f
543 1: mrs x0, sctlr_el1
544 CPU_BE( orr x0, x0, #(3 << 24) ) // Set the EE and E0E bits for EL1
545 CPU_LE( bic x0, x0, #(3 << 24) ) // Clear the EE and E0E bits for EL1
546 msr sctlr_el1, x0
547 mov w0, #BOOT_CPU_MODE_EL1 // This cpu booted in EL1
548 isb
549 ret
551 2:
552 #ifdef CONFIG_ARM64_VHE
553 /*
554 * Check for VHE being present. For the rest of the EL2 setup,
555 * x2 being non-zero indicates that we do have VHE, and that the
556 * kernel is intended to run at EL2.
557 */
558 mrs x2, id_aa64mmfr1_el1
559 ubfx x2, x2, #8, #4
560 #else
561 mov x2, xzr
562 #endif
564 /* Hyp configuration. */
565 mov x0, #HCR_RW // 64-bit EL1
566 cbz x2, set_hcr
567 orr x0, x0, #HCR_TGE // Enable Host Extensions
568 orr x0, x0, #HCR_E2H
569 set_hcr:
570 msr hcr_el2, x0
571 isb
573 /*
574 * Allow Non-secure EL1 and EL0 to access physical timer and counter.
575 * This is not necessary for VHE, since the host kernel runs in EL2,
576 * and EL0 accesses are configured in the later stage of boot process.
577 * Note that when HCR_EL2.E2H == 1, CNTHCTL_EL2 has the same bit layout
578 * as CNTKCTL_EL1, and CNTKCTL_EL1 accessing instructions are redefined
579 * to access CNTHCTL_EL2. This allows the kernel designed to run at EL1
580 * to transparently mess with the EL0 bits via CNTKCTL_EL1 access in
581 * EL2.
582 */
583 cbnz x2, 1f
584 mrs x0, cnthctl_el2
585 orr x0, x0, #3 // Enable EL1 physical timers
586 msr cnthctl_el2, x0
587 1:
588 msr cntvoff_el2, xzr // Clear virtual offset
590 #ifdef CONFIG_ARM_GIC_V3
591 /* GICv3 system register access */
592 mrs x0, id_aa64pfr0_el1
593 ubfx x0, x0, #24, #4
594 cmp x0, #1
595 b.ne 3f
597 mrs_s x0, ICC_SRE_EL2
598 orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1
599 orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1
600 msr_s ICC_SRE_EL2, x0
601 isb // Make sure SRE is now set
602 mrs_s x0, ICC_SRE_EL2 // Read SRE back,
603 tbz x0, #0, 3f // and check that it sticks
604 msr_s ICH_HCR_EL2, xzr // Reset ICC_HCR_EL2 to defaults
606 3:
607 #endif
609 /* Populate ID registers. */
610 mrs x0, midr_el1
611 mrs x1, mpidr_el1
612 msr vpidr_el2, x0
613 msr vmpidr_el2, x1
615 /*
616 * When VHE is not in use, early init of EL2 and EL1 needs to be
617 * done here.
618 * When VHE _is_ in use, EL1 will not be used in the host and
619 * requires no configuration, and all non-hyp-specific EL2 setup
620 * will be done via the _EL1 system register aliases in __cpu_setup.
621 */
622 cbnz x2, 1f
624 /* sctlr_el1 */
625 mov x0, #0x0800 // Set/clear RES{1,0} bits
626 CPU_BE( movk x0, #0x33d0, lsl #16 ) // Set EE and E0E on BE systems
627 CPU_LE( movk x0, #0x30d0, lsl #16 ) // Clear EE and E0E on LE systems
628 msr sctlr_el1, x0
630 /* Coprocessor traps. */
631 mov x0, #0x33ff
632 msr cptr_el2, x0 // Disable copro. traps to EL2
633 1:
635 #ifdef CONFIG_COMPAT
636 msr hstr_el2, xzr // Disable CP15 traps to EL2
637 #endif
639 /* EL2 debug */
640 mrs x1, id_aa64dfr0_el1 // Check ID_AA64DFR0_EL1 PMUVer
641 sbfx x0, x1, #8, #4
642 cmp x0, #1
643 b.lt 4f // Skip if no PMU present
644 mrs x0, pmcr_el0 // Disable debug access traps
645 ubfx x0, x0, #11, #5 // to EL2 and allow access to
646 4:
647 csel x3, xzr, x0, lt // all PMU counters from EL1
649 /* Statistical profiling */
650 ubfx x0, x1, #32, #4 // Check ID_AA64DFR0_EL1 PMSVer
651 cbz x0, 6f // Skip if SPE not present
652 cbnz x2, 5f // VHE?
653 mov x1, #(MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT)
654 orr x3, x3, x1 // If we don't have VHE, then
655 b 6f // use EL1&0 translation.
656 5: // For VHE, use EL2 translation
657 orr x3, x3, #MDCR_EL2_TPMS // and disable access from EL1
658 6:
659 msr mdcr_el2, x3 // Configure debug traps
661 /* Stage-2 translation */
662 msr vttbr_el2, xzr
664 cbz x2, install_el2_stub
666 mov w0, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2
667 isb
668 ret
670 install_el2_stub:
671 /* Hypervisor stub */
672 adr_l x0, __hyp_stub_vectors
673 msr vbar_el2, x0
675 /* spsr */
676 mov x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\
677 PSR_MODE_EL1h)
678 msr spsr_el2, x0
679 msr elr_el2, lr
680 mov w0, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2
681 eret
682 ENDPROC(el2_setup)
684 /*
685 * Sets the __boot_cpu_mode flag depending on the CPU boot mode passed
686 * in w0. See arch/arm64/include/asm/virt.h for more info.
687 */
688 set_cpu_boot_mode_flag:
689 adr_l x1, __boot_cpu_mode
690 cmp w0, #BOOT_CPU_MODE_EL2
691 b.ne 1f
692 add x1, x1, #4
693 1: str w0, [x1] // This CPU has booted in EL1
694 dmb sy
695 dc ivac, x1 // Invalidate potentially stale cache line
696 ret
697 ENDPROC(set_cpu_boot_mode_flag)
699 /*
700 * These values are written with the MMU off, but read with the MMU on.
701 * Writers will invalidate the corresponding address, discarding up to a
702 * 'Cache Writeback Granule' (CWG) worth of data. The linker script ensures
703 * sufficient alignment that the CWG doesn't overlap another section.
704 */
705 .pushsection ".mmuoff.data.write", "aw"
706 /*
707 * We need to find out the CPU boot mode long after boot, so we need to
708 * store it in a writable variable.
709 *
710 * This is not in .bss, because we set it sufficiently early that the boot-time
711 * zeroing of .bss would clobber it.
712 */
713 ENTRY(__boot_cpu_mode)
714 .long BOOT_CPU_MODE_EL2
715 .long BOOT_CPU_MODE_EL1
716 /*
717 * The booting CPU updates the failed status @__early_cpu_boot_status,
718 * with MMU turned off.
719 */
720 ENTRY(__early_cpu_boot_status)
721 .long 0
723 .popsection
725 /*
726 * This provides a "holding pen" for platforms to hold all secondary
727 * cores are held until we're ready for them to initialise.
728 */
729 ENTRY(secondary_holding_pen)
730 bl el2_setup // Drop to EL1, w0=cpu_boot_mode
731 bl set_cpu_boot_mode_flag
732 mrs x0, mpidr_el1
733 mov_q x1, MPIDR_HWID_BITMASK
734 and x0, x0, x1
735 adr_l x3, secondary_holding_pen_release
736 pen: ldr x4, [x3]
737 cmp x4, x0
738 b.eq secondary_startup
739 wfe
740 b pen
741 ENDPROC(secondary_holding_pen)
743 /*
744 * Secondary entry point that jumps straight into the kernel. Only to
745 * be used where CPUs are brought online dynamically by the kernel.
746 */
747 ENTRY(secondary_entry)
748 bl el2_setup // Drop to EL1
749 bl set_cpu_boot_mode_flag
750 b secondary_startup
751 ENDPROC(secondary_entry)
753 secondary_startup:
754 /*
755 * Common entry point for secondary CPUs.
756 */
757 bl __cpu_setup // initialise processor
758 bl __enable_mmu
759 ldr x8, =__secondary_switched
760 br x8
761 ENDPROC(secondary_startup)
763 __secondary_switched:
764 adr_l x5, vectors
765 msr vbar_el1, x5
766 isb
768 adr_l x0, secondary_data
769 ldr x1, [x0, #CPU_BOOT_STACK] // get secondary_data.stack
770 mov sp, x1
771 ldr x2, [x0, #CPU_BOOT_TASK]
772 msr sp_el0, x2
773 mov x29, #0
774 b secondary_start_kernel
775 ENDPROC(__secondary_switched)
777 /*
778 * The booting CPU updates the failed status @__early_cpu_boot_status,
779 * with MMU turned off.
780 *
781 * update_early_cpu_boot_status tmp, status
782 * - Corrupts tmp1, tmp2
783 * - Writes 'status' to __early_cpu_boot_status and makes sure
784 * it is committed to memory.
785 */
787 .macro update_early_cpu_boot_status status, tmp1, tmp2
788 mov \tmp2, #\status
789 adr_l \tmp1, __early_cpu_boot_status
790 str \tmp2, [\tmp1]
791 dmb sy
792 dc ivac, \tmp1 // Invalidate potentially stale cache line
793 .endm
795 /*
796 * Enable the MMU.
797 *
798 * x0 = SCTLR_EL1 value for turning on the MMU.
799 *
800 * Returns to the caller via x30/lr. This requires the caller to be covered
801 * by the .idmap.text section.
802 *
803 * Checks if the selected granule size is supported by the CPU.
804 * If it isn't, park the CPU
805 */
806 ENTRY(__enable_mmu)
807 mrs x1, ID_AA64MMFR0_EL1
808 ubfx x2, x1, #ID_AA64MMFR0_TGRAN_SHIFT, 4
809 cmp x2, #ID_AA64MMFR0_TGRAN_SUPPORTED
810 b.ne __no_granule_support
811 update_early_cpu_boot_status 0, x1, x2
812 adrp x1, idmap_pg_dir
813 adrp x2, swapper_pg_dir
814 msr ttbr0_el1, x1 // load TTBR0
815 msr ttbr1_el1, x2 // load TTBR1
816 isb
817 msr sctlr_el1, x0
818 isb
819 /*
820 * Invalidate the local I-cache so that any instructions fetched
821 * speculatively from the PoC are discarded, since they may have
822 * been dynamically patched at the PoU.
823 */
824 ic iallu
825 dsb nsh
826 isb
827 ret
828 ENDPROC(__enable_mmu)
830 __no_granule_support:
831 /* Indicate that this CPU can't boot and is stuck in the kernel */
832 update_early_cpu_boot_status CPU_STUCK_IN_KERNEL, x1, x2
833 1:
834 wfe
835 wfi
836 b 1b
837 ENDPROC(__no_granule_support)
839 #ifdef CONFIG_RELOCATABLE
840 __relocate_kernel:
841 /*
842 * Iterate over each entry in the relocation table, and apply the
843 * relocations in place.
844 */
845 ldr w9, =__rela_offset // offset to reloc table
846 ldr w10, =__rela_size // size of reloc table
848 mov_q x11, KIMAGE_VADDR // default virtual offset
849 add x11, x11, x23 // actual virtual offset
850 add x9, x9, x11 // __va(.rela)
851 add x10, x9, x10 // __va(.rela) + sizeof(.rela)
853 0: cmp x9, x10
854 b.hs 1f
855 ldp x11, x12, [x9], #24
856 ldr x13, [x9, #-8]
857 cmp w12, #R_AARCH64_RELATIVE
858 b.ne 0b
859 add x13, x13, x23 // relocate
860 str x13, [x11, x23]
861 b 0b
862 1: ret
863 ENDPROC(__relocate_kernel)
864 #endif
866 __primary_switch:
867 #ifdef CONFIG_RANDOMIZE_BASE
868 mov x19, x0 // preserve new SCTLR_EL1 value
869 mrs x20, sctlr_el1 // preserve old SCTLR_EL1 value
870 #endif
872 bl __enable_mmu
873 #ifdef CONFIG_RELOCATABLE
874 bl __relocate_kernel
875 #ifdef CONFIG_RANDOMIZE_BASE
876 ldr x8, =__primary_switched
877 adrp x0, __PHYS_OFFSET
878 blr x8
880 /*
881 * If we return here, we have a KASLR displacement in x23 which we need
882 * to take into account by discarding the current kernel mapping and
883 * creating a new one.
884 */
885 msr sctlr_el1, x20 // disable the MMU
886 isb
887 bl __create_page_tables // recreate kernel mapping
889 tlbi vmalle1 // Remove any stale TLB entries
890 dsb nsh
892 msr sctlr_el1, x19 // re-enable the MMU
893 isb
894 ic iallu // flush instructions fetched
895 dsb nsh // via old mapping
896 isb
898 bl __relocate_kernel
899 #endif
900 #endif
901 ldr x8, =__primary_switched
902 adrp x0, __PHYS_OFFSET
903 br x8
904 ENDPROC(__primary_switch)