arch/arm64/kernel/insn.c

   1 /*
   2  * Copyright (C) 2013 Huawei Ltd.
   3  * Author: Jiang Liu <liuj97@gmail.com>
   4  *
   5  * Copyright (C) 2014-2016 Zi Shen Lim <zlim.lnx@gmail.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include <linux/bitops.h>
  20 #include <linux/bug.h>
  21 #include <linux/compiler.h>
  22 #include <linux/kernel.h>
  23 #include <linux/mm.h>
  24 #include <linux/smp.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/stop_machine.h>
  27 #include <linux/types.h>
  28 #include <linux/uaccess.h>
  29
  30 #include <asm/cacheflush.h>
  31 #include <asm/debug-monitors.h>
  32 #include <asm/fixmap.h>
  33 #include <asm/insn.h>
  34 #include <asm/kprobes.h>
  35
  36 #define AARCH64_INSN_SF_BIT     BIT(31)
  37 #define AARCH64_INSN_N_BIT      BIT(22)
  38
  39 static int aarch64_insn_encoding_class[] = {
  40         AARCH64_INSN_CLS_UNKNOWN,
  41         AARCH64_INSN_CLS_UNKNOWN,
  42         AARCH64_INSN_CLS_UNKNOWN,
  43         AARCH64_INSN_CLS_UNKNOWN,
  44         AARCH64_INSN_CLS_LDST,
  45         AARCH64_INSN_CLS_DP_REG,
  46         AARCH64_INSN_CLS_LDST,
  47         AARCH64_INSN_CLS_DP_FPSIMD,
  48         AARCH64_INSN_CLS_DP_IMM,
  49         AARCH64_INSN_CLS_DP_IMM,
  50         AARCH64_INSN_CLS_BR_SYS,
  51         AARCH64_INSN_CLS_BR_SYS,
  52         AARCH64_INSN_CLS_LDST,
  53         AARCH64_INSN_CLS_DP_REG,
  54         AARCH64_INSN_CLS_LDST,
  55         AARCH64_INSN_CLS_DP_FPSIMD,
  56 };
  57
  58 enum aarch64_insn_encoding_class __kprobes aarch64_get_insn_class(u32 insn)
  59 {
  60         return aarch64_insn_encoding_class[(insn >> 25) & 0xf];
  61 }
  62
  63 /* NOP is an alias of HINT */
  64 bool __kprobes aarch64_insn_is_nop(u32 insn)
  65 {
  66         if (!aarch64_insn_is_hint(insn))
  67                 return false;
  68
  69         switch (insn & 0xFE0) {
  70         case AARCH64_INSN_HINT_YIELD:
  71         case AARCH64_INSN_HINT_WFE:
  72         case AARCH64_INSN_HINT_WFI:
  73         case AARCH64_INSN_HINT_SEV:
  74         case AARCH64_INSN_HINT_SEVL:
  75                 return false;
  76         default:
  77                 return true;
  78         }
  79 }
  80
  81 bool aarch64_insn_is_branch_imm(u32 insn)
  82 {
  83         return (aarch64_insn_is_b(insn) || aarch64_insn_is_bl(insn) ||
  84                 aarch64_insn_is_tbz(insn) || aarch64_insn_is_tbnz(insn) ||
  85                 aarch64_insn_is_cbz(insn) || aarch64_insn_is_cbnz(insn) ||
  86                 aarch64_insn_is_bcond(insn));
  87 }
  88
  89 static DEFINE_RAW_SPINLOCK(patch_lock);
  90
  91 static void __kprobes *patch_map(void *addr, int fixmap)
  92 {
  93         unsigned long uintaddr = (uintptr_t) addr;
  94         bool module = !core_kernel_text(uintaddr);
  95         struct page *page;
  96
  97         if (module && IS_ENABLED(CONFIG_STRICT_MODULE_RWX))
  98                 page = vmalloc_to_page(addr);
  99         else if (!module)
 100                 page = phys_to_page(__pa_symbol(addr));
 101         else
 102                 return addr;
 103
 104         BUG_ON(!page);
 105         return (void *)set_fixmap_offset(fixmap, page_to_phys(page) +
 106                         (uintaddr & ~PAGE_MASK));
 107 }
 108
 109 static void __kprobes patch_unmap(int fixmap)
 110 {
 111         clear_fixmap(fixmap);
 112 }
 113 /*
 114  * In ARMv8-A, A64 instructions have a fixed length of 32 bits and are always
 115  * little-endian.
 116  */
 117 int __kprobes aarch64_insn_read(void *addr, u32 *insnp)
 118 {
 119         int ret;
 120         u32 val;
 121
 122         ret = probe_kernel_read(&val, addr, AARCH64_INSN_SIZE);
 123         if (!ret)
 124                 *insnp = le32_to_cpu(val);
 125
 126         return ret;
 127 }
 128
 129 static int __kprobes __aarch64_insn_write(void *addr, u32 insn)
 130 {
 131         void *waddr = addr;
 132         unsigned long flags = 0;
 133         int ret;
 134
 135         raw_spin_lock_irqsave(&patch_lock, flags);
 136         waddr = patch_map(addr, FIX_TEXT_POKE0);
 137
 138         ret = probe_kernel_write(waddr, &insn, AARCH64_INSN_SIZE);
 139
 140         patch_unmap(FIX_TEXT_POKE0);
 141         raw_spin_unlock_irqrestore(&patch_lock, flags);
 142
 143         return ret;
 144 }
 145
 146 int __kprobes aarch64_insn_write(void *addr, u32 insn)
 147 {
 148         insn = cpu_to_le32(insn);
 149         return __aarch64_insn_write(addr, insn);
 150 }
 151
 152 static bool __kprobes __aarch64_insn_hotpatch_safe(u32 insn)
 153 {
 154         if (aarch64_get_insn_class(insn) != AARCH64_INSN_CLS_BR_SYS)
 155                 return false;
 156
 157         return  aarch64_insn_is_b(insn) ||
 158                 aarch64_insn_is_bl(insn) ||
 159                 aarch64_insn_is_svc(insn) ||
 160                 aarch64_insn_is_hvc(insn) ||
 161                 aarch64_insn_is_smc(insn) ||
 162                 aarch64_insn_is_brk(insn) ||
 163                 aarch64_insn_is_nop(insn);
 164 }
 165
 166 bool __kprobes aarch64_insn_uses_literal(u32 insn)
 167 {
 168         /* ldr/ldrsw (literal), prfm */
 169
 170         return aarch64_insn_is_ldr_lit(insn) ||
 171                 aarch64_insn_is_ldrsw_lit(insn) ||
 172                 aarch64_insn_is_adr_adrp(insn) ||
 173                 aarch64_insn_is_prfm_lit(insn);
 174 }
 175
 176 bool __kprobes aarch64_insn_is_branch(u32 insn)
 177 {
 178         /* b, bl, cb*, tb*, b.cond, br, blr */
 179
 180         return aarch64_insn_is_b(insn) ||
 181                 aarch64_insn_is_bl(insn) ||
 182                 aarch64_insn_is_cbz(insn) ||
 183                 aarch64_insn_is_cbnz(insn) ||
 184                 aarch64_insn_is_tbz(insn) ||
 185                 aarch64_insn_is_tbnz(insn) ||
 186                 aarch64_insn_is_ret(insn) ||
 187                 aarch64_insn_is_br(insn) ||
 188                 aarch64_insn_is_blr(insn) ||
 189                 aarch64_insn_is_bcond(insn);
 190 }
 191
 192 /*
 193  * ARM Architecture Reference Manual for ARMv8 Profile-A, Issue A.a
 194  * Section B2.6.5 "Concurrent modification and execution of instructions":
 195  * Concurrent modification and execution of instructions can lead to the
 196  * resulting instruction performing any behavior that can be achieved by
 197  * executing any sequence of instructions that can be executed from the
 198  * same Exception level, except where the instruction before modification
 199  * and the instruction after modification is a B, BL, NOP, BKPT, SVC, HVC,
 200  * or SMC instruction.
 201  */
 202 bool __kprobes aarch64_insn_hotpatch_safe(u32 old_insn, u32 new_insn)
 203 {
 204         return __aarch64_insn_hotpatch_safe(old_insn) &&
 205                __aarch64_insn_hotpatch_safe(new_insn);
 206 }
 207
 208 int __kprobes aarch64_insn_patch_text_nosync(void *addr, u32 insn)
 209 {
 210         u32 *tp = addr;
 211         int ret;
 212
 213         /* A64 instructions must be word aligned */
 214         if ((uintptr_t)tp & 0x3)
 215                 return -EINVAL;
 216
 217         ret = aarch64_insn_write(tp, insn);
 218         if (ret == 0)
 219                 flush_icache_range((uintptr_t)tp,
 220                                    (uintptr_t)tp + AARCH64_INSN_SIZE);
 221
 222         return ret;
 223 }
 224
 225 struct aarch64_insn_patch {
 226         void            **text_addrs;
 227         u32             *new_insns;
 228         int             insn_cnt;
 229         atomic_t        cpu_count;
 230 };
 231
 232 static int __kprobes aarch64_insn_patch_text_cb(void *arg)
 233 {
 234         int i, ret = 0;
 235         struct aarch64_insn_patch *pp = arg;
 236
 237         /* The first CPU becomes master */
 238         if (atomic_inc_return(&pp->cpu_count) == 1) {
 239                 for (i = 0; ret == 0 && i < pp->insn_cnt; i++)
 240                         ret = aarch64_insn_patch_text_nosync(pp->text_addrs[i],
 241                                                              pp->new_insns[i]);
 242                 /*
 243                  * aarch64_insn_patch_text_nosync() calls flush_icache_range(),
 244                  * which ends with "dsb; isb" pair guaranteeing global
 245                  * visibility.
 246                  */
 247                 /* Notify other processors with an additional increment. */
 248                 atomic_inc(&pp->cpu_count);
 249         } else {
 250                 while (atomic_read(&pp->cpu_count) <= num_online_cpus())
 251                         cpu_relax();
 252                 isb();
 253         }
 254
 255         return ret;
 256 }
 257
 258 int __kprobes aarch64_insn_patch_text_sync(void *addrs[], u32 insns[], int cnt)
 259 {
 260         struct aarch64_insn_patch patch = {
 261                 .text_addrs = addrs,
 262                 .new_insns = insns,
 263                 .insn_cnt = cnt,
 264                 .cpu_count = ATOMIC_INIT(0),
 265         };
 266
 267         if (cnt <= 0)
 268                 return -EINVAL;
 269
 270         return stop_machine(aarch64_insn_patch_text_cb, &patch,
 271                             cpu_online_mask);
 272 }
 273
 274 int __kprobes aarch64_insn_patch_text(void *addrs[], u32 insns[], int cnt)
 275 {
 276         int ret;
 277         u32 insn;
 278
 279         /* Unsafe to patch multiple instructions without synchronizaiton */
 280         if (cnt == 1) {
 281                 ret = aarch64_insn_read(addrs[0], &insn);
 282                 if (ret)
 283                         return ret;
 284
 285                 if (aarch64_insn_hotpatch_safe(insn, insns[0])) {
 286                         /*
 287                          * ARMv8 architecture doesn't guarantee all CPUs see
 288                          * the new instruction after returning from function
 289                          * aarch64_insn_patch_text_nosync(). So send IPIs to
 290                          * all other CPUs to achieve instruction
 291                          * synchronization.
 292                          */
 293                         ret = aarch64_insn_patch_text_nosync(addrs[0], insns[0]);
 294                         kick_all_cpus_sync();
 295                         return ret;
 296                 }
 297         }
 298
 299         return aarch64_insn_patch_text_sync(addrs, insns, cnt);
 300 }
 301
 302 static int __kprobes aarch64_get_imm_shift_mask(enum aarch64_insn_imm_type type,
 303                                                 u32 *maskp, int *shiftp)
 304 {
 305         u32 mask;
 306         int shift;
 307
 308         switch (type) {
 309         case AARCH64_INSN_IMM_26:
 310                 mask = BIT(26) - 1;
 311                 shift = 0;
 312                 break;
 313         case AARCH64_INSN_IMM_19:
 314                 mask = BIT(19) - 1;
 315                 shift = 5;
 316                 break;
 317         case AARCH64_INSN_IMM_16:
 318                 mask = BIT(16) - 1;
 319                 shift = 5;
 320                 break;
 321         case AARCH64_INSN_IMM_14:
 322                 mask = BIT(14) - 1;
 323                 shift = 5;
 324                 break;
 325         case AARCH64_INSN_IMM_12:
 326                 mask = BIT(12) - 1;
 327                 shift = 10;
 328                 break;
 329         case AARCH64_INSN_IMM_9:
 330                 mask = BIT(9) - 1;
 331                 shift = 12;
 332                 break;
 333         case AARCH64_INSN_IMM_7:
 334                 mask = BIT(7) - 1;
 335                 shift = 15;
 336                 break;
 337         case AARCH64_INSN_IMM_6:
 338         case AARCH64_INSN_IMM_S:
 339                 mask = BIT(6) - 1;
 340                 shift = 10;
 341                 break;
 342         case AARCH64_INSN_IMM_R:
 343                 mask = BIT(6) - 1;
 344                 shift = 16;
 345                 break;
 346         default:
 347                 return -EINVAL;
 348         }
 349
 350         *maskp = mask;
 351         *shiftp = shift;
 352
 353         return 0;
 354 }
 355
 356 #define ADR_IMM_HILOSPLIT       2
 357 #define ADR_IMM_SIZE            SZ_2M
 358 #define ADR_IMM_LOMASK          ((1 << ADR_IMM_HILOSPLIT) - 1)
 359 #define ADR_IMM_HIMASK          ((ADR_IMM_SIZE >> ADR_IMM_HILOSPLIT) - 1)
 360 #define ADR_IMM_LOSHIFT         29
 361 #define ADR_IMM_HISHIFT         5
 362
 363 u64 aarch64_insn_decode_immediate(enum aarch64_insn_imm_type type, u32 insn)
 364 {
 365         u32 immlo, immhi, mask;
 366         int shift;
 367
 368         switch (type) {
 369         case AARCH64_INSN_IMM_ADR:
 370                 shift = 0;
 371                 immlo = (insn >> ADR_IMM_LOSHIFT) & ADR_IMM_LOMASK;
 372                 immhi = (insn >> ADR_IMM_HISHIFT) & ADR_IMM_HIMASK;
 373                 insn = (immhi << ADR_IMM_HILOSPLIT) | immlo;
 374                 mask = ADR_IMM_SIZE - 1;
 375                 break;
 376         default:
 377                 if (aarch64_get_imm_shift_mask(type, &mask, &shift) < 0) {
 378                         pr_err("aarch64_insn_decode_immediate: unknown immediate encoding %d\n",
 379                                type);
 380                         return 0;
 381                 }
 382         }
 383
 384         return (insn >> shift) & mask;
 385 }
 386
 387 u32 __kprobes aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type,
 388                                   u32 insn, u64 imm)
 389 {
 390         u32 immlo, immhi, mask;
 391         int shift;
 392
 393         if (insn == AARCH64_BREAK_FAULT)
 394                 return AARCH64_BREAK_FAULT;
 395
 396         switch (type) {
 397         case AARCH64_INSN_IMM_ADR:
 398                 shift = 0;
 399                 immlo = (imm & ADR_IMM_LOMASK) << ADR_IMM_LOSHIFT;
 400                 imm >>= ADR_IMM_HILOSPLIT;
 401                 immhi = (imm & ADR_IMM_HIMASK) << ADR_IMM_HISHIFT;
 402                 imm = immlo | immhi;
 403                 mask = ((ADR_IMM_LOMASK << ADR_IMM_LOSHIFT) |
 404                         (ADR_IMM_HIMASK << ADR_IMM_HISHIFT));
 405                 break;
 406         default:
 407                 if (aarch64_get_imm_shift_mask(type, &mask, &shift) < 0) {
 408                         pr_err("aarch64_insn_encode_immediate: unknown immediate encoding %d\n",
 409                                type);
 410                         return AARCH64_BREAK_FAULT;
 411                 }
 412         }
 413
 414         /* Update the immediate field. */
 415         insn &= ~(mask << shift);
 416         insn |= (imm & mask) << shift;
 417
 418         return insn;
 419 }
 420
 421 u32 aarch64_insn_decode_register(enum aarch64_insn_register_type type,
 422                                         u32 insn)
 423 {
 424         int shift;
 425
 426         switch (type) {
 427         case AARCH64_INSN_REGTYPE_RT:
 428         case AARCH64_INSN_REGTYPE_RD:
 429                 shift = 0;
 430                 break;
 431         case AARCH64_INSN_REGTYPE_RN:
 432                 shift = 5;
 433                 break;
 434         case AARCH64_INSN_REGTYPE_RT2:
 435         case AARCH64_INSN_REGTYPE_RA:
 436                 shift = 10;
 437                 break;
 438         case AARCH64_INSN_REGTYPE_RM:
 439                 shift = 16;
 440                 break;
 441         default:
 442                 pr_err("%s: unknown register type encoding %d\n", __func__,
 443                        type);
 444                 return 0;
 445         }
 446
 447         return (insn >> shift) & GENMASK(4, 0);
 448 }
 449
 450 static u32 aarch64_insn_encode_register(enum aarch64_insn_register_type type,
 451                                         u32 insn,
 452                                         enum aarch64_insn_register reg)
 453 {
 454         int shift;
 455
 456         if (insn == AARCH64_BREAK_FAULT)
 457                 return AARCH64_BREAK_FAULT;
 458
 459         if (reg < AARCH64_INSN_REG_0 || reg > AARCH64_INSN_REG_SP) {
 460                 pr_err("%s: unknown register encoding %d\n", __func__, reg);
 461                 return AARCH64_BREAK_FAULT;
 462         }
 463
 464         switch (type) {
 465         case AARCH64_INSN_REGTYPE_RT:
 466         case AARCH64_INSN_REGTYPE_RD:
 467                 shift = 0;
 468                 break;
 469         case AARCH64_INSN_REGTYPE_RN:
 470                 shift = 5;
 471                 break;
 472         case AARCH64_INSN_REGTYPE_RT2:
 473         case AARCH64_INSN_REGTYPE_RA:
 474                 shift = 10;
 475                 break;
 476         case AARCH64_INSN_REGTYPE_RM:
 477                 shift = 16;
 478                 break;
 479         default:
 480                 pr_err("%s: unknown register type encoding %d\n", __func__,
 481                        type);
 482                 return AARCH64_BREAK_FAULT;
 483         }
 484
 485         insn &= ~(GENMASK(4, 0) << shift);
 486         insn |= reg << shift;
 487
 488         return insn;
 489 }
 490
 491 static u32 aarch64_insn_encode_ldst_size(enum aarch64_insn_size_type type,
 492                                          u32 insn)
 493 {
 494         u32 size;
 495
 496         switch (type) {
 497         case AARCH64_INSN_SIZE_8:
 498                 size = 0;
 499                 break;
 500         case AARCH64_INSN_SIZE_16:
 501                 size = 1;
 502                 break;
 503         case AARCH64_INSN_SIZE_32:
 504                 size = 2;
 505                 break;
 506         case AARCH64_INSN_SIZE_64:
 507                 size = 3;
 508                 break;
 509         default:
 510                 pr_err("%s: unknown size encoding %d\n", __func__, type);
 511                 return AARCH64_BREAK_FAULT;
 512         }
 513
 514         insn &= ~GENMASK(31, 30);
 515         insn |= size << 30;
 516
 517         return insn;
 518 }
 519
 520 static inline long branch_imm_common(unsigned long pc, unsigned long addr,
 521                                      long range)
 522 {
 523         long offset;
 524
 525         if ((pc & 0x3) || (addr & 0x3)) {
 526                 pr_err("%s: A64 instructions must be word aligned\n", __func__);
 527                 return range;
 528         }
 529
 530         offset = ((long)addr - (long)pc);
 531
 532         if (offset < -range || offset >= range) {
 533                 pr_err("%s: offset out of range\n", __func__);
 534                 return range;
 535         }
 536
 537         return offset;
 538 }
 539
 540 u32 __kprobes aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr,
 541                                           enum aarch64_insn_branch_type type)
 542 {
 543         u32 insn;
 544         long offset;
 545
 546         /*
 547          * B/BL support [-128M, 128M) offset
 548          * ARM64 virtual address arrangement guarantees all kernel and module
 549          * texts are within +/-128M.
 550          */
 551         offset = branch_imm_common(pc, addr, SZ_128M);
 552         if (offset >= SZ_128M)
 553                 return AARCH64_BREAK_FAULT;
 554
 555         switch (type) {
 556         case AARCH64_INSN_BRANCH_LINK:
 557                 insn = aarch64_insn_get_bl_value();
 558                 break;
 559         case AARCH64_INSN_BRANCH_NOLINK:
 560                 insn = aarch64_insn_get_b_value();
 561                 break;
 562         default:
 563                 pr_err("%s: unknown branch encoding %d\n", __func__, type);
 564                 return AARCH64_BREAK_FAULT;
 565         }
 566
 567         return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_26, insn,
 568                                              offset >> 2);
 569 }
 570
 571 u32 aarch64_insn_gen_comp_branch_imm(unsigned long pc, unsigned long addr,
 572                                      enum aarch64_insn_register reg,
 573                                      enum aarch64_insn_variant variant,
 574                                      enum aarch64_insn_branch_type type)
 575 {
 576         u32 insn;
 577         long offset;
 578
 579         offset = branch_imm_common(pc, addr, SZ_1M);
 580         if (offset >= SZ_1M)
 581                 return AARCH64_BREAK_FAULT;
 582
 583         switch (type) {
 584         case AARCH64_INSN_BRANCH_COMP_ZERO:
 585                 insn = aarch64_insn_get_cbz_value();
 586                 break;
 587         case AARCH64_INSN_BRANCH_COMP_NONZERO:
 588                 insn = aarch64_insn_get_cbnz_value();
 589                 break;
 590         default:
 591                 pr_err("%s: unknown branch encoding %d\n", __func__, type);
 592                 return AARCH64_BREAK_FAULT;
 593         }
 594
 595         switch (variant) {
 596         case AARCH64_INSN_VARIANT_32BIT:
 597                 break;
 598         case AARCH64_INSN_VARIANT_64BIT:
 599                 insn |= AARCH64_INSN_SF_BIT;
 600                 break;
 601         default:
 602                 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
 603                 return AARCH64_BREAK_FAULT;
 604         }
 605
 606         insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn, reg);
 607
 608         return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_19, insn,
 609                                              offset >> 2);
 610 }
 611
 612 u32 aarch64_insn_gen_cond_branch_imm(unsigned long pc, unsigned long addr,
 613                                      enum aarch64_insn_condition cond)
 614 {
 615         u32 insn;
 616         long offset;
 617
 618         offset = branch_imm_common(pc, addr, SZ_1M);
 619
 620         insn = aarch64_insn_get_bcond_value();
 621
 622         if (cond < AARCH64_INSN_COND_EQ || cond > AARCH64_INSN_COND_AL) {
 623                 pr_err("%s: unknown condition encoding %d\n", __func__, cond);
 624                 return AARCH64_BREAK_FAULT;
 625         }
 626         insn |= cond;
 627
 628         return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_19, insn,
 629                                              offset >> 2);
 630 }
 631
 632 u32 __kprobes aarch64_insn_gen_hint(enum aarch64_insn_hint_op op)
 633 {
 634         return aarch64_insn_get_hint_value() | op;
 635 }
 636
 637 u32 __kprobes aarch64_insn_gen_nop(void)
 638 {
 639         return aarch64_insn_gen_hint(AARCH64_INSN_HINT_NOP);
 640 }
 641
 642 u32 aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg,
 643                                 enum aarch64_insn_branch_type type)
 644 {
 645         u32 insn;
 646
 647         switch (type) {
 648         case AARCH64_INSN_BRANCH_NOLINK:
 649                 insn = aarch64_insn_get_br_value();
 650                 break;
 651         case AARCH64_INSN_BRANCH_LINK:
 652                 insn = aarch64_insn_get_blr_value();
 653                 break;
 654         case AARCH64_INSN_BRANCH_RETURN:
 655                 insn = aarch64_insn_get_ret_value();
 656                 break;
 657         default:
 658                 pr_err("%s: unknown branch encoding %d\n", __func__, type);
 659                 return AARCH64_BREAK_FAULT;
 660         }
 661
 662         return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, reg);
 663 }
 664
 665 u32 aarch64_insn_gen_load_store_reg(enum aarch64_insn_register reg,
 666                                     enum aarch64_insn_register base,
 667                                     enum aarch64_insn_register offset,
 668                                     enum aarch64_insn_size_type size,
 669                                     enum aarch64_insn_ldst_type type)
 670 {
 671         u32 insn;
 672
 673         switch (type) {
 674         case AARCH64_INSN_LDST_LOAD_REG_OFFSET:
 675                 insn = aarch64_insn_get_ldr_reg_value();
 676                 break;
 677         case AARCH64_INSN_LDST_STORE_REG_OFFSET:
 678                 insn = aarch64_insn_get_str_reg_value();
 679                 break;
 680         default:
 681                 pr_err("%s: unknown load/store encoding %d\n", __func__, type);
 682                 return AARCH64_BREAK_FAULT;
 683         }
 684
 685         insn = aarch64_insn_encode_ldst_size(size, insn);
 686
 687         insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn, reg);
 688
 689         insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
 690                                             base);
 691
 692         return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn,
 693                                             offset);
 694 }
 695
 696 u32 aarch64_insn_gen_load_store_pair(enum aarch64_insn_register reg1,
 697                                      enum aarch64_insn_register reg2,
 698                                      enum aarch64_insn_register base,
 699                                      int offset,
 700                                      enum aarch64_insn_variant variant,
 701                                      enum aarch64_insn_ldst_type type)
 702 {
 703         u32 insn;
 704         int shift;
 705
 706         switch (type) {
 707         case AARCH64_INSN_LDST_LOAD_PAIR_PRE_INDEX:
 708                 insn = aarch64_insn_get_ldp_pre_value();
 709                 break;
 710         case AARCH64_INSN_LDST_STORE_PAIR_PRE_INDEX:
 711                 insn = aarch64_insn_get_stp_pre_value();
 712                 break;
 713         case AARCH64_INSN_LDST_LOAD_PAIR_POST_INDEX:
 714                 insn = aarch64_insn_get_ldp_post_value();
 715                 break;
 716         case AARCH64_INSN_LDST_STORE_PAIR_POST_INDEX:
 717                 insn = aarch64_insn_get_stp_post_value();
 718                 break;
 719         default:
 720                 pr_err("%s: unknown load/store encoding %d\n", __func__, type);
 721                 return AARCH64_BREAK_FAULT;
 722         }
 723
 724         switch (variant) {
 725         case AARCH64_INSN_VARIANT_32BIT:
 726                 if ((offset & 0x3) || (offset < -256) || (offset > 252)) {
 727                         pr_err("%s: offset must be multiples of 4 in the range of [-256, 252] %d\n",
 728                                __func__, offset);
 729                         return AARCH64_BREAK_FAULT;
 730                 }
 731                 shift = 2;
 732                 break;
 733         case AARCH64_INSN_VARIANT_64BIT:
 734                 if ((offset & 0x7) || (offset < -512) || (offset > 504)) {
 735                         pr_err("%s: offset must be multiples of 8 in the range of [-512, 504] %d\n",
 736                                __func__, offset);
 737                         return AARCH64_BREAK_FAULT;
 738                 }
 739                 shift = 3;
 740                 insn |= AARCH64_INSN_SF_BIT;
 741                 break;
 742         default:
 743                 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
 744                 return AARCH64_BREAK_FAULT;
 745         }
 746
 747         insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn,
 748                                             reg1);
 749
 750         insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT2, insn,
 751                                             reg2);
 752
 753         insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
 754                                             base);
 755
 756         return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_7, insn,
 757                                              offset >> shift);
 758 }
 759
 760 u32 aarch64_insn_gen_add_sub_imm(enum aarch64_insn_register dst,
 761                                  enum aarch64_insn_register src,
 762                                  int imm, enum aarch64_insn_variant variant,
 763                                  enum aarch64_insn_adsb_type type)
 764 {
 765         u32 insn;
 766
 767         switch (type) {
 768         case AARCH64_INSN_ADSB_ADD:
 769                 insn = aarch64_insn_get_add_imm_value();
 770                 break;
 771         case AARCH64_INSN_ADSB_SUB:
 772                 insn = aarch64_insn_get_sub_imm_value();
 773                 break;
 774         case AARCH64_INSN_ADSB_ADD_SETFLAGS:
 775                 insn = aarch64_insn_get_adds_imm_value();
 776                 break;
 777         case AARCH64_INSN_ADSB_SUB_SETFLAGS:
 778                 insn = aarch64_insn_get_subs_imm_value();
 779                 break;
 780         default:
 781                 pr_err("%s: unknown add/sub encoding %d\n", __func__, type);
 782                 return AARCH64_BREAK_FAULT;
 783         }
 784
 785         switch (variant) {
 786         case AARCH64_INSN_VARIANT_32BIT:
 787                 break;
 788         case AARCH64_INSN_VARIANT_64BIT:
 789                 insn |= AARCH64_INSN_SF_BIT;
 790                 break;
 791         default:
 792                 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
 793                 return AARCH64_BREAK_FAULT;
 794         }
 795
 796         if (imm & ~(SZ_4K - 1)) {
 797                 pr_err("%s: invalid immediate encoding %d\n", __func__, imm);
 798                 return AARCH64_BREAK_FAULT;
 799         }
 800
 801         insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
 802
 803         insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
 804
 805         return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_12, insn, imm);
 806 }
 807
 808 u32 aarch64_insn_gen_bitfield(enum aarch64_insn_register dst,
 809                               enum aarch64_insn_register src,
 810                               int immr, int imms,
 811                               enum aarch64_insn_variant variant,
 812                               enum aarch64_insn_bitfield_type type)
 813 {
 814         u32 insn;
 815         u32 mask;
 816
 817         switch (type) {
 818         case AARCH64_INSN_BITFIELD_MOVE:
 819                 insn = aarch64_insn_get_bfm_value();
 820                 break;
 821         case AARCH64_INSN_BITFIELD_MOVE_UNSIGNED:
 822                 insn = aarch64_insn_get_ubfm_value();
 823                 break;
 824         case AARCH64_INSN_BITFIELD_MOVE_SIGNED:
 825                 insn = aarch64_insn_get_sbfm_value();
 826                 break;
 827         default:
 828                 pr_err("%s: unknown bitfield encoding %d\n", __func__, type);
 829                 return AARCH64_BREAK_FAULT;
 830         }
 831
 832         switch (variant) {
 833         case AARCH64_INSN_VARIANT_32BIT:
 834                 mask = GENMASK(4, 0);
 835                 break;
 836         case AARCH64_INSN_VARIANT_64BIT:
 837                 insn |= AARCH64_INSN_SF_BIT | AARCH64_INSN_N_BIT;
 838                 mask = GENMASK(5, 0);
 839                 break;
 840         default:
 841                 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
 842                 return AARCH64_BREAK_FAULT;
 843         }
 844
 845         if (immr & ~mask) {
 846                 pr_err("%s: invalid immr encoding %d\n", __func__, immr);
 847                 return AARCH64_BREAK_FAULT;
 848         }
 849         if (imms & ~mask) {
 850                 pr_err("%s: invalid imms encoding %d\n", __func__, imms);
 851                 return AARCH64_BREAK_FAULT;
 852         }
 853
 854         insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
 855
 856         insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
 857
 858         insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_R, insn, immr);
 859
 860         return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_S, insn, imms);
 861 }
 862
 863 u32 aarch64_insn_gen_movewide(enum aarch64_insn_register dst,
 864                               int imm, int shift,
 865                               enum aarch64_insn_variant variant,
 866                               enum aarch64_insn_movewide_type type)
 867 {
 868         u32 insn;
 869
 870         switch (type) {
 871         case AARCH64_INSN_MOVEWIDE_ZERO:
 872                 insn = aarch64_insn_get_movz_value();
 873                 break;
 874         case AARCH64_INSN_MOVEWIDE_KEEP:
 875                 insn = aarch64_insn_get_movk_value();
 876                 break;
 877         case AARCH64_INSN_MOVEWIDE_INVERSE:
 878                 insn = aarch64_insn_get_movn_value();
 879                 break;
 880         default:
 881                 pr_err("%s: unknown movewide encoding %d\n", __func__, type);
 882                 return AARCH64_BREAK_FAULT;
 883         }
 884
 885         if (imm & ~(SZ_64K - 1)) {
 886                 pr_err("%s: invalid immediate encoding %d\n", __func__, imm);
 887                 return AARCH64_BREAK_FAULT;
 888         }
 889
 890         switch (variant) {
 891         case AARCH64_INSN_VARIANT_32BIT:
 892                 if (shift != 0 && shift != 16) {
 893                         pr_err("%s: invalid shift encoding %d\n", __func__,
 894                                shift);
 895                         return AARCH64_BREAK_FAULT;
 896                 }
 897                 break;
 898         case AARCH64_INSN_VARIANT_64BIT:
 899                 insn |= AARCH64_INSN_SF_BIT;
 900                 if (shift != 0 && shift != 16 && shift != 32 && shift != 48) {
 901                         pr_err("%s: invalid shift encoding %d\n", __func__,
 902                                shift);
 903                         return AARCH64_BREAK_FAULT;
 904                 }
 905                 break;
 906         default:
 907                 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
 908                 return AARCH64_BREAK_FAULT;
 909         }
 910
 911         insn |= (shift >> 4) << 21;
 912
 913         insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
 914
 915         return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_16, insn, imm);
 916 }
 917
 918 u32 aarch64_insn_gen_add_sub_shifted_reg(enum aarch64_insn_register dst,
 919                                          enum aarch64_insn_register src,
 920                                          enum aarch64_insn_register reg,
 921                                          int shift,
 922                                          enum aarch64_insn_variant variant,
 923                                          enum aarch64_insn_adsb_type type)
 924 {
 925         u32 insn;
 926
 927         switch (type) {
 928         case AARCH64_INSN_ADSB_ADD:
 929                 insn = aarch64_insn_get_add_value();
 930                 break;
 931         case AARCH64_INSN_ADSB_SUB:
 932                 insn = aarch64_insn_get_sub_value();
 933                 break;
 934         case AARCH64_INSN_ADSB_ADD_SETFLAGS:
 935                 insn = aarch64_insn_get_adds_value();
 936                 break;
 937         case AARCH64_INSN_ADSB_SUB_SETFLAGS:
 938                 insn = aarch64_insn_get_subs_value();
 939                 break;
 940         default:
 941                 pr_err("%s: unknown add/sub encoding %d\n", __func__, type);
 942                 return AARCH64_BREAK_FAULT;
 943         }
 944
 945         switch (variant) {
 946         case AARCH64_INSN_VARIANT_32BIT:
 947                 if (shift & ~(SZ_32 - 1)) {
 948                         pr_err("%s: invalid shift encoding %d\n", __func__,
 949                                shift);
 950                         return AARCH64_BREAK_FAULT;
 951                 }
 952                 break;
 953         case AARCH64_INSN_VARIANT_64BIT:
 954                 insn |= AARCH64_INSN_SF_BIT;
 955                 if (shift & ~(SZ_64 - 1)) {
 956                         pr_err("%s: invalid shift encoding %d\n", __func__,
 957                                shift);
 958                         return AARCH64_BREAK_FAULT;
 959                 }
 960                 break;
 961         default:
 962                 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
 963                 return AARCH64_BREAK_FAULT;
 964         }
 965
 966
 967         insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
 968
 969         insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
 970
 971         insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, reg);
 972
 973         return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_6, insn, shift);
 974 }
 975
 976 u32 aarch64_insn_gen_data1(enum aarch64_insn_register dst,
 977                            enum aarch64_insn_register src,
 978                            enum aarch64_insn_variant variant,
 979                            enum aarch64_insn_data1_type type)
 980 {
 981         u32 insn;
 982
 983         switch (type) {
 984         case AARCH64_INSN_DATA1_REVERSE_16:
 985                 insn = aarch64_insn_get_rev16_value();
 986                 break;
 987         case AARCH64_INSN_DATA1_REVERSE_32:
 988                 insn = aarch64_insn_get_rev32_value();
 989                 break;
 990         case AARCH64_INSN_DATA1_REVERSE_64:
 991                 if (variant != AARCH64_INSN_VARIANT_64BIT) {
 992                         pr_err("%s: invalid variant for reverse64 %d\n",
 993                                __func__, variant);
 994                         return AARCH64_BREAK_FAULT;
 995                 }
 996                 insn = aarch64_insn_get_rev64_value();
 997                 break;
 998         default:
 999                 pr_err("%s: unknown data1 encoding %d\n", __func__, type);
1000                 return AARCH64_BREAK_FAULT;
1001         }
1002
1003         switch (variant) {
1004         case AARCH64_INSN_VARIANT_32BIT:
1005                 break;
1006         case AARCH64_INSN_VARIANT_64BIT:
1007                 insn |= AARCH64_INSN_SF_BIT;
1008                 break;
1009         default:
1010                 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
1011                 return AARCH64_BREAK_FAULT;
1012         }
1013
1014         insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
1015
1016         return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
1017 }
1018
1019 u32 aarch64_insn_gen_data2(enum aarch64_insn_register dst,
1020                            enum aarch64_insn_register src,
1021                            enum aarch64_insn_register reg,
1022                            enum aarch64_insn_variant variant,
1023                            enum aarch64_insn_data2_type type)
1024 {
1025         u32 insn;
1026
1027         switch (type) {
1028         case AARCH64_INSN_DATA2_UDIV:
1029                 insn = aarch64_insn_get_udiv_value();
1030                 break;
1031         case AARCH64_INSN_DATA2_SDIV:
1032                 insn = aarch64_insn_get_sdiv_value();
1033                 break;
1034         case AARCH64_INSN_DATA2_LSLV:
1035                 insn = aarch64_insn_get_lslv_value();
1036                 break;
1037         case AARCH64_INSN_DATA2_LSRV:
1038                 insn = aarch64_insn_get_lsrv_value();
1039                 break;
1040         case AARCH64_INSN_DATA2_ASRV:
1041                 insn = aarch64_insn_get_asrv_value();
1042                 break;
1043         case AARCH64_INSN_DATA2_RORV:
1044                 insn = aarch64_insn_get_rorv_value();
1045                 break;
1046         default:
1047                 pr_err("%s: unknown data2 encoding %d\n", __func__, type);
1048                 return AARCH64_BREAK_FAULT;
1049         }
1050
1051         switch (variant) {
1052         case AARCH64_INSN_VARIANT_32BIT:
1053                 break;
1054         case AARCH64_INSN_VARIANT_64BIT:
1055                 insn |= AARCH64_INSN_SF_BIT;
1056                 break;
1057         default:
1058                 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
1059                 return AARCH64_BREAK_FAULT;
1060         }
1061
1062         insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
1063
1064         insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
1065
1066         return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, reg);
1067 }
1068
1069 u32 aarch64_insn_gen_data3(enum aarch64_insn_register dst,
1070                            enum aarch64_insn_register src,
1071                            enum aarch64_insn_register reg1,
1072                            enum aarch64_insn_register reg2,
1073                            enum aarch64_insn_variant variant,
1074                            enum aarch64_insn_data3_type type)
1075 {
1076         u32 insn;
1077
1078         switch (type) {
1079         case AARCH64_INSN_DATA3_MADD:
1080                 insn = aarch64_insn_get_madd_value();
1081                 break;
1082         case AARCH64_INSN_DATA3_MSUB:
1083                 insn = aarch64_insn_get_msub_value();
1084                 break;
1085         default:
1086                 pr_err("%s: unknown data3 encoding %d\n", __func__, type);
1087                 return AARCH64_BREAK_FAULT;
1088         }
1089
1090         switch (variant) {
1091         case AARCH64_INSN_VARIANT_32BIT:
1092                 break;
1093         case AARCH64_INSN_VARIANT_64BIT:
1094                 insn |= AARCH64_INSN_SF_BIT;
1095                 break;
1096         default:
1097                 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
1098                 return AARCH64_BREAK_FAULT;
1099         }
1100
1101         insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
1102
1103         insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RA, insn, src);
1104
1105         insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
1106                                             reg1);
1107
1108         return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn,
1109                                             reg2);
1110 }
1111
1112 u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
1113                                          enum aarch64_insn_register src,
1114                                          enum aarch64_insn_register reg,
1115                                          int shift,
1116                                          enum aarch64_insn_variant variant,
1117                                          enum aarch64_insn_logic_type type)
1118 {
1119         u32 insn;
1120
1121         switch (type) {
1122         case AARCH64_INSN_LOGIC_AND:
1123                 insn = aarch64_insn_get_and_value();
1124                 break;
1125         case AARCH64_INSN_LOGIC_BIC:
1126                 insn = aarch64_insn_get_bic_value();
1127                 break;
1128         case AARCH64_INSN_LOGIC_ORR:
1129                 insn = aarch64_insn_get_orr_value();
1130                 break;
1131         case AARCH64_INSN_LOGIC_ORN:
1132                 insn = aarch64_insn_get_orn_value();
1133                 break;
1134         case AARCH64_INSN_LOGIC_EOR:
1135                 insn = aarch64_insn_get_eor_value();
1136                 break;
1137         case AARCH64_INSN_LOGIC_EON:
1138                 insn = aarch64_insn_get_eon_value();
1139                 break;
1140         case AARCH64_INSN_LOGIC_AND_SETFLAGS:
1141                 insn = aarch64_insn_get_ands_value();
1142                 break;
1143         case AARCH64_INSN_LOGIC_BIC_SETFLAGS:
1144                 insn = aarch64_insn_get_bics_value();
1145                 break;
1146         default:
1147                 pr_err("%s: unknown logical encoding %d\n", __func__, type);
1148                 return AARCH64_BREAK_FAULT;
1149         }
1150
1151         switch (variant) {
1152         case AARCH64_INSN_VARIANT_32BIT:
1153                 if (shift & ~(SZ_32 - 1)) {
1154                         pr_err("%s: invalid shift encoding %d\n", __func__,
1155                                shift);
1156                         return AARCH64_BREAK_FAULT;
1157                 }
1158                 break;
1159         case AARCH64_INSN_VARIANT_64BIT:
1160                 insn |= AARCH64_INSN_SF_BIT;
1161                 if (shift & ~(SZ_64 - 1)) {
1162                         pr_err("%s: invalid shift encoding %d\n", __func__,
1163                                shift);
1164                         return AARCH64_BREAK_FAULT;
1165                 }
1166                 break;
1167         default:
1168                 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
1169                 return AARCH64_BREAK_FAULT;
1170         }
1171
1172
1173         insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
1174
1175         insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
1176
1177         insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, reg);
1178
1179         return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_6, insn, shift);
1180 }
1181
1182 /*
1183  * Decode the imm field of a branch, and return the byte offset as a
1184  * signed value (so it can be used when computing a new branch
1185  * target).
1186  */
1187 s32 aarch64_get_branch_offset(u32 insn)
1188 {
1189         s32 imm;
1190
1191         if (aarch64_insn_is_b(insn) || aarch64_insn_is_bl(insn)) {
1192                 imm = aarch64_insn_decode_immediate(AARCH64_INSN_IMM_26, insn);
1193                 return (imm << 6) >> 4;
1194         }
1195
1196         if (aarch64_insn_is_cbz(insn) || aarch64_insn_is_cbnz(insn) ||
1197             aarch64_insn_is_bcond(insn)) {
1198                 imm = aarch64_insn_decode_immediate(AARCH64_INSN_IMM_19, insn);
1199                 return (imm << 13) >> 11;
1200         }
1201
1202         if (aarch64_insn_is_tbz(insn) || aarch64_insn_is_tbnz(insn)) {
1203                 imm = aarch64_insn_decode_immediate(AARCH64_INSN_IMM_14, insn);
1204                 return (imm << 18) >> 16;
1205         }
1206
1207         /* Unhandled instruction */
1208         BUG();
1209 }
1210
1211 /*
1212  * Encode the displacement of a branch in the imm field and return the
1213  * updated instruction.
1214  */
1215 u32 aarch64_set_branch_offset(u32 insn, s32 offset)
1216 {
1217         if (aarch64_insn_is_b(insn) || aarch64_insn_is_bl(insn))
1218                 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_26, insn,
1219                                                      offset >> 2);
1220
1221         if (aarch64_insn_is_cbz(insn) || aarch64_insn_is_cbnz(insn) ||
1222             aarch64_insn_is_bcond(insn))
1223                 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_19, insn,
1224                                                      offset >> 2);
1225
1226         if (aarch64_insn_is_tbz(insn) || aarch64_insn_is_tbnz(insn))
1227                 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_14, insn,
1228                                                      offset >> 2);
1229
1230         /* Unhandled instruction */
1231         BUG();
1232 }
1233
1234 s32 aarch64_insn_adrp_get_offset(u32 insn)
1235 {
1236         BUG_ON(!aarch64_insn_is_adrp(insn));
1237         return aarch64_insn_decode_immediate(AARCH64_INSN_IMM_ADR, insn) << 12;
1238 }
1239
1240 u32 aarch64_insn_adrp_set_offset(u32 insn, s32 offset)
1241 {
1242         BUG_ON(!aarch64_insn_is_adrp(insn));
1243         return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_ADR, insn,
1244                                                 offset >> 12);
1245 }
1246
1247 /*
1248  * Extract the Op/CR data from a msr/mrs instruction.
1249  */
1250 u32 aarch64_insn_extract_system_reg(u32 insn)
1251 {
1252         return (insn & 0x1FFFE0) >> 5;
1253 }
1254
1255 bool aarch32_insn_is_wide(u32 insn)
1256 {
1257         return insn >= 0xe800;
1258 }
1259
1260 /*
1261  * Macros/defines for extracting register numbers from instruction.
1262  */
1263 u32 aarch32_insn_extract_reg_num(u32 insn, int offset)
1264 {
1265         return (insn & (0xf << offset)) >> offset;
1266 }
1267
1268 #define OPC2_MASK       0x7
1269 #define OPC2_OFFSET     5
1270 u32 aarch32_insn_mcr_extract_opc2(u32 insn)
1271 {
1272         return (insn & (OPC2_MASK << OPC2_OFFSET)) >> OPC2_OFFSET;
1273 }
1274
1275 #define CRM_MASK        0xf
1276 u32 aarch32_insn_mcr_extract_crm(u32 insn)
1277 {
1278         return insn & CRM_MASK;
1279 }
1280
1281 static bool __kprobes __check_eq(unsigned long pstate)
1282 {
1283         return (pstate & PSR_Z_BIT) != 0;
1284 }
1285
1286 static bool __kprobes __check_ne(unsigned long pstate)
1287 {
1288         return (pstate & PSR_Z_BIT) == 0;
1289 }
1290
1291 static bool __kprobes __check_cs(unsigned long pstate)
1292 {
1293         return (pstate & PSR_C_BIT) != 0;
1294 }
1295
1296 static bool __kprobes __check_cc(unsigned long pstate)
1297 {
1298         return (pstate & PSR_C_BIT) == 0;
1299 }
1300
1301 static bool __kprobes __check_mi(unsigned long pstate)
1302 {
1303         return (pstate & PSR_N_BIT) != 0;
1304 }
1305
1306 static bool __kprobes __check_pl(unsigned long pstate)
1307 {
1308         return (pstate & PSR_N_BIT) == 0;
1309 }
1310
1311 static bool __kprobes __check_vs(unsigned long pstate)
1312 {
1313         return (pstate & PSR_V_BIT) != 0;
1314 }
1315
1316 static bool __kprobes __check_vc(unsigned long pstate)
1317 {
1318         return (pstate & PSR_V_BIT) == 0;
1319 }
1320
1321 static bool __kprobes __check_hi(unsigned long pstate)
1322 {
1323         pstate &= ~(pstate >> 1);       /* PSR_C_BIT &= ~PSR_Z_BIT */
1324         return (pstate & PSR_C_BIT) != 0;
1325 }
1326
1327 static bool __kprobes __check_ls(unsigned long pstate)
1328 {
1329         pstate &= ~(pstate >> 1);       /* PSR_C_BIT &= ~PSR_Z_BIT */
1330         return (pstate & PSR_C_BIT) == 0;
1331 }
1332
1333 static bool __kprobes __check_ge(unsigned long pstate)
1334 {
1335         pstate ^= (pstate << 3);        /* PSR_N_BIT ^= PSR_V_BIT */
1336         return (pstate & PSR_N_BIT) == 0;
1337 }
1338
1339 static bool __kprobes __check_lt(unsigned long pstate)
1340 {
1341         pstate ^= (pstate << 3);        /* PSR_N_BIT ^= PSR_V_BIT */
1342         return (pstate & PSR_N_BIT) != 0;
1343 }
1344
1345 static bool __kprobes __check_gt(unsigned long pstate)
1346 {
1347         /*PSR_N_BIT ^= PSR_V_BIT */
1348         unsigned long temp = pstate ^ (pstate << 3);
1349
1350         temp |= (pstate << 1);  /*PSR_N_BIT |= PSR_Z_BIT */
1351         return (temp & PSR_N_BIT) == 0;
1352 }
1353
1354 static bool __kprobes __check_le(unsigned long pstate)
1355 {
1356         /*PSR_N_BIT ^= PSR_V_BIT */
1357         unsigned long temp = pstate ^ (pstate << 3);
1358
1359         temp |= (pstate << 1);  /*PSR_N_BIT |= PSR_Z_BIT */
1360         return (temp & PSR_N_BIT) != 0;
1361 }
1362
1363 static bool __kprobes __check_al(unsigned long pstate)
1364 {
1365         return true;
1366 }
1367
1368 /*
1369  * Note that the ARMv8 ARM calls condition code 0b1111 "nv", but states that
1370  * it behaves identically to 0b1110 ("al").
1371  */
1372 pstate_check_t * const aarch32_opcode_cond_checks[16] = {
1373         __check_eq, __check_ne, __check_cs, __check_cc,
1374         __check_mi, __check_pl, __check_vs, __check_vc,
1375         __check_hi, __check_ls, __check_ge, __check_lt,
1376         __check_gt, __check_le, __check_al, __check_al
1377 };