x86/mm/pat: Don't report PAT on CPUs that don't support it
[linux/fpc-iii.git] / arch / arm64 / kvm / hyp / tlb.c
blob9e1d2b75eecd606df6a6ccf632247ebc02149c67
1 /*
2 * Copyright (C) 2015 - ARM Ltd
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <asm/kvm_hyp.h>
19 #include <asm/tlbflush.h>
21 static void __hyp_text __tlb_switch_to_guest_vhe(struct kvm *kvm)
23 u64 val;
26 * With VHE enabled, we have HCR_EL2.{E2H,TGE} = {1,1}, and
27 * most TLB operations target EL2/EL0. In order to affect the
28 * guest TLBs (EL1/EL0), we need to change one of these two
29 * bits. Changing E2H is impossible (goodbye TTBR1_EL2), so
30 * let's flip TGE before executing the TLB operation.
32 write_sysreg(kvm->arch.vttbr, vttbr_el2);
33 val = read_sysreg(hcr_el2);
34 val &= ~HCR_TGE;
35 write_sysreg(val, hcr_el2);
36 isb();
39 static void __hyp_text __tlb_switch_to_guest_nvhe(struct kvm *kvm)
41 write_sysreg(kvm->arch.vttbr, vttbr_el2);
42 isb();
45 static hyp_alternate_select(__tlb_switch_to_guest,
46 __tlb_switch_to_guest_nvhe,
47 __tlb_switch_to_guest_vhe,
48 ARM64_HAS_VIRT_HOST_EXTN);
50 static void __hyp_text __tlb_switch_to_host_vhe(struct kvm *kvm)
53 * We're done with the TLB operation, let's restore the host's
54 * view of HCR_EL2.
56 write_sysreg(0, vttbr_el2);
57 write_sysreg(HCR_HOST_VHE_FLAGS, hcr_el2);
60 static void __hyp_text __tlb_switch_to_host_nvhe(struct kvm *kvm)
62 write_sysreg(0, vttbr_el2);
65 static hyp_alternate_select(__tlb_switch_to_host,
66 __tlb_switch_to_host_nvhe,
67 __tlb_switch_to_host_vhe,
68 ARM64_HAS_VIRT_HOST_EXTN);
70 void __hyp_text __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa)
72 dsb(ishst);
74 /* Switch to requested VMID */
75 kvm = kern_hyp_va(kvm);
76 __tlb_switch_to_guest()(kvm);
79 * We could do so much better if we had the VA as well.
80 * Instead, we invalidate Stage-2 for this IPA, and the
81 * whole of Stage-1. Weep...
83 ipa >>= 12;
84 __tlbi(ipas2e1is, ipa);
87 * We have to ensure completion of the invalidation at Stage-2,
88 * since a table walk on another CPU could refill a TLB with a
89 * complete (S1 + S2) walk based on the old Stage-2 mapping if
90 * the Stage-1 invalidation happened first.
92 dsb(ish);
93 __tlbi(vmalle1is);
94 dsb(ish);
95 isb();
97 __tlb_switch_to_host()(kvm);
100 void __hyp_text __kvm_tlb_flush_vmid(struct kvm *kvm)
102 dsb(ishst);
104 /* Switch to requested VMID */
105 kvm = kern_hyp_va(kvm);
106 __tlb_switch_to_guest()(kvm);
108 __tlbi(vmalls12e1is);
109 dsb(ish);
110 isb();
112 __tlb_switch_to_host()(kvm);
115 void __hyp_text __kvm_tlb_flush_local_vmid(struct kvm_vcpu *vcpu)
117 struct kvm *kvm = kern_hyp_va(kern_hyp_va(vcpu)->kvm);
119 /* Switch to requested VMID */
120 __tlb_switch_to_guest()(kvm);
122 __tlbi(vmalle1);
123 dsb(nsh);
124 isb();
126 __tlb_switch_to_host()(kvm);
129 void __hyp_text __kvm_flush_vm_context(void)
131 dsb(ishst);
132 __tlbi(alle1is);
133 asm volatile("ic ialluis" : : );
134 dsb(ish);