arch/m68k/coldfire/m5249.c

   1 /***************************************************************************/
   2
   3 /*
   4  *      m5249.c  -- platform support for ColdFire 5249 based boards
   5  *
   6  *      Copyright (C) 2002, Greg Ungerer (gerg@snapgear.com)
   7  */
   8
   9 /***************************************************************************/
  10
  11 #include <linux/kernel.h>
  12 #include <linux/param.h>
  13 #include <linux/init.h>
  14 #include <linux/io.h>
  15 #include <linux/platform_device.h>
  16 #include <asm/machdep.h>
  17 #include <asm/coldfire.h>
  18 #include <asm/mcfsim.h>
  19 #include <asm/mcfclk.h>
  20
  21 /***************************************************************************/
  22
  23 DEFINE_CLK(pll, "pll.0", MCF_CLK);
  24 DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
  25 DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
  26 DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
  27 DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
  28 DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
  29 DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
  30 DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
  31 DEFINE_CLK(mcfi2c1, "imx1-i2c.1", MCF_BUSCLK);
  32
  33 struct clk *mcf_clks[] = {
  34         &clk_pll,
  35         &clk_sys,
  36         &clk_mcftmr0,
  37         &clk_mcftmr1,
  38         &clk_mcfuart0,
  39         &clk_mcfuart1,
  40         &clk_mcfqspi0,
  41         &clk_mcfi2c0,
  42         &clk_mcfi2c1,
  43         NULL
  44 };
  45
  46 /***************************************************************************/
  47
  48 #ifdef CONFIG_M5249C3
  49
  50 static struct resource m5249_smc91x_resources[] = {
  51         {
  52                 .start          = 0xe0000300,
  53                 .end            = 0xe0000300 + 0x100,
  54                 .flags          = IORESOURCE_MEM,
  55         },
  56         {
  57                 .start          = MCF_IRQ_GPIO6,
  58                 .end            = MCF_IRQ_GPIO6,
  59                 .flags          = IORESOURCE_IRQ,
  60         },
  61 };
  62
  63 static struct platform_device m5249_smc91x = {
  64         .name                   = "smc91x",
  65         .id                     = 0,
  66         .num_resources          = ARRAY_SIZE(m5249_smc91x_resources),
  67         .resource               = m5249_smc91x_resources,
  68 };
  69
  70 #endif /* CONFIG_M5249C3 */
  71
  72 static struct platform_device *m5249_devices[] __initdata = {
  73 #ifdef CONFIG_M5249C3
  74         &m5249_smc91x,
  75 #endif
  76 };
  77
  78 /***************************************************************************/
  79
  80 static void __init m5249_qspi_init(void)
  81 {
  82 #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
  83         /* QSPI irq setup */
  84         writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0,
  85                MCFSIM_QSPIICR);
  86         mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI);
  87 #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
  88 }
  89
  90 /***************************************************************************/
  91
  92 static void __init m5249_i2c_init(void)
  93 {
  94 #if IS_ENABLED(CONFIG_I2C_IMX)
  95         u32 r;
  96
  97         /* first I2C controller uses regular irq setup */
  98         writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
  99                MCFSIM_I2CICR);
 100         mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
 101
 102         /* second I2C controller is completely different */
 103         r = readl(MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
 104         r &= ~MCFINTC2_INTPRI_BITS(0xf, MCF_IRQ_I2C1);
 105         r |= MCFINTC2_INTPRI_BITS(0x5, MCF_IRQ_I2C1);
 106         writel(r, MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
 107 #endif /* CONFIG_I2C_IMX */
 108 }
 109
 110 /***************************************************************************/
 111
 112 #ifdef CONFIG_M5249C3
 113
 114 static void __init m5249_smc91x_init(void)
 115 {
 116         u32  gpio;
 117
 118         /* Set the GPIO line as interrupt source for smc91x device */
 119         gpio = readl(MCFSIM2_GPIOINTENABLE);
 120         writel(gpio | 0x40, MCFSIM2_GPIOINTENABLE);
 121
 122         gpio = readl(MCFINTC2_INTPRI5);
 123         writel(gpio | 0x04000000, MCFINTC2_INTPRI5);
 124 }
 125
 126 #endif /* CONFIG_M5249C3 */
 127
 128 /***************************************************************************/
 129
 130 void __init config_BSP(char *commandp, int size)
 131 {
 132         mach_sched_init = hw_timer_init;
 133
 134 #ifdef CONFIG_M5249C3
 135         m5249_smc91x_init();
 136 #endif
 137         m5249_qspi_init();
 138         m5249_i2c_init();
 139 }
 140
 141 /***************************************************************************/
 142
 143 static int __init init_BSP(void)
 144 {
 145         platform_add_devices(m5249_devices, ARRAY_SIZE(m5249_devices));
 146         return 0;
 147 }
 148
 149 arch_initcall(init_BSP);
 150
 151 /***************************************************************************/