arch/m68k/include/asm/MC68EZ328.h

   1
   2 /* include/asm-m68knommu/MC68EZ328.h: 'EZ328 control registers
   3  *
   4  * Copyright (C) 1999  Vladimir Gurevich <vgurevic@cisco.com>
   5  *                     Bear & Hare Software, Inc.
   6  *
   7  * Based on include/asm-m68knommu/MC68332.h
   8  * Copyright (C) 1998  Kenneth Albanowski <kjahds@kjahds.com>,
   9  *                     The Silver Hammer Group, Ltd.
  10  *
  11  */
  12 #include <linux/compiler.h>
  13
  14 #ifndef _MC68EZ328_H_
  15 #define _MC68EZ328_H_
  16
  17 #define BYTE_REF(addr) (*((volatile unsigned char*)addr))
  18 #define WORD_REF(addr) (*((volatile unsigned short*)addr))
  19 #define LONG_REF(addr) (*((volatile unsigned long*)addr))
  20
  21 #define PUT_FIELD(field, val) (((val) << field##_SHIFT) & field##_MASK)
  22 #define GET_FIELD(reg, field) (((reg) & field##_MASK) >> field##_SHIFT)
  23
  24 /**********
  25  *
  26  * 0xFFFFF0xx -- System Control
  27  *
  28  **********/
  29
  30 /*
  31  * System Control Register (SCR)
  32  */
  33 #define SCR_ADDR        0xfffff000
  34 #define SCR             BYTE_REF(SCR_ADDR)
  35
  36 #define SCR_WDTH8       0x01    /* 8-Bit Width Select */
  37 #define SCR_DMAP        0x04    /* Double Map */
  38 #define SCR_SO          0x08    /* Supervisor Only */
  39 #define SCR_BETEN       0x10    /* Bus-Error Time-Out Enable */
  40 #define SCR_PRV         0x20    /* Privilege Violation */
  41 #define SCR_WPV         0x40    /* Write Protect Violation */
  42 #define SCR_BETO        0x80    /* Bus-Error TimeOut */
  43
  44 /*
  45  * Silicon ID Register (Mask Revision Register (MRR) for '328 Compatibility)
  46  */
  47 #define MRR_ADDR 0xfffff004
  48 #define MRR      LONG_REF(MRR_ADDR)
  49
  50 /**********
  51  *
  52  * 0xFFFFF1xx -- Chip-Select logic
  53  *
  54  **********/
  55
  56 /*
  57  * Chip Select Group Base Registers
  58  */
  59 #define CSGBA_ADDR      0xfffff100
  60 #define CSGBB_ADDR      0xfffff102
  61
  62 #define CSGBC_ADDR      0xfffff104
  63 #define CSGBD_ADDR      0xfffff106
  64
  65 #define CSGBA           WORD_REF(CSGBA_ADDR)
  66 #define CSGBB           WORD_REF(CSGBB_ADDR)
  67 #define CSGBC           WORD_REF(CSGBC_ADDR)
  68 #define CSGBD           WORD_REF(CSGBD_ADDR)
  69
  70 /*
  71  * Chip Select Registers
  72  */
  73 #define CSA_ADDR        0xfffff110
  74 #define CSB_ADDR        0xfffff112
  75 #define CSC_ADDR        0xfffff114
  76 #define CSD_ADDR        0xfffff116
  77
  78 #define CSA             WORD_REF(CSA_ADDR)
  79 #define CSB             WORD_REF(CSB_ADDR)
  80 #define CSC             WORD_REF(CSC_ADDR)
  81 #define CSD             WORD_REF(CSD_ADDR)
  82
  83 #define CSA_EN          0x0001          /* Chip-Select Enable */
  84 #define CSA_SIZ_MASK    0x000e          /* Chip-Select Size */
  85 #define CSA_SIZ_SHIFT   1
  86 #define CSA_WS_MASK     0x0070          /* Wait State */
  87 #define CSA_WS_SHIFT    4
  88 #define CSA_BSW         0x0080          /* Data Bus Width */
  89 #define CSA_FLASH       0x0100          /* FLASH Memory Support */
  90 #define CSA_RO          0x8000          /* Read-Only */
  91
  92 #define CSB_EN          0x0001          /* Chip-Select Enable */
  93 #define CSB_SIZ_MASK    0x000e          /* Chip-Select Size */
  94 #define CSB_SIZ_SHIFT   1
  95 #define CSB_WS_MASK     0x0070          /* Wait State */
  96 #define CSB_WS_SHIFT    4
  97 #define CSB_BSW         0x0080          /* Data Bus Width */
  98 #define CSB_FLASH       0x0100          /* FLASH Memory Support */
  99 #define CSB_UPSIZ_MASK  0x1800          /* Unprotected memory block size */
 100 #define CSB_UPSIZ_SHIFT 11
 101 #define CSB_ROP         0x2000          /* Readonly if protected */
 102 #define CSB_SOP         0x4000          /* Supervisor only if protected */
 103 #define CSB_RO          0x8000          /* Read-Only */
 104
 105 #define CSC_EN          0x0001          /* Chip-Select Enable */
 106 #define CSC_SIZ_MASK    0x000e          /* Chip-Select Size */
 107 #define CSC_SIZ_SHIFT   1
 108 #define CSC_WS_MASK     0x0070          /* Wait State */
 109 #define CSC_WS_SHIFT    4
 110 #define CSC_BSW         0x0080          /* Data Bus Width */
 111 #define CSC_FLASH       0x0100          /* FLASH Memory Support */
 112 #define CSC_UPSIZ_MASK  0x1800          /* Unprotected memory block size */
 113 #define CSC_UPSIZ_SHIFT 11
 114 #define CSC_ROP         0x2000          /* Readonly if protected */
 115 #define CSC_SOP         0x4000          /* Supervisor only if protected */
 116 #define CSC_RO          0x8000          /* Read-Only */
 117
 118 #define CSD_EN          0x0001          /* Chip-Select Enable */
 119 #define CSD_SIZ_MASK    0x000e          /* Chip-Select Size */
 120 #define CSD_SIZ_SHIFT   1
 121 #define CSD_WS_MASK     0x0070          /* Wait State */
 122 #define CSD_WS_SHIFT    4
 123 #define CSD_BSW         0x0080          /* Data Bus Width */
 124 #define CSD_FLASH       0x0100          /* FLASH Memory Support */
 125 #define CSD_DRAM        0x0200          /* Dram Selection */
 126 #define CSD_COMB        0x0400          /* Combining */
 127 #define CSD_UPSIZ_MASK  0x1800          /* Unprotected memory block size */
 128 #define CSD_UPSIZ_SHIFT 11
 129 #define CSD_ROP         0x2000          /* Readonly if protected */
 130 #define CSD_SOP         0x4000          /* Supervisor only if protected */
 131 #define CSD_RO          0x8000          /* Read-Only */
 132
 133 /*
 134  * Emulation Chip-Select Register
 135  */
 136 #define EMUCS_ADDR      0xfffff118
 137 #define EMUCS           WORD_REF(EMUCS_ADDR)
 138
 139 #define EMUCS_WS_MASK   0x0070
 140 #define EMUCS_WS_SHIFT  4
 141
 142 /**********
 143  *
 144  * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
 145  *
 146  **********/
 147
 148 /*
 149  * PLL Control Register
 150  */
 151 #define PLLCR_ADDR      0xfffff200
 152 #define PLLCR           WORD_REF(PLLCR_ADDR)
 153
 154 #define PLLCR_DISPLL           0x0008   /* Disable PLL */
 155 #define PLLCR_CLKEN            0x0010   /* Clock (CLKO pin) enable */
 156 #define PLLCR_PRESC            0x0020   /* VCO prescaler */
 157 #define PLLCR_SYSCLK_SEL_MASK  0x0700   /* System Clock Selection */
 158 #define PLLCR_SYSCLK_SEL_SHIFT 8
 159 #define PLLCR_LCDCLK_SEL_MASK  0x3800   /* LCD Clock Selection */
 160 #define PLLCR_LCDCLK_SEL_SHIFT 11
 161
 162 /* '328-compatible definitions */
 163 #define PLLCR_PIXCLK_SEL_MASK   PLLCR_LCDCLK_SEL_MASK
 164 #define PLLCR_PIXCLK_SEL_SHIFT  PLLCR_LCDCLK_SEL_SHIFT
 165
 166 /*
 167  * PLL Frequency Select Register
 168  */
 169 #define PLLFSR_ADDR     0xfffff202
 170 #define PLLFSR          WORD_REF(PLLFSR_ADDR)
 171
 172 #define PLLFSR_PC_MASK  0x00ff          /* P Count */
 173 #define PLLFSR_PC_SHIFT 0
 174 #define PLLFSR_QC_MASK  0x0f00          /* Q Count */
 175 #define PLLFSR_QC_SHIFT 8
 176 #define PLLFSR_PROT     0x4000          /* Protect P & Q */
 177 #define PLLFSR_CLK32    0x8000          /* Clock 32 (kHz) */
 178
 179 /*
 180  * Power Control Register
 181  */
 182 #define PCTRL_ADDR      0xfffff207
 183 #define PCTRL           BYTE_REF(PCTRL_ADDR)
 184
 185 #define PCTRL_WIDTH_MASK        0x1f    /* CPU Clock bursts width */
 186 #define PCTRL_WIDTH_SHIFT       0
 187 #define PCTRL_PCEN              0x80    /* Power Control Enable */
 188
 189 /**********
 190  *
 191  * 0xFFFFF3xx -- Interrupt Controller
 192  *
 193  **********/
 194
 195 /*
 196  * Interrupt Vector Register
 197  */
 198 #define IVR_ADDR        0xfffff300
 199 #define IVR             BYTE_REF(IVR_ADDR)
 200
 201 #define IVR_VECTOR_MASK 0xF8
 202
 203 /*
 204  * Interrupt control Register
 205  */
 206 #define ICR_ADDR        0xfffff302
 207 #define ICR             WORD_REF(ICR_ADDR)
 208
 209 #define ICR_POL5        0x0080  /* Polarity Control for IRQ5 */
 210 #define ICR_ET6         0x0100  /* Edge Trigger Select for IRQ6 */
 211 #define ICR_ET3         0x0200  /* Edge Trigger Select for IRQ3 */
 212 #define ICR_ET2         0x0400  /* Edge Trigger Select for IRQ2 */
 213 #define ICR_ET1         0x0800  /* Edge Trigger Select for IRQ1 */
 214 #define ICR_POL6        0x1000  /* Polarity Control for IRQ6 */
 215 #define ICR_POL3        0x2000  /* Polarity Control for IRQ3 */
 216 #define ICR_POL2        0x4000  /* Polarity Control for IRQ2 */
 217 #define ICR_POL1        0x8000  /* Polarity Control for IRQ1 */
 218
 219 /*
 220  * Interrupt Mask Register
 221  */
 222 #define IMR_ADDR        0xfffff304
 223 #define IMR             LONG_REF(IMR_ADDR)
 224
 225 /*
 226  * Define the names for bit positions first. This is useful for
 227  * request_irq
 228  */
 229 #define SPI_IRQ_NUM     0       /* SPI interrupt */
 230 #define TMR_IRQ_NUM     1       /* Timer interrupt */
 231 #define UART_IRQ_NUM    2       /* UART interrupt */
 232 #define WDT_IRQ_NUM     3       /* Watchdog Timer interrupt */
 233 #define RTC_IRQ_NUM     4       /* RTC interrupt */
 234 #define KB_IRQ_NUM      6       /* Keyboard Interrupt */
 235 #define PWM_IRQ_NUM     7       /* Pulse-Width Modulator int. */
 236 #define INT0_IRQ_NUM    8       /* External INT0 */
 237 #define INT1_IRQ_NUM    9       /* External INT1 */
 238 #define INT2_IRQ_NUM    10      /* External INT2 */
 239 #define INT3_IRQ_NUM    11      /* External INT3 */
 240 #define IRQ1_IRQ_NUM    16      /* IRQ1 */
 241 #define IRQ2_IRQ_NUM    17      /* IRQ2 */
 242 #define IRQ3_IRQ_NUM    18      /* IRQ3 */
 243 #define IRQ6_IRQ_NUM    19      /* IRQ6 */
 244 #define IRQ5_IRQ_NUM    20      /* IRQ5 */
 245 #define SAM_IRQ_NUM     22      /* Sampling Timer for RTC */
 246 #define EMIQ_IRQ_NUM    23      /* Emulator Interrupt */
 247
 248 /* '328-compatible definitions */
 249 #define SPIM_IRQ_NUM    SPI_IRQ_NUM
 250 #define TMR1_IRQ_NUM    TMR_IRQ_NUM
 251
 252 /*
 253  * Here go the bitmasks themselves
 254  */
 255 #define IMR_MSPI        (1 << SPI_IRQ_NUM)      /* Mask SPI interrupt */
 256 #define IMR_MTMR        (1 << TMR_IRQ_NUM)      /* Mask Timer interrupt */
 257 #define IMR_MUART       (1 << UART_IRQ_NUM)     /* Mask UART interrupt */
 258 #define IMR_MWDT        (1 << WDT_IRQ_NUM)      /* Mask Watchdog Timer interrupt */
 259 #define IMR_MRTC        (1 << RTC_IRQ_NUM)      /* Mask RTC interrupt */
 260 #define IMR_MKB         (1 << KB_IRQ_NUM)       /* Mask Keyboard Interrupt */
 261 #define IMR_MPWM        (1 << PWM_IRQ_NUM)      /* Mask Pulse-Width Modulator int. */
 262 #define IMR_MINT0       (1 << INT0_IRQ_NUM)     /* Mask External INT0 */
 263 #define IMR_MINT1       (1 << INT1_IRQ_NUM)     /* Mask External INT1 */
 264 #define IMR_MINT2       (1 << INT2_IRQ_NUM)     /* Mask External INT2 */
 265 #define IMR_MINT3       (1 << INT3_IRQ_NUM)     /* Mask External INT3 */
 266 #define IMR_MIRQ1       (1 << IRQ1_IRQ_NUM)     /* Mask IRQ1 */
 267 #define IMR_MIRQ2       (1 << IRQ2_IRQ_NUM)     /* Mask IRQ2 */
 268 #define IMR_MIRQ3       (1 << IRQ3_IRQ_NUM)     /* Mask IRQ3 */
 269 #define IMR_MIRQ6       (1 << IRQ6_IRQ_NUM)     /* Mask IRQ6 */
 270 #define IMR_MIRQ5       (1 << IRQ5_IRQ_NUM)     /* Mask IRQ5 */
 271 #define IMR_MSAM        (1 << SAM_IRQ_NUM)      /* Mask Sampling Timer for RTC */
 272 #define IMR_MEMIQ       (1 << EMIQ_IRQ_NUM)     /* Mask Emulator Interrupt */
 273
 274 /* '328-compatible definitions */
 275 #define IMR_MSPIM       IMR_MSPI
 276 #define IMR_MTMR1       IMR_MTMR
 277
 278 /*
 279  * Interrupt Status Register
 280  */
 281 #define ISR_ADDR        0xfffff30c
 282 #define ISR             LONG_REF(ISR_ADDR)
 283
 284 #define ISR_SPI         (1 << SPI_IRQ_NUM)      /* SPI interrupt */
 285 #define ISR_TMR         (1 << TMR_IRQ_NUM)      /* Timer interrupt */
 286 #define ISR_UART        (1 << UART_IRQ_NUM)     /* UART interrupt */
 287 #define ISR_WDT         (1 << WDT_IRQ_NUM)      /* Watchdog Timer interrupt */
 288 #define ISR_RTC         (1 << RTC_IRQ_NUM)      /* RTC interrupt */
 289 #define ISR_KB          (1 << KB_IRQ_NUM)       /* Keyboard Interrupt */
 290 #define ISR_PWM         (1 << PWM_IRQ_NUM)      /* Pulse-Width Modulator interrupt */
 291 #define ISR_INT0        (1 << INT0_IRQ_NUM)     /* External INT0 */
 292 #define ISR_INT1        (1 << INT1_IRQ_NUM)     /* External INT1 */
 293 #define ISR_INT2        (1 << INT2_IRQ_NUM)     /* External INT2 */
 294 #define ISR_INT3        (1 << INT3_IRQ_NUM)     /* External INT3 */
 295 #define ISR_IRQ1        (1 << IRQ1_IRQ_NUM)     /* IRQ1 */
 296 #define ISR_IRQ2        (1 << IRQ2_IRQ_NUM)     /* IRQ2 */
 297 #define ISR_IRQ3        (1 << IRQ3_IRQ_NUM)     /* IRQ3 */
 298 #define ISR_IRQ6        (1 << IRQ6_IRQ_NUM)     /* IRQ6 */
 299 #define ISR_IRQ5        (1 << IRQ5_IRQ_NUM)     /* IRQ5 */
 300 #define ISR_SAM         (1 << SAM_IRQ_NUM)      /* Sampling Timer for RTC */
 301 #define ISR_EMIQ        (1 << EMIQ_IRQ_NUM)     /* Emulator Interrupt */
 302
 303 /* '328-compatible definitions */
 304 #define ISR_SPIM        ISR_SPI
 305 #define ISR_TMR1        ISR_TMR
 306
 307 /*
 308  * Interrupt Pending Register
 309  */
 310 #define IPR_ADDR        0xfffff30c
 311 #define IPR             LONG_REF(IPR_ADDR)
 312
 313 #define IPR_SPI         (1 << SPI_IRQ_NUM)      /* SPI interrupt */
 314 #define IPR_TMR         (1 << TMR_IRQ_NUM)      /* Timer interrupt */
 315 #define IPR_UART        (1 << UART_IRQ_NUM)     /* UART interrupt */
 316 #define IPR_WDT         (1 << WDT_IRQ_NUM)      /* Watchdog Timer interrupt */
 317 #define IPR_RTC         (1 << RTC_IRQ_NUM)      /* RTC interrupt */
 318 #define IPR_KB          (1 << KB_IRQ_NUM)       /* Keyboard Interrupt */
 319 #define IPR_PWM         (1 << PWM_IRQ_NUM)      /* Pulse-Width Modulator interrupt */
 320 #define IPR_INT0        (1 << INT0_IRQ_NUM)     /* External INT0 */
 321 #define IPR_INT1        (1 << INT1_IRQ_NUM)     /* External INT1 */
 322 #define IPR_INT2        (1 << INT2_IRQ_NUM)     /* External INT2 */
 323 #define IPR_INT3        (1 << INT3_IRQ_NUM)     /* External INT3 */
 324 #define IPR_IRQ1        (1 << IRQ1_IRQ_NUM)     /* IRQ1 */
 325 #define IPR_IRQ2        (1 << IRQ2_IRQ_NUM)     /* IRQ2 */
 326 #define IPR_IRQ3        (1 << IRQ3_IRQ_NUM)     /* IRQ3 */
 327 #define IPR_IRQ6        (1 << IRQ6_IRQ_NUM)     /* IRQ6 */
 328 #define IPR_IRQ5        (1 << IRQ5_IRQ_NUM)     /* IRQ5 */
 329 #define IPR_SAM         (1 << SAM_IRQ_NUM)      /* Sampling Timer for RTC */
 330 #define IPR_EMIQ        (1 << EMIQ_IRQ_NUM)     /* Emulator Interrupt */
 331
 332 /* '328-compatible definitions */
 333 #define IPR_SPIM        IPR_SPI
 334 #define IPR_TMR1        IPR_TMR
 335
 336 /**********
 337  *
 338  * 0xFFFFF4xx -- Parallel Ports
 339  *
 340  **********/
 341
 342 /*
 343  * Port A
 344  */
 345 #define PADIR_ADDR      0xfffff400              /* Port A direction reg */
 346 #define PADATA_ADDR     0xfffff401              /* Port A data register */
 347 #define PAPUEN_ADDR     0xfffff402              /* Port A Pull-Up enable reg */
 348
 349 #define PADIR           BYTE_REF(PADIR_ADDR)
 350 #define PADATA          BYTE_REF(PADATA_ADDR)
 351 #define PAPUEN          BYTE_REF(PAPUEN_ADDR)
 352
 353 #define PA(x)           (1 << (x))
 354
 355 /*
 356  * Port B
 357  */
 358 #define PBDIR_ADDR      0xfffff408              /* Port B direction reg */
 359 #define PBDATA_ADDR     0xfffff409              /* Port B data register */
 360 #define PBPUEN_ADDR     0xfffff40a              /* Port B Pull-Up enable reg */
 361 #define PBSEL_ADDR      0xfffff40b              /* Port B Select Register */
 362
 363 #define PBDIR           BYTE_REF(PBDIR_ADDR)
 364 #define PBDATA          BYTE_REF(PBDATA_ADDR)
 365 #define PBPUEN          BYTE_REF(PBPUEN_ADDR)
 366 #define PBSEL           BYTE_REF(PBSEL_ADDR)
 367
 368 #define PB(x)           (1 << (x))
 369
 370 #define PB_CSB0         0x01    /* Use CSB0      as PB[0] */
 371 #define PB_CSB1         0x02    /* Use CSB1      as PB[1] */
 372 #define PB_CSC0_RAS0    0x04    /* Use CSC0/RAS0 as PB[2] */
 373 #define PB_CSC1_RAS1    0x08    /* Use CSC1/RAS1 as PB[3] */
 374 #define PB_CSD0_CAS0    0x10    /* Use CSD0/CAS0 as PB[4] */
 375 #define PB_CSD1_CAS1    0x20    /* Use CSD1/CAS1 as PB[5] */
 376 #define PB_TIN_TOUT     0x40    /* Use TIN/TOUT  as PB[6] */
 377 #define PB_PWMO         0x80    /* Use PWMO      as PB[7] */
 378
 379 /*
 380  * Port C
 381  */
 382 #define PCDIR_ADDR      0xfffff410              /* Port C direction reg */
 383 #define PCDATA_ADDR     0xfffff411              /* Port C data register */
 384 #define PCPDEN_ADDR     0xfffff412              /* Port C Pull-Down enb. reg */
 385 #define PCSEL_ADDR      0xfffff413              /* Port C Select Register */
 386
 387 #define PCDIR           BYTE_REF(PCDIR_ADDR)
 388 #define PCDATA          BYTE_REF(PCDATA_ADDR)
 389 #define PCPDEN          BYTE_REF(PCPDEN_ADDR)
 390 #define PCSEL           BYTE_REF(PCSEL_ADDR)
 391
 392 #define PC(x)           (1 << (x))
 393
 394 #define PC_LD0          0x01    /* Use LD0  as PC[0] */
 395 #define PC_LD1          0x02    /* Use LD1  as PC[1] */
 396 #define PC_LD2          0x04    /* Use LD2  as PC[2] */
 397 #define PC_LD3          0x08    /* Use LD3  as PC[3] */
 398 #define PC_LFLM         0x10    /* Use LFLM as PC[4] */
 399 #define PC_LLP          0x20    /* Use LLP  as PC[5] */
 400 #define PC_LCLK         0x40    /* Use LCLK as PC[6] */
 401 #define PC_LACD         0x80    /* Use LACD as PC[7] */
 402
 403 /*
 404  * Port D
 405  */
 406 #define PDDIR_ADDR      0xfffff418              /* Port D direction reg */
 407 #define PDDATA_ADDR     0xfffff419              /* Port D data register */
 408 #define PDPUEN_ADDR     0xfffff41a              /* Port D Pull-Up enable reg */
 409 #define PDSEL_ADDR      0xfffff41b              /* Port D Select Register */
 410 #define PDPOL_ADDR      0xfffff41c              /* Port D Polarity Register */
 411 #define PDIRQEN_ADDR    0xfffff41d              /* Port D IRQ enable register */
 412 #define PDKBEN_ADDR     0xfffff41e              /* Port D Keyboard Enable reg */
 413 #define PDIQEG_ADDR     0xfffff41f              /* Port D IRQ Edge Register */
 414
 415 #define PDDIR           BYTE_REF(PDDIR_ADDR)
 416 #define PDDATA          BYTE_REF(PDDATA_ADDR)
 417 #define PDPUEN          BYTE_REF(PDPUEN_ADDR)
 418 #define PDSEL           BYTE_REF(PDSEL_ADDR)
 419 #define PDPOL           BYTE_REF(PDPOL_ADDR)
 420 #define PDIRQEN         BYTE_REF(PDIRQEN_ADDR)
 421 #define PDKBEN          BYTE_REF(PDKBEN_ADDR)
 422 #define PDIQEG          BYTE_REF(PDIQEG_ADDR)
 423
 424 #define PD(x)           (1 << (x))
 425
 426 #define PD_INT0         0x01    /* Use INT0 as PD[0] */
 427 #define PD_INT1         0x02    /* Use INT1 as PD[1] */
 428 #define PD_INT2         0x04    /* Use INT2 as PD[2] */
 429 #define PD_INT3         0x08    /* Use INT3 as PD[3] */
 430 #define PD_IRQ1         0x10    /* Use IRQ1 as PD[4] */
 431 #define PD_IRQ2         0x20    /* Use IRQ2 as PD[5] */
 432 #define PD_IRQ3         0x40    /* Use IRQ3 as PD[6] */
 433 #define PD_IRQ6         0x80    /* Use IRQ6 as PD[7] */
 434
 435 /*
 436  * Port E
 437  */
 438 #define PEDIR_ADDR      0xfffff420              /* Port E direction reg */
 439 #define PEDATA_ADDR     0xfffff421              /* Port E data register */
 440 #define PEPUEN_ADDR     0xfffff422              /* Port E Pull-Up enable reg */
 441 #define PESEL_ADDR      0xfffff423              /* Port E Select Register */
 442
 443 #define PEDIR           BYTE_REF(PEDIR_ADDR)
 444 #define PEDATA          BYTE_REF(PEDATA_ADDR)
 445 #define PEPUEN          BYTE_REF(PEPUEN_ADDR)
 446 #define PESEL           BYTE_REF(PESEL_ADDR)
 447
 448 #define PE(x)           (1 << (x))
 449
 450 #define PE_SPMTXD       0x01    /* Use SPMTXD as PE[0] */
 451 #define PE_SPMRXD       0x02    /* Use SPMRXD as PE[1] */
 452 #define PE_SPMCLK       0x04    /* Use SPMCLK as PE[2] */
 453 #define PE_DWE          0x08    /* Use DWE    as PE[3] */
 454 #define PE_RXD          0x10    /* Use RXD    as PE[4] */
 455 #define PE_TXD          0x20    /* Use TXD    as PE[5] */
 456 #define PE_RTS          0x40    /* Use RTS    as PE[6] */
 457 #define PE_CTS          0x80    /* Use CTS    as PE[7] */
 458
 459 /*
 460  * Port F
 461  */
 462 #define PFDIR_ADDR      0xfffff428              /* Port F direction reg */
 463 #define PFDATA_ADDR     0xfffff429              /* Port F data register */
 464 #define PFPUEN_ADDR     0xfffff42a              /* Port F Pull-Up enable reg */
 465 #define PFSEL_ADDR      0xfffff42b              /* Port F Select Register */
 466
 467 #define PFDIR           BYTE_REF(PFDIR_ADDR)
 468 #define PFDATA          BYTE_REF(PFDATA_ADDR)
 469 #define PFPUEN          BYTE_REF(PFPUEN_ADDR)
 470 #define PFSEL           BYTE_REF(PFSEL_ADDR)
 471
 472 #define PF(x)           (1 << (x))
 473
 474 #define PF_LCONTRAST    0x01    /* Use LCONTRAST as PF[0] */
 475 #define PF_IRQ5         0x02    /* Use IRQ5      as PF[1] */
 476 #define PF_CLKO         0x04    /* Use CLKO      as PF[2] */
 477 #define PF_A20          0x08    /* Use A20       as PF[3] */
 478 #define PF_A21          0x10    /* Use A21       as PF[4] */
 479 #define PF_A22          0x20    /* Use A22       as PF[5] */
 480 #define PF_A23          0x40    /* Use A23       as PF[6] */
 481 #define PF_CSA1         0x80    /* Use CSA1      as PF[7] */
 482
 483 /*
 484  * Port G
 485  */
 486 #define PGDIR_ADDR      0xfffff430              /* Port G direction reg */
 487 #define PGDATA_ADDR     0xfffff431              /* Port G data register */
 488 #define PGPUEN_ADDR     0xfffff432              /* Port G Pull-Up enable reg */
 489 #define PGSEL_ADDR      0xfffff433              /* Port G Select Register */
 490
 491 #define PGDIR           BYTE_REF(PGDIR_ADDR)
 492 #define PGDATA          BYTE_REF(PGDATA_ADDR)
 493 #define PGPUEN          BYTE_REF(PGPUEN_ADDR)
 494 #define PGSEL           BYTE_REF(PGSEL_ADDR)
 495
 496 #define PG(x)           (1 << (x))
 497
 498 #define PG_BUSW_DTACK   0x01    /* Use BUSW/DTACK as PG[0] */
 499 #define PG_A0           0x02    /* Use A0         as PG[1] */
 500 #define PG_EMUIRQ       0x04    /* Use EMUIRQ     as PG[2] */
 501 #define PG_HIZ_P_D      0x08    /* Use HIZ/P/D    as PG[3] */
 502 #define PG_EMUCS        0x10    /* Use EMUCS      as PG[4] */
 503 #define PG_EMUBRK       0x20    /* Use EMUBRK     as PG[5] */
 504
 505 /**********
 506  *
 507  * 0xFFFFF5xx -- Pulse-Width Modulator (PWM)
 508  *
 509  **********/
 510
 511 /*
 512  * PWM Control Register
 513  */
 514 #define PWMC_ADDR       0xfffff500
 515 #define PWMC            WORD_REF(PWMC_ADDR)
 516
 517 #define PWMC_CLKSEL_MASK        0x0003  /* Clock Selection */
 518 #define PWMC_CLKSEL_SHIFT       0
 519 #define PWMC_REPEAT_MASK        0x000c  /* Sample Repeats */
 520 #define PWMC_REPEAT_SHIFT       2
 521 #define PWMC_EN                 0x0010  /* Enable PWM */
 522 #define PMNC_FIFOAV             0x0020  /* FIFO Available */
 523 #define PWMC_IRQEN              0x0040  /* Interrupt Request Enable */
 524 #define PWMC_IRQ                0x0080  /* Interrupt Request (FIFO empty) */
 525 #define PWMC_PRESCALER_MASK     0x7f00  /* Incoming Clock prescaler */
 526 #define PWMC_PRESCALER_SHIFT    8
 527 #define PWMC_CLKSRC             0x8000  /* Clock Source Select */
 528
 529 /* '328-compatible definitions */
 530 #define PWMC_PWMEN      PWMC_EN
 531
 532 /*
 533  * PWM Sample Register
 534  */
 535 #define PWMS_ADDR       0xfffff502
 536 #define PWMS            WORD_REF(PWMS_ADDR)
 537
 538 /*
 539  * PWM Period Register
 540  */
 541 #define PWMP_ADDR       0xfffff504
 542 #define PWMP            BYTE_REF(PWMP_ADDR)
 543
 544 /*
 545  * PWM Counter Register
 546  */
 547 #define PWMCNT_ADDR     0xfffff505
 548 #define PWMCNT          BYTE_REF(PWMCNT_ADDR)
 549
 550 /**********
 551  *
 552  * 0xFFFFF6xx -- General-Purpose Timer
 553  *
 554  **********/
 555
 556 /*
 557  * Timer Control register
 558  */
 559 #define TCTL_ADDR       0xfffff600
 560 #define TCTL            WORD_REF(TCTL_ADDR)
 561
 562 #define TCTL_TEN                0x0001  /* Timer Enable  */
 563 #define TCTL_CLKSOURCE_MASK     0x000e  /* Clock Source: */
 564 #define   TCTL_CLKSOURCE_STOP      0x0000       /* Stop count (disabled)    */
 565 #define   TCTL_CLKSOURCE_SYSCLK    0x0002       /* SYSCLK to prescaler      */
 566 #define   TCTL_CLKSOURCE_SYSCLK_16 0x0004       /* SYSCLK/16 to prescaler   */
 567 #define   TCTL_CLKSOURCE_TIN       0x0006       /* TIN to prescaler         */
 568 #define   TCTL_CLKSOURCE_32KHZ     0x0008       /* 32kHz clock to prescaler */
 569 #define TCTL_IRQEN              0x0010  /* IRQ Enable    */
 570 #define TCTL_OM                 0x0020  /* Output Mode   */
 571 #define TCTL_CAP_MASK           0x00c0  /* Capture Edge: */
 572 #define   TCTL_CAP_RE           0x0040          /* Capture on rizing edge   */
 573 #define   TCTL_CAP_FE           0x0080          /* Capture on falling edge  */
 574 #define TCTL_FRR                0x0010  /* Free-Run Mode */
 575
 576 /* '328-compatible definitions */
 577 #define TCTL1_ADDR      TCTL_ADDR
 578 #define TCTL1           TCTL
 579
 580 /*
 581  * Timer Prescaler Register
 582  */
 583 #define TPRER_ADDR      0xfffff602
 584 #define TPRER           WORD_REF(TPRER_ADDR)
 585
 586 /* '328-compatible definitions */
 587 #define TPRER1_ADDR     TPRER_ADDR
 588 #define TPRER1          TPRER
 589
 590 /*
 591  * Timer Compare Register
 592  */
 593 #define TCMP_ADDR       0xfffff604
 594 #define TCMP            WORD_REF(TCMP_ADDR)
 595
 596 /* '328-compatible definitions */
 597 #define TCMP1_ADDR      TCMP_ADDR
 598 #define TCMP1           TCMP
 599
 600 /*
 601  * Timer Capture register
 602  */
 603 #define TCR_ADDR        0xfffff606
 604 #define TCR             WORD_REF(TCR_ADDR)
 605
 606 /* '328-compatible definitions */
 607 #define TCR1_ADDR       TCR_ADDR
 608 #define TCR1            TCR
 609
 610 /*
 611  * Timer Counter Register
 612  */
 613 #define TCN_ADDR        0xfffff608
 614 #define TCN             WORD_REF(TCN_ADDR)
 615
 616 /* '328-compatible definitions */
 617 #define TCN1_ADDR       TCN_ADDR
 618 #define TCN1            TCN
 619
 620 /*
 621  * Timer Status Register
 622  */
 623 #define TSTAT_ADDR      0xfffff60a
 624 #define TSTAT           WORD_REF(TSTAT_ADDR)
 625
 626 #define TSTAT_COMP      0x0001          /* Compare Event occurred */
 627 #define TSTAT_CAPT      0x0001          /* Capture Event occurred */
 628
 629 /* '328-compatible definitions */
 630 #define TSTAT1_ADDR     TSTAT_ADDR
 631 #define TSTAT1          TSTAT
 632
 633 /**********
 634  *
 635  * 0xFFFFF8xx -- Serial Peripheral Interface Master (SPIM)
 636  *
 637  **********/
 638
 639 /*
 640  * SPIM Data Register
 641  */
 642 #define SPIMDATA_ADDR   0xfffff800
 643 #define SPIMDATA        WORD_REF(SPIMDATA_ADDR)
 644
 645 /*
 646  * SPIM Control/Status Register
 647  */
 648 #define SPIMCONT_ADDR   0xfffff802
 649 #define SPIMCONT        WORD_REF(SPIMCONT_ADDR)
 650
 651 #define SPIMCONT_BIT_COUNT_MASK  0x000f /* Transfer Length in Bytes */
 652 #define SPIMCONT_BIT_COUNT_SHIFT 0
 653 #define SPIMCONT_POL             0x0010 /* SPMCLK Signel Polarity */
 654 #define SPIMCONT_PHA             0x0020 /* Clock/Data phase relationship */
 655 #define SPIMCONT_IRQEN           0x0040 /* IRQ Enable */
 656 #define SPIMCONT_IRQ             0x0080 /* Interrupt Request */
 657 #define SPIMCONT_XCH             0x0100 /* Exchange */
 658 #define SPIMCONT_ENABLE          0x0200 /* Enable SPIM */
 659 #define SPIMCONT_DATA_RATE_MASK  0xe000 /* SPIM Data Rate */
 660 #define SPIMCONT_DATA_RATE_SHIFT 13
 661
 662 /* '328-compatible definitions */
 663 #define SPIMCONT_SPIMIRQ        SPIMCONT_IRQ
 664 #define SPIMCONT_SPIMEN         SPIMCONT_ENABLE
 665
 666 /**********
 667  *
 668  * 0xFFFFF9xx -- UART
 669  *
 670  **********/
 671
 672 /*
 673  * UART Status/Control Register
 674  */
 675 #define USTCNT_ADDR     0xfffff900
 676 #define USTCNT          WORD_REF(USTCNT_ADDR)
 677
 678 #define USTCNT_TXAE     0x0001  /* Transmitter Available Interrupt Enable */
 679 #define USTCNT_TXHE     0x0002  /* Transmitter Half Empty Enable */
 680 #define USTCNT_TXEE     0x0004  /* Transmitter Empty Interrupt Enable */
 681 #define USTCNT_RXRE     0x0008  /* Receiver Ready Interrupt Enable */
 682 #define USTCNT_RXHE     0x0010  /* Receiver Half-Full Interrupt Enable */
 683 #define USTCNT_RXFE     0x0020  /* Receiver Full Interrupt Enable */
 684 #define USTCNT_CTSD     0x0040  /* CTS Delta Interrupt Enable */
 685 #define USTCNT_ODEN     0x0080  /* Old Data Interrupt Enable */
 686 #define USTCNT_8_7      0x0100  /* Eight or seven-bit transmission */
 687 #define USTCNT_STOP     0x0200  /* Stop bit transmission */
 688 #define USTCNT_ODD      0x0400  /* Odd Parity */
 689 #define USTCNT_PEN      0x0800  /* Parity Enable */
 690 #define USTCNT_CLKM     0x1000  /* Clock Mode Select */
 691 #define USTCNT_TXEN     0x2000  /* Transmitter Enable */
 692 #define USTCNT_RXEN     0x4000  /* Receiver Enable */
 693 #define USTCNT_UEN      0x8000  /* UART Enable */
 694
 695 /* '328-compatible definitions */
 696 #define USTCNT_TXAVAILEN        USTCNT_TXAE
 697 #define USTCNT_TXHALFEN         USTCNT_TXHE
 698 #define USTCNT_TXEMPTYEN        USTCNT_TXEE
 699 #define USTCNT_RXREADYEN        USTCNT_RXRE
 700 #define USTCNT_RXHALFEN         USTCNT_RXHE
 701 #define USTCNT_RXFULLEN         USTCNT_RXFE
 702 #define USTCNT_CTSDELTAEN       USTCNT_CTSD
 703 #define USTCNT_ODD_EVEN         USTCNT_ODD
 704 #define USTCNT_PARITYEN         USTCNT_PEN
 705 #define USTCNT_CLKMODE          USTCNT_CLKM
 706 #define USTCNT_UARTEN           USTCNT_UEN
 707
 708 /*
 709  * UART Baud Control Register
 710  */
 711 #define UBAUD_ADDR      0xfffff902
 712 #define UBAUD           WORD_REF(UBAUD_ADDR)
 713
 714 #define UBAUD_PRESCALER_MASK    0x003f  /* Actual divisor is 65 - PRESCALER */
 715 #define UBAUD_PRESCALER_SHIFT   0
 716 #define UBAUD_DIVIDE_MASK       0x0700  /* Baud Rate freq. divisor */
 717 #define UBAUD_DIVIDE_SHIFT      8
 718 #define UBAUD_BAUD_SRC          0x0800  /* Baud Rate Source */
 719 #define UBAUD_UCLKDIR           0x2000  /* UCLK Direction */
 720
 721 /*
 722  * UART Receiver Register
 723  */
 724 #define URX_ADDR        0xfffff904
 725 #define URX             WORD_REF(URX_ADDR)
 726
 727 #define URX_RXDATA_ADDR 0xfffff905
 728 #define URX_RXDATA      BYTE_REF(URX_RXDATA_ADDR)
 729
 730 #define URX_RXDATA_MASK  0x00ff /* Received data */
 731 #define URX_RXDATA_SHIFT 0
 732 #define URX_PARITY_ERROR 0x0100 /* Parity Error */
 733 #define URX_BREAK        0x0200 /* Break Detected */
 734 #define URX_FRAME_ERROR  0x0400 /* Framing Error */
 735 #define URX_OVRUN        0x0800 /* Serial Overrun */
 736 #define URX_OLD_DATA     0x1000 /* Old data in FIFO */
 737 #define URX_DATA_READY   0x2000 /* Data Ready (FIFO not empty) */
 738 #define URX_FIFO_HALF    0x4000 /* FIFO is Half-Full */
 739 #define URX_FIFO_FULL    0x8000 /* FIFO is Full */
 740
 741 /*
 742  * UART Transmitter Register
 743  */
 744 #define UTX_ADDR        0xfffff906
 745 #define UTX             WORD_REF(UTX_ADDR)
 746
 747 #define UTX_TXDATA_ADDR 0xfffff907
 748 #define UTX_TXDATA      BYTE_REF(UTX_TXDATA_ADDR)
 749
 750 #define UTX_TXDATA_MASK  0x00ff /* Data to be transmitted */
 751 #define UTX_TXDATA_SHIFT 0
 752 #define UTX_CTS_DELTA    0x0100 /* CTS changed */
 753 #define UTX_CTS_STAT     0x0200 /* CTS State */
 754 #define UTX_BUSY         0x0400 /* FIFO is busy, sending a character */
 755 #define UTX_NOCTS        0x0800 /* Ignore CTS */
 756 #define UTX_SEND_BREAK   0x1000 /* Send a BREAK */
 757 #define UTX_TX_AVAIL     0x2000 /* Transmit FIFO has a slot available */
 758 #define UTX_FIFO_HALF    0x4000 /* Transmit FIFO is half empty */
 759 #define UTX_FIFO_EMPTY   0x8000 /* Transmit FIFO is empty */
 760
 761 /* '328-compatible definitions */
 762 #define UTX_CTS_STATUS  UTX_CTS_STAT
 763 #define UTX_IGNORE_CTS  UTX_NOCTS
 764
 765 /*
 766  * UART Miscellaneous Register
 767  */
 768 #define UMISC_ADDR      0xfffff908
 769 #define UMISC           WORD_REF(UMISC_ADDR)
 770
 771 #define UMISC_TX_POL     0x0004 /* Transmit Polarity */
 772 #define UMISC_RX_POL     0x0008 /* Receive Polarity */
 773 #define UMISC_IRDA_LOOP  0x0010 /* IrDA Loopback Enable */
 774 #define UMISC_IRDA_EN    0x0020 /* Infra-Red Enable */
 775 #define UMISC_RTS        0x0040 /* Set RTS status */
 776 #define UMISC_RTSCONT    0x0080 /* Choose RTS control */
 777 #define UMISC_IR_TEST    0x0400 /* IRDA Test Enable */
 778 #define UMISC_BAUD_RESET 0x0800 /* Reset Baud Rate Generation Counters */
 779 #define UMISC_LOOP       0x1000 /* Serial Loopback Enable */
 780 #define UMISC_FORCE_PERR 0x2000 /* Force Parity Error */
 781 #define UMISC_CLKSRC     0x4000 /* Clock Source */
 782 #define UMISC_BAUD_TEST  0x8000 /* Enable Baud Test Mode */
 783
 784 /*
 785  * UART Non-integer Prescaler Register
 786  */
 787 #define NIPR_ADDR       0xfffff90a
 788 #define NIPR            WORD_REF(NIPR_ADDR)
 789
 790 #define NIPR_STEP_VALUE_MASK    0x00ff  /* NI prescaler step value */
 791 #define NIPR_STEP_VALUE_SHIFT   0
 792 #define NIPR_SELECT_MASK        0x0700  /* Tap Selection */
 793 #define NIPR_SELECT_SHIFT       8
 794 #define NIPR_PRE_SEL            0x8000  /* Non-integer prescaler select */
 795
 796
 797 /* generalization of uart control registers to support multiple ports: */
 798 typedef volatile struct {
 799   volatile unsigned short int ustcnt;
 800   volatile unsigned short int ubaud;
 801   union {
 802     volatile unsigned short int w;
 803     struct {
 804       volatile unsigned char status;
 805       volatile unsigned char rxdata;
 806     } b;
 807   } urx;
 808   union {
 809     volatile unsigned short int w;
 810     struct {
 811       volatile unsigned char status;
 812       volatile unsigned char txdata;
 813     } b;
 814   } utx;
 815   volatile unsigned short int umisc;
 816   volatile unsigned short int nipr;
 817   volatile unsigned short int pad1;
 818   volatile unsigned short int pad2;
 819 } __packed m68328_uart;
 820
 821
 822 /**********
 823  *
 824  * 0xFFFFFAxx -- LCD Controller
 825  *
 826  **********/
 827
 828 /*
 829  * LCD Screen Starting Address Register
 830  */
 831 #define LSSA_ADDR       0xfffffa00
 832 #define LSSA            LONG_REF(LSSA_ADDR)
 833
 834 #define LSSA_SSA_MASK   0x1ffffffe      /* Bits 0 and 29-31 are reserved */
 835
 836 /*
 837  * LCD Virtual Page Width Register
 838  */
 839 #define LVPW_ADDR       0xfffffa05
 840 #define LVPW            BYTE_REF(LVPW_ADDR)
 841
 842 /*
 843  * LCD Screen Width Register (not compatible with '328 !!!)
 844  */
 845 #define LXMAX_ADDR      0xfffffa08
 846 #define LXMAX           WORD_REF(LXMAX_ADDR)
 847
 848 #define LXMAX_XM_MASK   0x02f0          /* Bits 0-3 and 10-15 are reserved */
 849
 850 /*
 851  * LCD Screen Height Register
 852  */
 853 #define LYMAX_ADDR      0xfffffa0a
 854 #define LYMAX           WORD_REF(LYMAX_ADDR)
 855
 856 #define LYMAX_YM_MASK   0x01ff          /* Bits 9-15 are reserved */
 857
 858 /*
 859  * LCD Cursor X Position Register
 860  */
 861 #define LCXP_ADDR       0xfffffa18
 862 #define LCXP            WORD_REF(LCXP_ADDR)
 863
 864 #define LCXP_CC_MASK    0xc000          /* Cursor Control */
 865 #define   LCXP_CC_TRAMSPARENT   0x0000
 866 #define   LCXP_CC_BLACK         0x4000
 867 #define   LCXP_CC_REVERSED      0x8000
 868 #define   LCXP_CC_WHITE         0xc000
 869 #define LCXP_CXP_MASK   0x02ff          /* Cursor X position */
 870
 871 /*
 872  * LCD Cursor Y Position Register
 873  */
 874 #define LCYP_ADDR       0xfffffa1a
 875 #define LCYP            WORD_REF(LCYP_ADDR)
 876
 877 #define LCYP_CYP_MASK   0x01ff          /* Cursor Y Position */
 878
 879 /*
 880  * LCD Cursor Width and Heigth Register
 881  */
 882 #define LCWCH_ADDR      0xfffffa1c
 883 #define LCWCH           WORD_REF(LCWCH_ADDR)
 884
 885 #define LCWCH_CH_MASK   0x001f          /* Cursor Height */
 886 #define LCWCH_CH_SHIFT  0
 887 #define LCWCH_CW_MASK   0x1f00          /* Cursor Width */
 888 #define LCWCH_CW_SHIFT  8
 889
 890 /*
 891  * LCD Blink Control Register
 892  */
 893 #define LBLKC_ADDR      0xfffffa1f
 894 #define LBLKC           BYTE_REF(LBLKC_ADDR)
 895
 896 #define LBLKC_BD_MASK   0x7f    /* Blink Divisor */
 897 #define LBLKC_BD_SHIFT  0
 898 #define LBLKC_BKEN      0x80    /* Blink Enabled */
 899
 900 /*
 901  * LCD Panel Interface Configuration Register
 902  */
 903 #define LPICF_ADDR      0xfffffa20
 904 #define LPICF           BYTE_REF(LPICF_ADDR)
 905
 906 #define LPICF_GS_MASK    0x03    /* Gray-Scale Mode */
 907 #define   LPICF_GS_BW      0x00
 908 #define   LPICF_GS_GRAY_4  0x01
 909 #define   LPICF_GS_GRAY_16 0x02
 910 #define LPICF_PBSIZ_MASK 0x0c   /* Panel Bus Width */
 911 #define   LPICF_PBSIZ_1    0x00
 912 #define   LPICF_PBSIZ_2    0x04
 913 #define   LPICF_PBSIZ_4    0x08
 914
 915 /*
 916  * LCD Polarity Configuration Register
 917  */
 918 #define LPOLCF_ADDR     0xfffffa21
 919 #define LPOLCF          BYTE_REF(LPOLCF_ADDR)
 920
 921 #define LPOLCF_PIXPOL   0x01    /* Pixel Polarity */
 922 #define LPOLCF_LPPOL    0x02    /* Line Pulse Polarity */
 923 #define LPOLCF_FLMPOL   0x04    /* Frame Marker Polarity */
 924 #define LPOLCF_LCKPOL   0x08    /* LCD Shift Lock Polarity */
 925
 926 /*
 927  * LACD (LCD Alternate Crystal Direction) Rate Control Register
 928  */
 929 #define LACDRC_ADDR     0xfffffa23
 930 #define LACDRC          BYTE_REF(LACDRC_ADDR)
 931
 932 #define LACDRC_ACDSLT    0x80   /* Signal Source Select */
 933 #define LACDRC_ACD_MASK  0x0f   /* Alternate Crystal Direction Control */
 934 #define LACDRC_ACD_SHIFT 0
 935
 936 /*
 937  * LCD Pixel Clock Divider Register
 938  */
 939 #define LPXCD_ADDR      0xfffffa25
 940 #define LPXCD           BYTE_REF(LPXCD_ADDR)
 941
 942 #define LPXCD_PCD_MASK  0x3f    /* Pixel Clock Divider */
 943 #define LPXCD_PCD_SHIFT 0
 944
 945 /*
 946  * LCD Clocking Control Register
 947  */
 948 #define LCKCON_ADDR     0xfffffa27
 949 #define LCKCON          BYTE_REF(LCKCON_ADDR)
 950
 951 #define LCKCON_DWS_MASK  0x0f   /* Display Wait-State */
 952 #define LCKCON_DWS_SHIFT 0
 953 #define LCKCON_DWIDTH    0x40   /* Display Memory Width  */
 954 #define LCKCON_LCDON     0x80   /* Enable LCD Controller */
 955
 956 /* '328-compatible definitions */
 957 #define LCKCON_DW_MASK  LCKCON_DWS_MASK
 958 #define LCKCON_DW_SHIFT LCKCON_DWS_SHIFT
 959
 960 /*
 961  * LCD Refresh Rate Adjustment Register
 962  */
 963 #define LRRA_ADDR       0xfffffa29
 964 #define LRRA            BYTE_REF(LRRA_ADDR)
 965
 966 /*
 967  * LCD Panning Offset Register
 968  */
 969 #define LPOSR_ADDR      0xfffffa2d
 970 #define LPOSR           BYTE_REF(LPOSR_ADDR)
 971
 972 #define LPOSR_POS_MASK  0x0f    /* Pixel Offset Code */
 973 #define LPOSR_POS_SHIFT 0
 974
 975 /*
 976  * LCD Frame Rate Control Modulation Register
 977  */
 978 #define LFRCM_ADDR      0xfffffa31
 979 #define LFRCM           BYTE_REF(LFRCM_ADDR)
 980
 981 #define LFRCM_YMOD_MASK  0x0f   /* Vertical Modulation */
 982 #define LFRCM_YMOD_SHIFT 0
 983 #define LFRCM_XMOD_MASK  0xf0   /* Horizontal Modulation */
 984 #define LFRCM_XMOD_SHIFT 4
 985
 986 /*
 987  * LCD Gray Palette Mapping Register
 988  */
 989 #define LGPMR_ADDR      0xfffffa33
 990 #define LGPMR           BYTE_REF(LGPMR_ADDR)
 991
 992 #define LGPMR_G1_MASK   0x0f
 993 #define LGPMR_G1_SHIFT  0
 994 #define LGPMR_G2_MASK   0xf0
 995 #define LGPMR_G2_SHIFT  4
 996
 997 /*
 998  * PWM Contrast Control Register
 999  */
1000 #define PWMR_ADDR       0xfffffa36
1001 #define PWMR            WORD_REF(PWMR_ADDR)
1002
1003 #define PWMR_PW_MASK    0x00ff  /* Pulse Width */
1004 #define PWMR_PW_SHIFT   0
1005 #define PWMR_CCPEN      0x0100  /* Contrast Control Enable */
1006 #define PWMR_SRC_MASK   0x0600  /* Input Clock Source */
1007 #define   PWMR_SRC_LINE   0x0000        /* Line Pulse  */
1008 #define   PWMR_SRC_PIXEL  0x0200        /* Pixel Clock */
1009 #define   PWMR_SRC_LCD    0x4000        /* LCD clock   */
1010
1011 /**********
1012  *
1013  * 0xFFFFFBxx -- Real-Time Clock (RTC)
1014  *
1015  **********/
1016
1017 /*
1018  * RTC Hours Minutes and Seconds Register
1019  */
1020 #define RTCTIME_ADDR    0xfffffb00
1021 #define RTCTIME         LONG_REF(RTCTIME_ADDR)
1022
1023 #define RTCTIME_SECONDS_MASK    0x0000003f      /* Seconds */
1024 #define RTCTIME_SECONDS_SHIFT   0
1025 #define RTCTIME_MINUTES_MASK    0x003f0000      /* Minutes */
1026 #define RTCTIME_MINUTES_SHIFT   16
1027 #define RTCTIME_HOURS_MASK      0x1f000000      /* Hours */
1028 #define RTCTIME_HOURS_SHIFT     24
1029
1030 /*
1031  *  RTC Alarm Register
1032  */
1033 #define RTCALRM_ADDR    0xfffffb04
1034 #define RTCALRM         LONG_REF(RTCALRM_ADDR)
1035
1036 #define RTCALRM_SECONDS_MASK    0x0000003f      /* Seconds */
1037 #define RTCALRM_SECONDS_SHIFT   0
1038 #define RTCALRM_MINUTES_MASK    0x003f0000      /* Minutes */
1039 #define RTCALRM_MINUTES_SHIFT   16
1040 #define RTCALRM_HOURS_MASK      0x1f000000      /* Hours */
1041 #define RTCALRM_HOURS_SHIFT     24
1042
1043 /*
1044  * Watchdog Timer Register
1045  */
1046 #define WATCHDOG_ADDR   0xfffffb0a
1047 #define WATCHDOG        WORD_REF(WATCHDOG_ADDR)
1048
1049 #define WATCHDOG_EN     0x0001  /* Watchdog Enabled */
1050 #define WATCHDOG_ISEL   0x0002  /* Select the watchdog interrupt */
1051 #define WATCHDOG_INTF   0x0080  /* Watchdog interrupt occurred */
1052 #define WATCHDOG_CNT_MASK  0x0300       /* Watchdog Counter */
1053 #define WATCHDOG_CNT_SHIFT 8
1054
1055 /*
1056  * RTC Control Register
1057  */
1058 #define RTCCTL_ADDR     0xfffffb0c
1059 #define RTCCTL          WORD_REF(RTCCTL_ADDR)
1060
1061 #define RTCCTL_XTL      0x0020  /* Crystal Selection */
1062 #define RTCCTL_EN       0x0080  /* RTC Enable */
1063
1064 /* '328-compatible definitions */
1065 #define RTCCTL_384      RTCCTL_XTL
1066 #define RTCCTL_ENABLE   RTCCTL_EN
1067
1068 /*
1069  * RTC Interrupt Status Register
1070  */
1071 #define RTCISR_ADDR     0xfffffb0e
1072 #define RTCISR          WORD_REF(RTCISR_ADDR)
1073
1074 #define RTCISR_SW       0x0001  /* Stopwatch timed out */
1075 #define RTCISR_MIN      0x0002  /* 1-minute interrupt has occurred */
1076 #define RTCISR_ALM      0x0004  /* Alarm interrupt has occurred */
1077 #define RTCISR_DAY      0x0008  /* 24-hour rollover interrupt has occurred */
1078 #define RTCISR_1HZ      0x0010  /* 1Hz interrupt has occurred */
1079 #define RTCISR_HR       0x0020  /* 1-hour interrupt has occurred */
1080 #define RTCISR_SAM0     0x0100  /*   4Hz /   4.6875Hz interrupt has occurred */
1081 #define RTCISR_SAM1     0x0200  /*   8Hz /   9.3750Hz interrupt has occurred */
1082 #define RTCISR_SAM2     0x0400  /*  16Hz /  18.7500Hz interrupt has occurred */
1083 #define RTCISR_SAM3     0x0800  /*  32Hz /  37.5000Hz interrupt has occurred */
1084 #define RTCISR_SAM4     0x1000  /*  64Hz /  75.0000Hz interrupt has occurred */
1085 #define RTCISR_SAM5     0x2000  /* 128Hz / 150.0000Hz interrupt has occurred */
1086 #define RTCISR_SAM6     0x4000  /* 256Hz / 300.0000Hz interrupt has occurred */
1087 #define RTCISR_SAM7     0x8000  /* 512Hz / 600.0000Hz interrupt has occurred */
1088
1089 /*
1090  * RTC Interrupt Enable Register
1091  */
1092 #define RTCIENR_ADDR    0xfffffb10
1093 #define RTCIENR         WORD_REF(RTCIENR_ADDR)
1094
1095 #define RTCIENR_SW      0x0001  /* Stopwatch interrupt enable */
1096 #define RTCIENR_MIN     0x0002  /* 1-minute interrupt enable */
1097 #define RTCIENR_ALM     0x0004  /* Alarm interrupt enable */
1098 #define RTCIENR_DAY     0x0008  /* 24-hour rollover interrupt enable */
1099 #define RTCIENR_1HZ     0x0010  /* 1Hz interrupt enable */
1100 #define RTCIENR_HR      0x0020  /* 1-hour interrupt enable */
1101 #define RTCIENR_SAM0    0x0100  /*   4Hz /   4.6875Hz interrupt enable */
1102 #define RTCIENR_SAM1    0x0200  /*   8Hz /   9.3750Hz interrupt enable */
1103 #define RTCIENR_SAM2    0x0400  /*  16Hz /  18.7500Hz interrupt enable */
1104 #define RTCIENR_SAM3    0x0800  /*  32Hz /  37.5000Hz interrupt enable */
1105 #define RTCIENR_SAM4    0x1000  /*  64Hz /  75.0000Hz interrupt enable */
1106 #define RTCIENR_SAM5    0x2000  /* 128Hz / 150.0000Hz interrupt enable */
1107 #define RTCIENR_SAM6    0x4000  /* 256Hz / 300.0000Hz interrupt enable */
1108 #define RTCIENR_SAM7    0x8000  /* 512Hz / 600.0000Hz interrupt enable */
1109
1110 /*
1111  * Stopwatch Minutes Register
1112  */
1113 #define STPWCH_ADDR     0xfffffb12
1114 #define STPWCH          WORD_REF(STPWCH)
1115
1116 #define STPWCH_CNT_MASK  0x003f /* Stopwatch countdown value */
1117 #define SPTWCH_CNT_SHIFT 0
1118
1119 /*
1120  * RTC Day Count Register
1121  */
1122 #define DAYR_ADDR       0xfffffb1a
1123 #define DAYR            WORD_REF(DAYR_ADDR)
1124
1125 #define DAYR_DAYS_MASK  0x1ff   /* Day Setting */
1126 #define DAYR_DAYS_SHIFT 0
1127
1128 /*
1129  * RTC Day Alarm Register
1130  */
1131 #define DAYALARM_ADDR   0xfffffb1c
1132 #define DAYALARM        WORD_REF(DAYALARM_ADDR)
1133
1134 #define DAYALARM_DAYSAL_MASK    0x01ff  /* Day Setting of the Alarm */
1135 #define DAYALARM_DAYSAL_SHIFT   0
1136
1137 /**********
1138  *
1139  * 0xFFFFFCxx -- DRAM Controller
1140  *
1141  **********/
1142
1143 /*
1144  * DRAM Memory Configuration Register
1145  */
1146 #define DRAMMC_ADDR     0xfffffc00
1147 #define DRAMMC          WORD_REF(DRAMMC_ADDR)
1148
1149 #define DRAMMC_ROW12_MASK       0xc000  /* Row address bit for MD12 */
1150 #define   DRAMMC_ROW12_PA10     0x0000
1151 #define   DRAMMC_ROW12_PA21     0x4000
1152 #define   DRAMMC_ROW12_PA23     0x8000
1153 #define DRAMMC_ROW0_MASK        0x3000  /* Row address bit for MD0 */
1154 #define   DRAMMC_ROW0_PA11      0x0000
1155 #define   DRAMMC_ROW0_PA22      0x1000
1156 #define   DRAMMC_ROW0_PA23      0x2000
1157 #define DRAMMC_ROW11            0x0800  /* Row address bit for MD11 PA20/PA22 */
1158 #define DRAMMC_ROW10            0x0400  /* Row address bit for MD10 PA19/PA21 */
1159 #define DRAMMC_ROW9             0x0200  /* Row address bit for MD9  PA9/PA19  */
1160 #define DRAMMC_ROW8             0x0100  /* Row address bit for MD8  PA10/PA20 */
1161 #define DRAMMC_COL10            0x0080  /* Col address bit for MD10 PA11/PA0  */
1162 #define DRAMMC_COL9             0x0040  /* Col address bit for MD9  PA10/PA0  */
1163 #define DRAMMC_COL8             0x0020  /* Col address bit for MD8  PA9/PA0   */
1164 #define DRAMMC_REF_MASK         0x001f  /* Refresh Cycle */
1165 #define DRAMMC_REF_SHIFT        0
1166
1167 /*
1168  * DRAM Control Register
1169  */
1170 #define DRAMC_ADDR      0xfffffc02
1171 #define DRAMC           WORD_REF(DRAMC_ADDR)
1172
1173 #define DRAMC_DWE          0x0001       /* DRAM Write Enable */
1174 #define DRAMC_RST          0x0002       /* Reset Burst Refresh Enable */
1175 #define DRAMC_LPR          0x0004       /* Low-Power Refresh Enable */
1176 #define DRAMC_SLW          0x0008       /* Slow RAM */
1177 #define DRAMC_LSP          0x0010       /* Light Sleep */
1178 #define DRAMC_MSW          0x0020       /* Slow Multiplexing */
1179 #define DRAMC_WS_MASK      0x00c0       /* Wait-states */
1180 #define DRAMC_WS_SHIFT     6
1181 #define DRAMC_PGSZ_MASK    0x0300       /* Page Size for fast page mode */
1182 #define DRAMC_PGSZ_SHIFT   8
1183 #define   DRAMC_PGSZ_256K  0x0000
1184 #define   DRAMC_PGSZ_512K  0x0100
1185 #define   DRAMC_PGSZ_1024K 0x0200
1186 #define   DRAMC_PGSZ_2048K 0x0300
1187 #define DRAMC_EDO          0x0400       /* EDO DRAM */
1188 #define DRAMC_CLK          0x0800       /* Refresh Timer Clock source select */
1189 #define DRAMC_BC_MASK      0x3000       /* Page Access Clock Cycle (FP mode) */
1190 #define DRAMC_BC_SHIFT     12
1191 #define DRAMC_RM           0x4000       /* Refresh Mode */
1192 #define DRAMC_EN           0x8000       /* DRAM Controller enable */
1193
1194
1195 /**********
1196  *
1197  * 0xFFFFFDxx -- In-Circuit Emulation (ICE)
1198  *
1199  **********/
1200
1201 /*
1202  * ICE Module Address Compare Register
1203  */
1204 #define ICEMACR_ADDR    0xfffffd00
1205 #define ICEMACR         LONG_REF(ICEMACR_ADDR)
1206
1207 /*
1208  * ICE Module Address Mask Register
1209  */
1210 #define ICEMAMR_ADDR    0xfffffd04
1211 #define ICEMAMR         LONG_REF(ICEMAMR_ADDR)
1212
1213 /*
1214  * ICE Module Control Compare Register
1215  */
1216 #define ICEMCCR_ADDR    0xfffffd08
1217 #define ICEMCCR         WORD_REF(ICEMCCR_ADDR)
1218
1219 #define ICEMCCR_PD      0x0001  /* Program/Data Cycle Selection */
1220 #define ICEMCCR_RW      0x0002  /* Read/Write Cycle Selection */
1221
1222 /*
1223  * ICE Module Control Mask Register
1224  */
1225 #define ICEMCMR_ADDR    0xfffffd0a
1226 #define ICEMCMR         WORD_REF(ICEMCMR_ADDR)
1227
1228 #define ICEMCMR_PDM     0x0001  /* Program/Data Cycle Mask */
1229 #define ICEMCMR_RWM     0x0002  /* Read/Write Cycle Mask */
1230
1231 /*
1232  * ICE Module Control Register
1233  */
1234 #define ICEMCR_ADDR     0xfffffd0c
1235 #define ICEMCR          WORD_REF(ICEMCR_ADDR)
1236
1237 #define ICEMCR_CEN      0x0001  /* Compare Enable */
1238 #define ICEMCR_PBEN     0x0002  /* Program Break Enable */
1239 #define ICEMCR_SB       0x0004  /* Single Breakpoint */
1240 #define ICEMCR_HMDIS    0x0008  /* HardMap disable */
1241 #define ICEMCR_BBIEN    0x0010  /* Bus Break Interrupt Enable */
1242
1243 /*
1244  * ICE Module Status Register
1245  */
1246 #define ICEMSR_ADDR     0xfffffd0e
1247 #define ICEMSR          WORD_REF(ICEMSR_ADDR)
1248
1249 #define ICEMSR_EMUEN    0x0001  /* Emulation Enable */
1250 #define ICEMSR_BRKIRQ   0x0002  /* A-Line Vector Fetch Detected */
1251 #define ICEMSR_BBIRQ    0x0004  /* Bus Break Interrupt Detected */
1252 #define ICEMSR_EMIRQ    0x0008  /* EMUIRQ Falling Edge Detected */
1253
1254 #endif /* _MC68EZ328_H_ */