x86/mm/pat: Don't report PAT on CPUs that don't support it
[linux/fpc-iii.git] / arch / mips / math-emu / sp_add.c
blobc55c0c00bca803b989825397aedb915f28359402
1 /* IEEE754 floating point arithmetic
2 * single precision
3 */
4 /*
5 * MIPS floating point support
6 * Copyright (C) 1994-2000 Algorithmics Ltd.
8 * This program is free software; you can distribute it and/or modify it
9 * under the terms of the GNU General Public License (Version 2) as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
22 #include "ieee754sp.h"
24 union ieee754sp ieee754sp_add(union ieee754sp x, union ieee754sp y)
26 int s;
28 COMPXSP;
29 COMPYSP;
31 EXPLODEXSP;
32 EXPLODEYSP;
34 ieee754_clearcx();
36 FLUSHXSP;
37 FLUSHYSP;
39 switch (CLPAIR(xc, yc)) {
40 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_SNAN):
41 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_SNAN):
42 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_SNAN):
43 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_SNAN):
44 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_SNAN):
45 return ieee754sp_nanxcpt(y);
47 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN):
48 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN):
49 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_ZERO):
50 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_NORM):
51 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_DNORM):
52 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF):
53 return ieee754sp_nanxcpt(x);
55 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN):
56 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN):
57 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_QNAN):
58 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_QNAN):
59 return y;
61 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN):
62 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_ZERO):
63 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_NORM):
64 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_DNORM):
65 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_INF):
66 return x;
70 * Infinity handling
72 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_INF):
73 if (xs == ys)
74 return x;
75 ieee754_setcx(IEEE754_INVALID_OPERATION);
76 return ieee754sp_indef();
78 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_INF):
79 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_INF):
80 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_INF):
81 return y;
83 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_ZERO):
84 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_NORM):
85 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_DNORM):
86 return x;
89 * Zero handling
91 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_ZERO):
92 if (xs == ys)
93 return x;
94 else
95 return ieee754sp_zero(ieee754_csr.rm == FPU_CSR_RD);
97 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_ZERO):
98 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_ZERO):
99 return x;
101 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_NORM):
102 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_DNORM):
103 return y;
105 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_DNORM):
106 SPDNORMX;
108 /* FALL THROUGH */
110 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_DNORM):
111 SPDNORMY;
112 break;
114 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_NORM):
115 SPDNORMX;
116 break;
118 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_NORM):
119 break;
121 assert(xm & SP_HIDDEN_BIT);
122 assert(ym & SP_HIDDEN_BIT);
125 * Provide guard, round and stick bit space.
127 xm <<= 3;
128 ym <<= 3;
130 if (xe > ye) {
132 * Have to shift y fraction right to align.
134 s = xe - ye;
135 ym = XSPSRS(ym, s);
136 ye += s;
137 } else if (ye > xe) {
139 * Have to shift x fraction right to align.
141 s = ye - xe;
142 xm = XSPSRS(xm, s);
143 xe += s;
145 assert(xe == ye);
146 assert(xe <= SP_EMAX);
148 if (xs == ys) {
150 * Generate 28 bit result of adding two 27 bit numbers
151 * leaving result in xm, xs and xe.
153 xm = xm + ym;
155 if (xm >> (SP_FBITS + 1 + 3)) { /* carry out */
156 SPXSRSX1();
158 } else {
159 if (xm >= ym) {
160 xm = xm - ym;
161 } else {
162 xm = ym - xm;
163 xs = ys;
165 if (xm == 0)
166 return ieee754sp_zero(ieee754_csr.rm == FPU_CSR_RD);
169 * Normalize in extended single precision
171 while ((xm >> (SP_FBITS + 3)) == 0) {
172 xm <<= 1;
173 xe--;
177 return ieee754sp_format(xs, xe, xm);