4 #include <linux/compiler.h>
5 #include <linux/types.h>
6 #include <linux/errno.h>
8 #include <soc/fsl/qe/qe.h>
11 * SPI Parameter RAM common to QE and CPM.
14 __be16 rbase
; /* Rx Buffer descriptor base address */
15 __be16 tbase
; /* Tx Buffer descriptor base address */
16 u8 rfcr
; /* Rx function code */
17 u8 tfcr
; /* Tx function code */
18 __be16 mrblr
; /* Max receive buffer length */
19 __be32 rstate
; /* Internal */
20 __be32 rdp
; /* Internal */
21 __be16 rbptr
; /* Internal */
22 __be16 rbc
; /* Internal */
23 __be32 rxtmp
; /* Internal */
24 __be32 tstate
; /* Internal */
25 __be32 tdp
; /* Internal */
26 __be16 tbptr
; /* Internal */
27 __be16 tbc
; /* Internal */
28 __be32 txtmp
; /* Internal */
29 __be32 res
; /* Tx temp. */
30 __be16 rpbase
; /* Relocation pointer (CPM1 only) */
31 __be16 res1
; /* Reserved */
35 * USB Controller pram common to QE and CPM.
49 /* Fields down below are QE-only */
54 } __attribute__ ((packed
));
57 * Function code bits, usually generic to devices.
60 #define CPMFCR_GBL ((u_char)0x00) /* Flag doesn't exist in CPM1 */
61 #define CPMFCR_TC2 ((u_char)0x00) /* Flag doesn't exist in CPM1 */
62 #define CPMFCR_DTB ((u_char)0x00) /* Flag doesn't exist in CPM1 */
63 #define CPMFCR_BDB ((u_char)0x00) /* Flag doesn't exist in CPM1 */
65 #define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */
66 #define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */
67 #define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */
68 #define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */
70 #define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */
72 /* Opcodes common to CPM1 and CPM2
74 #define CPM_CR_INIT_TRX ((ushort)0x0000)
75 #define CPM_CR_INIT_RX ((ushort)0x0001)
76 #define CPM_CR_INIT_TX ((ushort)0x0002)
77 #define CPM_CR_HUNT_MODE ((ushort)0x0003)
78 #define CPM_CR_STOP_TX ((ushort)0x0004)
79 #define CPM_CR_GRA_STOP_TX ((ushort)0x0005)
80 #define CPM_CR_RESTART_TX ((ushort)0x0006)
81 #define CPM_CR_CLOSE_RX_BD ((ushort)0x0007)
82 #define CPM_CR_SET_GADDR ((ushort)0x0008)
83 #define CPM_CR_SET_TIMER ((ushort)0x0008)
84 #define CPM_CR_STOP_IDMA ((ushort)0x000b)
86 /* Buffer descriptors used by many of the CPM protocols. */
87 typedef struct cpm_buf_desc
{
88 ushort cbd_sc
; /* Status and Control */
89 ushort cbd_datlen
; /* Data length in buffer */
90 uint cbd_bufaddr
; /* Buffer address in host memory */
93 /* Buffer descriptor control/status used by serial
96 #define BD_SC_EMPTY (0x8000) /* Receive is empty */
97 #define BD_SC_READY (0x8000) /* Transmit is ready */
98 #define BD_SC_WRAP (0x2000) /* Last buffer descriptor */
99 #define BD_SC_INTRPT (0x1000) /* Interrupt on change */
100 #define BD_SC_LAST (0x0800) /* Last buffer in frame */
101 #define BD_SC_TC (0x0400) /* Transmit CRC */
102 #define BD_SC_CM (0x0200) /* Continuous mode */
103 #define BD_SC_ID (0x0100) /* Rec'd too many idles */
104 #define BD_SC_P (0x0100) /* xmt preamble */
105 #define BD_SC_BR (0x0020) /* Break received */
106 #define BD_SC_FR (0x0010) /* Framing error */
107 #define BD_SC_PR (0x0008) /* Parity error */
108 #define BD_SC_NAK (0x0004) /* NAK - did not respond */
109 #define BD_SC_OV (0x0002) /* Overrun */
110 #define BD_SC_UN (0x0002) /* Underrun */
111 #define BD_SC_CD (0x0001) /* */
112 #define BD_SC_CL (0x0001) /* Collision */
114 /* Buffer descriptor control/status used by Ethernet receive.
115 * Common to SCC and FCC.
117 #define BD_ENET_RX_EMPTY (0x8000)
118 #define BD_ENET_RX_WRAP (0x2000)
119 #define BD_ENET_RX_INTR (0x1000)
120 #define BD_ENET_RX_LAST (0x0800)
121 #define BD_ENET_RX_FIRST (0x0400)
122 #define BD_ENET_RX_MISS (0x0100)
123 #define BD_ENET_RX_BC (0x0080) /* FCC Only */
124 #define BD_ENET_RX_MC (0x0040) /* FCC Only */
125 #define BD_ENET_RX_LG (0x0020)
126 #define BD_ENET_RX_NO (0x0010)
127 #define BD_ENET_RX_SH (0x0008)
128 #define BD_ENET_RX_CR (0x0004)
129 #define BD_ENET_RX_OV (0x0002)
130 #define BD_ENET_RX_CL (0x0001)
131 #define BD_ENET_RX_STATS (0x01ff) /* All status bits */
133 /* Buffer descriptor control/status used by Ethernet transmit.
134 * Common to SCC and FCC.
136 #define BD_ENET_TX_READY (0x8000)
137 #define BD_ENET_TX_PAD (0x4000)
138 #define BD_ENET_TX_WRAP (0x2000)
139 #define BD_ENET_TX_INTR (0x1000)
140 #define BD_ENET_TX_LAST (0x0800)
141 #define BD_ENET_TX_TC (0x0400)
142 #define BD_ENET_TX_DEF (0x0200)
143 #define BD_ENET_TX_HB (0x0100)
144 #define BD_ENET_TX_LC (0x0080)
145 #define BD_ENET_TX_RL (0x0040)
146 #define BD_ENET_TX_RCMASK (0x003c)
147 #define BD_ENET_TX_UN (0x0002)
148 #define BD_ENET_TX_CSL (0x0001)
149 #define BD_ENET_TX_STATS (0x03ff) /* All status bits */
151 /* Buffer descriptor control/status used by Transparent mode SCC.
153 #define BD_SCC_TX_LAST (0x0800)
155 /* Buffer descriptor control/status used by I2C.
157 #define BD_I2C_START (0x0400)
160 int cpm_command(u32 command
, u8 opcode
);
162 static inline int cpm_command(u32 command
, u8 opcode
)
166 #endif /* CONFIG_CPM */
168 int cpm2_gpiochip_add32(struct device_node
*np
);