arch/powerpc/include/asm/cpuidle.h

   1 #ifndef _ASM_POWERPC_CPUIDLE_H
   2 #define _ASM_POWERPC_CPUIDLE_H
   3
   4 #ifdef CONFIG_PPC_POWERNV
   5 /* Used in powernv idle state management */
   6 #define PNV_THREAD_RUNNING              0
   7 #define PNV_THREAD_NAP                  1
   8 #define PNV_THREAD_SLEEP                2
   9 #define PNV_THREAD_WINKLE               3
  10 #define PNV_CORE_IDLE_LOCK_BIT          0x100
  11 #define PNV_CORE_IDLE_THREAD_BITS       0x0FF
  12
  13 /*
  14  * ============================ NOTE =================================
  15  * The older firmware populates only the RL field in the psscr_val and
  16  * sets the psscr_mask to 0xf. On such a firmware, the kernel sets the
  17  * remaining PSSCR fields to default values as follows:
  18  *
  19  * - ESL and EC bits are to 1. So wakeup from any stop state will be
  20  *   at vector 0x100.
  21  *
  22  * - MTL and PSLL are set to the maximum allowed value as per the ISA,
  23  *    i.e. 15.
  24  *
  25  * - The Transition Rate, TR is set to the Maximum value 3.
  26  */
  27 #define PSSCR_HV_DEFAULT_VAL    (PSSCR_ESL | PSSCR_EC |             \
  28                                 PSSCR_PSLL_MASK | PSSCR_TR_MASK |   \
  29                                 PSSCR_MTL_MASK)
  30
  31 #define PSSCR_HV_DEFAULT_MASK   (PSSCR_ESL | PSSCR_EC |             \
  32                                 PSSCR_PSLL_MASK | PSSCR_TR_MASK |   \
  33                                 PSSCR_MTL_MASK | PSSCR_RL_MASK)
  34 #define PSSCR_EC_SHIFT    20
  35 #define PSSCR_ESL_SHIFT   21
  36 #define GET_PSSCR_EC(x)   (((x) & PSSCR_EC) >> PSSCR_EC_SHIFT)
  37 #define GET_PSSCR_ESL(x)  (((x) & PSSCR_ESL) >> PSSCR_ESL_SHIFT)
  38 #define GET_PSSCR_RL(x)   ((x) & PSSCR_RL_MASK)
  39
  40 #define ERR_EC_ESL_MISMATCH             -1
  41 #define ERR_DEEP_STATE_ESL_MISMATCH     -2
  42
  43 #ifndef __ASSEMBLY__
  44 extern u32 pnv_fastsleep_workaround_at_entry[];
  45 extern u32 pnv_fastsleep_workaround_at_exit[];
  46
  47 extern u64 pnv_first_deep_stop_state;
  48
  49 int validate_psscr_val_mask(u64 *psscr_val, u64 *psscr_mask, u32 flags);
  50 static inline void report_invalid_psscr_val(u64 psscr_val, int err)
  51 {
  52         switch (err) {
  53         case ERR_EC_ESL_MISMATCH:
  54                 pr_warn("Invalid psscr 0x%016llx : ESL,EC bits unequal",
  55                         psscr_val);
  56                 break;
  57         case ERR_DEEP_STATE_ESL_MISMATCH:
  58                 pr_warn("Invalid psscr 0x%016llx : ESL cleared for deep stop-state",
  59                         psscr_val);
  60         }
  61 }
  62 #endif
  63
  64 #endif
  65
  66 /* Idle state entry routines */
  67 #ifdef  CONFIG_PPC_P7_NAP
  68 #define IDLE_STATE_ENTER_SEQ(IDLE_INST)                         \
  69         /* Magic NAP/SLEEP/WINKLE mode enter sequence */        \
  70         std     r0,0(r1);                                       \
  71         ptesync;                                                \
  72         ld      r0,0(r1);                                       \
  73 236:    cmpd    cr0,r0,r0;                                      \
  74         bne     236b;                                           \
  75         IDLE_INST;                                              \
  76
  77 #define IDLE_STATE_ENTER_SEQ_NORET(IDLE_INST)                   \
  78         IDLE_STATE_ENTER_SEQ(IDLE_INST)                         \
  79         b       .
  80 #endif /* CONFIG_PPC_P7_NAP */
  81
  82 #endif