x86/mm/pat: Don't report PAT on CPUs that don't support it
[linux/fpc-iii.git] / arch / powerpc / include / asm / exception-64s.h
blobed3beadd2cc515d1b8a99b4836b3f06c1a97a87c
1 #ifndef _ASM_POWERPC_EXCEPTION_H
2 #define _ASM_POWERPC_EXCEPTION_H
3 /*
4 * Extracted from head_64.S
6 * PowerPC version
7 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
9 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
10 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
11 * Adapted for Power Macintosh by Paul Mackerras.
12 * Low-level exception handlers and MMU support
13 * rewritten by Paul Mackerras.
14 * Copyright (C) 1996 Paul Mackerras.
16 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
17 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
19 * This file contains the low-level support and setup for the
20 * PowerPC-64 platform, including trap and interrupt dispatch.
22 * This program is free software; you can redistribute it and/or
23 * modify it under the terms of the GNU General Public License
24 * as published by the Free Software Foundation; either version
25 * 2 of the License, or (at your option) any later version.
28 * The following macros define the code that appears as
29 * the prologue to each of the exception handlers. They
30 * are split into two parts to allow a single kernel binary
31 * to be used for pSeries and iSeries.
33 * We make as much of the exception code common between native
34 * exception handlers (including pSeries LPAR) and iSeries LPAR
35 * implementations as possible.
37 #include <asm/head-64.h>
39 #define EX_R9 0
40 #define EX_R10 8
41 #define EX_R11 16
42 #define EX_R12 24
43 #define EX_R13 32
44 #define EX_SRR0 40
45 #define EX_DAR 48
46 #define EX_DSISR 56
47 #define EX_CCR 60
48 #define EX_R3 64
49 #define EX_LR 72
50 #define EX_CFAR 80
51 #define EX_PPR 88 /* SMT thread status register (priority) */
52 #define EX_CTR 96
54 #ifdef CONFIG_RELOCATABLE
55 #define __EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \
56 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \
57 LOAD_HANDLER(r12,label); \
58 mtctr r12; \
59 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \
60 li r10,MSR_RI; \
61 mtmsrd r10,1; /* Set RI (EE=0) */ \
62 bctr;
63 #else
64 /* If not relocatable, we can jump directly -- and save messing with LR */
65 #define __EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \
66 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \
67 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \
68 li r10,MSR_RI; \
69 mtmsrd r10,1; /* Set RI (EE=0) */ \
70 b label;
71 #endif
72 #define EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \
73 __EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \
76 * As EXCEPTION_PROLOG_PSERIES(), except we've already got relocation on
77 * so no need to rfid. Save lr in case we're CONFIG_RELOCATABLE, in which
78 * case EXCEPTION_RELON_PROLOG_PSERIES_1 will be using lr.
80 #define EXCEPTION_RELON_PROLOG_PSERIES(area, label, h, extra, vec) \
81 EXCEPTION_PROLOG_0(area); \
82 EXCEPTION_PROLOG_1(area, extra, vec); \
83 EXCEPTION_RELON_PROLOG_PSERIES_1(label, h)
86 * We're short on space and time in the exception prolog, so we can't
87 * use the normal LOAD_REG_IMMEDIATE macro to load the address of label.
88 * Instead we get the base of the kernel from paca->kernelbase and or in the low
89 * part of label. This requires that the label be within 64KB of kernelbase, and
90 * that kernelbase be 64K aligned.
92 #define LOAD_HANDLER(reg, label) \
93 ld reg,PACAKBASE(r13); /* get high part of &label */ \
94 ori reg,reg,FIXED_SYMBOL_ABS_ADDR(label);
96 #define __LOAD_HANDLER(reg, label) \
97 ld reg,PACAKBASE(r13); \
98 ori reg,reg,(ABS_ADDR(label))@l;
101 * Branches from unrelocated code (e.g., interrupts) to labels outside
102 * head-y require >64K offsets.
104 #define __LOAD_FAR_HANDLER(reg, label) \
105 ld reg,PACAKBASE(r13); \
106 ori reg,reg,(ABS_ADDR(label))@l; \
107 addis reg,reg,(ABS_ADDR(label))@h;
109 /* Exception register prefixes */
110 #define EXC_HV H
111 #define EXC_STD
113 #if defined(CONFIG_RELOCATABLE)
115 * If we support interrupts with relocation on AND we're a relocatable kernel,
116 * we need to use CTR to get to the 2nd level handler. So, save/restore it
117 * when required.
119 #define SAVE_CTR(reg, area) mfctr reg ; std reg,area+EX_CTR(r13)
120 #define GET_CTR(reg, area) ld reg,area+EX_CTR(r13)
121 #define RESTORE_CTR(reg, area) ld reg,area+EX_CTR(r13) ; mtctr reg
122 #else
123 /* ...else CTR is unused and in register. */
124 #define SAVE_CTR(reg, area)
125 #define GET_CTR(reg, area) mfctr reg
126 #define RESTORE_CTR(reg, area)
127 #endif
130 * PPR save/restore macros used in exceptions_64s.S
131 * Used for P7 or later processors
133 #define SAVE_PPR(area, ra, rb) \
134 BEGIN_FTR_SECTION_NESTED(940) \
135 ld ra,PACACURRENT(r13); \
136 ld rb,area+EX_PPR(r13); /* Read PPR from paca */ \
137 std rb,TASKTHREADPPR(ra); \
138 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,940)
140 #define RESTORE_PPR_PACA(area, ra) \
141 BEGIN_FTR_SECTION_NESTED(941) \
142 ld ra,area+EX_PPR(r13); \
143 mtspr SPRN_PPR,ra; \
144 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,941)
147 * Get an SPR into a register if the CPU has the given feature
149 #define OPT_GET_SPR(ra, spr, ftr) \
150 BEGIN_FTR_SECTION_NESTED(943) \
151 mfspr ra,spr; \
152 END_FTR_SECTION_NESTED(ftr,ftr,943)
155 * Set an SPR from a register if the CPU has the given feature
157 #define OPT_SET_SPR(ra, spr, ftr) \
158 BEGIN_FTR_SECTION_NESTED(943) \
159 mtspr spr,ra; \
160 END_FTR_SECTION_NESTED(ftr,ftr,943)
163 * Save a register to the PACA if the CPU has the given feature
165 #define OPT_SAVE_REG_TO_PACA(offset, ra, ftr) \
166 BEGIN_FTR_SECTION_NESTED(943) \
167 std ra,offset(r13); \
168 END_FTR_SECTION_NESTED(ftr,ftr,943)
170 #define EXCEPTION_PROLOG_0_PACA(area) \
171 std r9,area+EX_R9(r13); /* save r9 */ \
172 OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR); \
173 HMT_MEDIUM; \
174 std r10,area+EX_R10(r13); /* save r10 - r12 */ \
175 OPT_GET_SPR(r10, SPRN_CFAR, CPU_FTR_CFAR)
177 #define EXCEPTION_PROLOG_0(area) \
178 GET_PACA(r13); \
179 EXCEPTION_PROLOG_0_PACA(area)
181 #define __EXCEPTION_PROLOG_1(area, extra, vec) \
182 OPT_SAVE_REG_TO_PACA(area+EX_PPR, r9, CPU_FTR_HAS_PPR); \
183 OPT_SAVE_REG_TO_PACA(area+EX_CFAR, r10, CPU_FTR_CFAR); \
184 SAVE_CTR(r10, area); \
185 mfcr r9; \
186 extra(vec); \
187 std r11,area+EX_R11(r13); \
188 std r12,area+EX_R12(r13); \
189 GET_SCRATCH0(r10); \
190 std r10,area+EX_R13(r13)
191 #define EXCEPTION_PROLOG_1(area, extra, vec) \
192 __EXCEPTION_PROLOG_1(area, extra, vec)
194 #define __EXCEPTION_PROLOG_PSERIES_1(label, h) \
195 ld r10,PACAKMSR(r13); /* get MSR value for kernel */ \
196 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \
197 LOAD_HANDLER(r12,label) \
198 mtspr SPRN_##h##SRR0,r12; \
199 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \
200 mtspr SPRN_##h##SRR1,r10; \
201 h##rfid; \
202 b . /* prevent speculative execution */
203 #define EXCEPTION_PROLOG_PSERIES_1(label, h) \
204 __EXCEPTION_PROLOG_PSERIES_1(label, h)
206 #define EXCEPTION_PROLOG_PSERIES(area, label, h, extra, vec) \
207 EXCEPTION_PROLOG_0(area); \
208 EXCEPTION_PROLOG_1(area, extra, vec); \
209 EXCEPTION_PROLOG_PSERIES_1(label, h);
211 /* Have the PACA in r13 already */
212 #define EXCEPTION_PROLOG_PSERIES_PACA(area, label, h, extra, vec) \
213 EXCEPTION_PROLOG_0_PACA(area); \
214 EXCEPTION_PROLOG_1(area, extra, vec); \
215 EXCEPTION_PROLOG_PSERIES_1(label, h);
217 #define __KVMTEST(h, n) \
218 lbz r10,HSTATE_IN_GUEST(r13); \
219 cmpwi r10,0; \
220 bne do_kvm_##h##n
222 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
224 * If hv is possible, interrupts come into to the hv version
225 * of the kvmppc_interrupt code, which then jumps to the PR handler,
226 * kvmppc_interrupt_pr, if the guest is a PR guest.
228 #define kvmppc_interrupt kvmppc_interrupt_hv
229 #else
230 #define kvmppc_interrupt kvmppc_interrupt_pr
231 #endif
233 #ifdef CONFIG_RELOCATABLE
234 #define BRANCH_TO_COMMON(reg, label) \
235 __LOAD_HANDLER(reg, label); \
236 mtctr reg; \
237 bctr
239 #define BRANCH_LINK_TO_FAR(label) \
240 __LOAD_FAR_HANDLER(r12, label); \
241 mtctr r12; \
242 bctrl
245 * KVM requires __LOAD_FAR_HANDLER.
247 * __BRANCH_TO_KVM_EXIT branches are also a special case because they
248 * explicitly use r9 then reload it from PACA before branching. Hence
249 * the double-underscore.
251 #define __BRANCH_TO_KVM_EXIT(area, label) \
252 mfctr r9; \
253 std r9,HSTATE_SCRATCH1(r13); \
254 __LOAD_FAR_HANDLER(r9, label); \
255 mtctr r9; \
256 ld r9,area+EX_R9(r13); \
257 bctr
259 #define BRANCH_TO_KVM(reg, label) \
260 __LOAD_FAR_HANDLER(reg, label); \
261 mtctr reg; \
262 bctr
264 #else
265 #define BRANCH_TO_COMMON(reg, label) \
266 b label
268 #define BRANCH_LINK_TO_FAR(label) \
269 bl label
271 #define BRANCH_TO_KVM(reg, label) \
272 b label
274 #define __BRANCH_TO_KVM_EXIT(area, label) \
275 ld r9,area+EX_R9(r13); \
276 b label
278 #endif
281 #define __KVM_HANDLER(area, h, n) \
282 BEGIN_FTR_SECTION_NESTED(947) \
283 ld r10,area+EX_CFAR(r13); \
284 std r10,HSTATE_CFAR(r13); \
285 END_FTR_SECTION_NESTED(CPU_FTR_CFAR,CPU_FTR_CFAR,947); \
286 BEGIN_FTR_SECTION_NESTED(948) \
287 ld r10,area+EX_PPR(r13); \
288 std r10,HSTATE_PPR(r13); \
289 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948); \
290 ld r10,area+EX_R10(r13); \
291 std r12,HSTATE_SCRATCH0(r13); \
292 sldi r12,r9,32; \
293 ori r12,r12,(n); \
294 /* This reloads r9 before branching to kvmppc_interrupt */ \
295 __BRANCH_TO_KVM_EXIT(area, kvmppc_interrupt)
297 #define __KVM_HANDLER_SKIP(area, h, n) \
298 cmpwi r10,KVM_GUEST_MODE_SKIP; \
299 beq 89f; \
300 BEGIN_FTR_SECTION_NESTED(948) \
301 ld r10,area+EX_PPR(r13); \
302 std r10,HSTATE_PPR(r13); \
303 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948); \
304 ld r10,area+EX_R10(r13); \
305 std r12,HSTATE_SCRATCH0(r13); \
306 sldi r12,r9,32; \
307 ori r12,r12,(n); \
308 /* This reloads r9 before branching to kvmppc_interrupt */ \
309 __BRANCH_TO_KVM_EXIT(area, kvmppc_interrupt); \
310 89: mtocrf 0x80,r9; \
311 ld r9,area+EX_R9(r13); \
312 ld r10,area+EX_R10(r13); \
313 b kvmppc_skip_##h##interrupt
315 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
316 #define KVMTEST(h, n) __KVMTEST(h, n)
317 #define KVM_HANDLER(area, h, n) __KVM_HANDLER(area, h, n)
318 #define KVM_HANDLER_SKIP(area, h, n) __KVM_HANDLER_SKIP(area, h, n)
320 #else
321 #define KVMTEST(h, n)
322 #define KVM_HANDLER(area, h, n)
323 #define KVM_HANDLER_SKIP(area, h, n)
324 #endif
326 #define NOTEST(n)
329 * The common exception prolog is used for all except a few exceptions
330 * such as a segment miss on a kernel address. We have to be prepared
331 * to take another exception from the point where we first touch the
332 * kernel stack onwards.
334 * On entry r13 points to the paca, r9-r13 are saved in the paca,
335 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and
336 * SRR1, and relocation is on.
338 #define EXCEPTION_PROLOG_COMMON(n, area) \
339 andi. r10,r12,MSR_PR; /* See if coming from user */ \
340 mr r10,r1; /* Save r1 */ \
341 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \
342 beq- 1f; \
343 ld r1,PACAKSAVE(r13); /* kernel stack to use */ \
344 1: cmpdi cr1,r1,-INT_FRAME_SIZE; /* check if r1 is in userspace */ \
345 blt+ cr1,3f; /* abort if it is */ \
346 li r1,(n); /* will be reloaded later */ \
347 sth r1,PACA_TRAP_SAVE(r13); \
348 std r3,area+EX_R3(r13); \
349 addi r3,r13,area; /* r3 -> where regs are saved*/ \
350 RESTORE_CTR(r1, area); \
351 b bad_stack; \
352 3: std r9,_CCR(r1); /* save CR in stackframe */ \
353 std r11,_NIP(r1); /* save SRR0 in stackframe */ \
354 std r12,_MSR(r1); /* save SRR1 in stackframe */ \
355 std r10,0(r1); /* make stack chain pointer */ \
356 std r0,GPR0(r1); /* save r0 in stackframe */ \
357 std r10,GPR1(r1); /* save r1 in stackframe */ \
358 beq 4f; /* if from kernel mode */ \
359 ACCOUNT_CPU_USER_ENTRY(r13, r9, r10); \
360 SAVE_PPR(area, r9, r10); \
361 4: EXCEPTION_PROLOG_COMMON_2(area) \
362 EXCEPTION_PROLOG_COMMON_3(n) \
363 ACCOUNT_STOLEN_TIME
365 /* Save original regs values from save area to stack frame. */
366 #define EXCEPTION_PROLOG_COMMON_2(area) \
367 ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \
368 ld r10,area+EX_R10(r13); \
369 std r9,GPR9(r1); \
370 std r10,GPR10(r1); \
371 ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \
372 ld r10,area+EX_R12(r13); \
373 ld r11,area+EX_R13(r13); \
374 std r9,GPR11(r1); \
375 std r10,GPR12(r1); \
376 std r11,GPR13(r1); \
377 BEGIN_FTR_SECTION_NESTED(66); \
378 ld r10,area+EX_CFAR(r13); \
379 std r10,ORIG_GPR3(r1); \
380 END_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 66); \
381 GET_CTR(r10, area); \
382 std r10,_CTR(r1);
384 #define EXCEPTION_PROLOG_COMMON_3(n) \
385 std r2,GPR2(r1); /* save r2 in stackframe */ \
386 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
387 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
388 mflr r9; /* Get LR, later save to stack */ \
389 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \
390 std r9,_LINK(r1); \
391 lbz r10,PACASOFTIRQEN(r13); \
392 mfspr r11,SPRN_XER; /* save XER in stackframe */ \
393 std r10,SOFTE(r1); \
394 std r11,_XER(r1); \
395 li r9,(n)+1; \
396 std r9,_TRAP(r1); /* set trap number */ \
397 li r10,0; \
398 ld r11,exception_marker@toc(r2); \
399 std r10,RESULT(r1); /* clear regs->result */ \
400 std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */
403 * Exception vectors.
405 #define STD_EXCEPTION_PSERIES(vec, label) \
406 SET_SCRATCH0(r13); /* save r13 */ \
407 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label, \
408 EXC_STD, KVMTEST_PR, vec); \
410 /* Version of above for when we have to branch out-of-line */
411 #define __OOL_EXCEPTION(vec, label, hdlr) \
412 SET_SCRATCH0(r13) \
413 EXCEPTION_PROLOG_0(PACA_EXGEN) \
414 b hdlr;
416 #define STD_EXCEPTION_PSERIES_OOL(vec, label) \
417 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_PR, vec); \
418 EXCEPTION_PROLOG_PSERIES_1(label, EXC_STD)
420 #define STD_EXCEPTION_HV(loc, vec, label) \
421 SET_SCRATCH0(r13); /* save r13 */ \
422 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label, \
423 EXC_HV, KVMTEST_HV, vec);
425 #define STD_EXCEPTION_HV_OOL(vec, label) \
426 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, vec); \
427 EXCEPTION_PROLOG_PSERIES_1(label, EXC_HV)
429 #define STD_RELON_EXCEPTION_PSERIES(loc, vec, label) \
430 /* No guest interrupts come through here */ \
431 SET_SCRATCH0(r13); /* save r13 */ \
432 EXCEPTION_RELON_PROLOG_PSERIES(PACA_EXGEN, label, EXC_STD, NOTEST, vec);
434 #define STD_RELON_EXCEPTION_PSERIES_OOL(vec, label) \
435 EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, vec); \
436 EXCEPTION_RELON_PROLOG_PSERIES_1(label, EXC_STD)
438 #define STD_RELON_EXCEPTION_HV(loc, vec, label) \
439 SET_SCRATCH0(r13); /* save r13 */ \
440 EXCEPTION_RELON_PROLOG_PSERIES(PACA_EXGEN, label, \
441 EXC_HV, KVMTEST_HV, vec);
443 #define STD_RELON_EXCEPTION_HV_OOL(vec, label) \
444 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, vec); \
445 EXCEPTION_RELON_PROLOG_PSERIES_1(label, EXC_HV)
447 /* This associate vector numbers with bits in paca->irq_happened */
448 #define SOFTEN_VALUE_0x500 PACA_IRQ_EE
449 #define SOFTEN_VALUE_0x900 PACA_IRQ_DEC
450 #define SOFTEN_VALUE_0x980 PACA_IRQ_DEC
451 #define SOFTEN_VALUE_0xa00 PACA_IRQ_DBELL
452 #define SOFTEN_VALUE_0xe80 PACA_IRQ_DBELL
453 #define SOFTEN_VALUE_0xe60 PACA_IRQ_HMI
454 #define SOFTEN_VALUE_0xea0 PACA_IRQ_EE
456 #define __SOFTEN_TEST(h, vec) \
457 lbz r10,PACASOFTIRQEN(r13); \
458 cmpwi r10,0; \
459 li r10,SOFTEN_VALUE_##vec; \
460 beq masked_##h##interrupt
462 #define _SOFTEN_TEST(h, vec) __SOFTEN_TEST(h, vec)
464 #define SOFTEN_TEST_PR(vec) \
465 KVMTEST(EXC_STD, vec); \
466 _SOFTEN_TEST(EXC_STD, vec)
468 #define SOFTEN_TEST_HV(vec) \
469 KVMTEST(EXC_HV, vec); \
470 _SOFTEN_TEST(EXC_HV, vec)
472 #define KVMTEST_PR(vec) \
473 KVMTEST(EXC_STD, vec)
475 #define KVMTEST_HV(vec) \
476 KVMTEST(EXC_HV, vec)
478 #define SOFTEN_NOTEST_PR(vec) _SOFTEN_TEST(EXC_STD, vec)
479 #define SOFTEN_NOTEST_HV(vec) _SOFTEN_TEST(EXC_HV, vec)
481 #define __MASKABLE_EXCEPTION_PSERIES(vec, label, h, extra) \
482 SET_SCRATCH0(r13); /* save r13 */ \
483 EXCEPTION_PROLOG_0(PACA_EXGEN); \
484 __EXCEPTION_PROLOG_1(PACA_EXGEN, extra, vec); \
485 EXCEPTION_PROLOG_PSERIES_1(label, h);
487 #define _MASKABLE_EXCEPTION_PSERIES(vec, label, h, extra) \
488 __MASKABLE_EXCEPTION_PSERIES(vec, label, h, extra)
490 #define MASKABLE_EXCEPTION_PSERIES(loc, vec, label) \
491 _MASKABLE_EXCEPTION_PSERIES(vec, label, \
492 EXC_STD, SOFTEN_TEST_PR)
494 #define MASKABLE_EXCEPTION_PSERIES_OOL(vec, label) \
495 EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_TEST_PR, vec); \
496 EXCEPTION_PROLOG_PSERIES_1(label, EXC_STD)
498 #define MASKABLE_EXCEPTION_HV(loc, vec, label) \
499 _MASKABLE_EXCEPTION_PSERIES(vec, label, \
500 EXC_HV, SOFTEN_TEST_HV)
502 #define MASKABLE_EXCEPTION_HV_OOL(vec, label) \
503 EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_TEST_HV, vec); \
504 EXCEPTION_PROLOG_PSERIES_1(label, EXC_HV)
506 #define __MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, h, extra) \
507 SET_SCRATCH0(r13); /* save r13 */ \
508 EXCEPTION_PROLOG_0(PACA_EXGEN); \
509 __EXCEPTION_PROLOG_1(PACA_EXGEN, extra, vec); \
510 EXCEPTION_RELON_PROLOG_PSERIES_1(label, h)
512 #define _MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, h, extra) \
513 __MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, h, extra)
515 #define MASKABLE_RELON_EXCEPTION_PSERIES(loc, vec, label) \
516 _MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, \
517 EXC_STD, SOFTEN_NOTEST_PR)
519 #define MASKABLE_RELON_EXCEPTION_HV(loc, vec, label) \
520 _MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, \
521 EXC_HV, SOFTEN_TEST_HV)
523 #define MASKABLE_RELON_EXCEPTION_HV_OOL(vec, label) \
524 EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_TEST_HV, vec); \
525 EXCEPTION_PROLOG_PSERIES_1(label, EXC_HV)
528 * Our exception common code can be passed various "additions"
529 * to specify the behaviour of interrupts, whether to kick the
530 * runlatch, etc...
534 * This addition reconciles our actual IRQ state with the various software
535 * flags that track it. This may call C code.
537 #define ADD_RECONCILE RECONCILE_IRQ_STATE(r10,r11)
539 #define ADD_NVGPRS \
540 bl save_nvgprs
542 #define RUNLATCH_ON \
543 BEGIN_FTR_SECTION \
544 CURRENT_THREAD_INFO(r3, r1); \
545 ld r4,TI_LOCAL_FLAGS(r3); \
546 andi. r0,r4,_TLF_RUNLATCH; \
547 beql ppc64_runlatch_on_trampoline; \
548 END_FTR_SECTION_IFSET(CPU_FTR_CTRL)
550 #define EXCEPTION_COMMON(trap, label, hdlr, ret, additions) \
551 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
552 /* Volatile regs are potentially clobbered here */ \
553 additions; \
554 addi r3,r1,STACK_FRAME_OVERHEAD; \
555 bl hdlr; \
556 b ret
558 #define STD_EXCEPTION_COMMON(trap, label, hdlr) \
559 EXCEPTION_COMMON(trap, label, hdlr, ret_from_except, \
560 ADD_NVGPRS;ADD_RECONCILE)
563 * Like STD_EXCEPTION_COMMON, but for exceptions that can occur
564 * in the idle task and therefore need the special idle handling
565 * (finish nap and runlatch)
567 #define STD_EXCEPTION_COMMON_ASYNC(trap, label, hdlr) \
568 EXCEPTION_COMMON(trap, label, hdlr, ret_from_except_lite, \
569 FINISH_NAP;ADD_RECONCILE;RUNLATCH_ON)
572 * When the idle code in power4_idle puts the CPU into NAP mode,
573 * it has to do so in a loop, and relies on the external interrupt
574 * and decrementer interrupt entry code to get it out of the loop.
575 * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags
576 * to signal that it is in the loop and needs help to get out.
578 #ifdef CONFIG_PPC_970_NAP
579 #define FINISH_NAP \
580 BEGIN_FTR_SECTION \
581 CURRENT_THREAD_INFO(r11, r1); \
582 ld r9,TI_LOCAL_FLAGS(r11); \
583 andi. r10,r9,_TLF_NAPPING; \
584 bnel power4_fixup_nap; \
585 END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
586 #else
587 #define FINISH_NAP
588 #endif
590 #endif /* _ASM_POWERPC_EXCEPTION_H */