arch/powerpc/include/asm/io.h

   1 #ifndef _ASM_POWERPC_IO_H
   2 #define _ASM_POWERPC_IO_H
   3 #ifdef __KERNEL__
   4
   5 #define ARCH_HAS_IOREMAP_WC
   6
   7 /*
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * as published by the Free Software Foundation; either version
  11  * 2 of the License, or (at your option) any later version.
  12  */
  13
  14 /* Check of existence of legacy devices */
  15 extern int check_legacy_ioport(unsigned long base_port);
  16 #define I8042_DATA_REG  0x60
  17 #define FDC_BASE        0x3f0
  18
  19 #if defined(CONFIG_PPC64) && defined(CONFIG_PCI)
  20 extern struct pci_dev *isa_bridge_pcidev;
  21 /*
  22  * has legacy ISA devices ?
  23  */
  24 #define arch_has_dev_port()     (isa_bridge_pcidev != NULL || isa_io_special)
  25 #endif
  26
  27 #include <linux/device.h>
  28 #include <linux/io.h>
  29
  30 #include <linux/compiler.h>
  31 #include <asm/page.h>
  32 #include <asm/byteorder.h>
  33 #include <asm/synch.h>
  34 #include <asm/delay.h>
  35 #include <asm/mmu.h>
  36 #include <asm/ppc_asm.h>
  37
  38 #include <asm-generic/iomap.h>
  39
  40 #ifdef CONFIG_PPC64
  41 #include <asm/paca.h>
  42 #endif
  43
  44 #define SIO_CONFIG_RA   0x398
  45 #define SIO_CONFIG_RD   0x399
  46
  47 #define SLOW_DOWN_IO
  48
  49 /* 32 bits uses slightly different variables for the various IO
  50  * bases. Most of this file only uses _IO_BASE though which we
  51  * define properly based on the platform
  52  */
  53 #ifndef CONFIG_PCI
  54 #define _IO_BASE        0
  55 #define _ISA_MEM_BASE   0
  56 #define PCI_DRAM_OFFSET 0
  57 #elif defined(CONFIG_PPC32)
  58 #define _IO_BASE        isa_io_base
  59 #define _ISA_MEM_BASE   isa_mem_base
  60 #define PCI_DRAM_OFFSET pci_dram_offset
  61 #else
  62 #define _IO_BASE        pci_io_base
  63 #define _ISA_MEM_BASE   isa_mem_base
  64 #define PCI_DRAM_OFFSET 0
  65 #endif
  66
  67 extern unsigned long isa_io_base;
  68 extern unsigned long pci_io_base;
  69 extern unsigned long pci_dram_offset;
  70
  71 extern resource_size_t isa_mem_base;
  72
  73 /* Boolean set by platform if PIO accesses are suppored while _IO_BASE
  74  * is not set or addresses cannot be translated to MMIO. This is typically
  75  * set when the platform supports "special" PIO accesses via a non memory
  76  * mapped mechanism, and allows things like the early udbg UART code to
  77  * function.
  78  */
  79 extern bool isa_io_special;
  80
  81 #ifdef CONFIG_PPC32
  82 #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
  83 #error CONFIG_PPC_INDIRECT_{PIO,MMIO} are not yet supported on 32 bits
  84 #endif
  85 #endif
  86
  87 /*
  88  *
  89  * Low level MMIO accessors
  90  *
  91  * This provides the non-bus specific accessors to MMIO. Those are PowerPC
  92  * specific and thus shouldn't be used in generic code. The accessors
  93  * provided here are:
  94  *
  95  *      in_8, in_le16, in_be16, in_le32, in_be32, in_le64, in_be64
  96  *      out_8, out_le16, out_be16, out_le32, out_be32, out_le64, out_be64
  97  *      _insb, _insw_ns, _insl_ns, _outsb, _outsw_ns, _outsl_ns
  98  *
  99  * Those operate directly on a kernel virtual address. Note that the prototype
 100  * for the out_* accessors has the arguments in opposite order from the usual
 101  * linux PCI accessors. Unlike those, they take the address first and the value
 102  * next.
 103  *
 104  * Note: I might drop the _ns suffix on the stream operations soon as it is
 105  * simply normal for stream operations to not swap in the first place.
 106  *
 107  */
 108
 109 #ifdef CONFIG_PPC64
 110 #define IO_SET_SYNC_FLAG()      do { local_paca->io_sync = 1; } while(0)
 111 #else
 112 #define IO_SET_SYNC_FLAG()
 113 #endif
 114
 115 /* gcc 4.0 and older doesn't have 'Z' constraint */
 116 #if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ == 0)
 117 #define DEF_MMIO_IN_X(name, size, insn)                         \
 118 static inline u##size name(const volatile u##size __iomem *addr)        \
 119 {                                                                       \
 120         u##size ret;                                                    \
 121         __asm__ __volatile__("sync;"#insn" %0,0,%1;twi 0,%0,0;isync"    \
 122                 : "=r" (ret) : "r" (addr), "m" (*addr) : "memory");     \
 123         return ret;                                                     \
 124 }
 125
 126 #define DEF_MMIO_OUT_X(name, size, insn)                                \
 127 static inline void name(volatile u##size __iomem *addr, u##size val)    \
 128 {                                                                       \
 129         __asm__ __volatile__("sync;"#insn" %1,0,%2"                     \
 130                 : "=m" (*addr) : "r" (val), "r" (addr) : "memory");     \
 131         IO_SET_SYNC_FLAG();                                             \
 132 }
 133 #else /* newer gcc */
 134 #define DEF_MMIO_IN_X(name, size, insn)                         \
 135 static inline u##size name(const volatile u##size __iomem *addr)        \
 136 {                                                                       \
 137         u##size ret;                                                    \
 138         __asm__ __volatile__("sync;"#insn" %0,%y1;twi 0,%0,0;isync"     \
 139                 : "=r" (ret) : "Z" (*addr) : "memory");                 \
 140         return ret;                                                     \
 141 }
 142
 143 #define DEF_MMIO_OUT_X(name, size, insn)                                \
 144 static inline void name(volatile u##size __iomem *addr, u##size val)    \
 145 {                                                                       \
 146         __asm__ __volatile__("sync;"#insn" %1,%y0"                      \
 147                 : "=Z" (*addr) : "r" (val) : "memory");                 \
 148         IO_SET_SYNC_FLAG();                                             \
 149 }
 150 #endif
 151
 152 #define DEF_MMIO_IN_D(name, size, insn)                         \
 153 static inline u##size name(const volatile u##size __iomem *addr)        \
 154 {                                                                       \
 155         u##size ret;                                                    \
 156         __asm__ __volatile__("sync;"#insn"%U1%X1 %0,%1;twi 0,%0,0;isync"\
 157                 : "=r" (ret) : "m" (*addr) : "memory");                 \
 158         return ret;                                                     \
 159 }
 160
 161 #define DEF_MMIO_OUT_D(name, size, insn)                                \
 162 static inline void name(volatile u##size __iomem *addr, u##size val)    \
 163 {                                                                       \
 164         __asm__ __volatile__("sync;"#insn"%U0%X0 %1,%0"                 \
 165                 : "=m" (*addr) : "r" (val) : "memory");                 \
 166         IO_SET_SYNC_FLAG();                                             \
 167 }
 168
 169 DEF_MMIO_IN_D(in_8,     8, lbz);
 170 DEF_MMIO_OUT_D(out_8,   8, stb);
 171
 172 #ifdef __BIG_ENDIAN__
 173 DEF_MMIO_IN_D(in_be16, 16, lhz);
 174 DEF_MMIO_IN_D(in_be32, 32, lwz);
 175 DEF_MMIO_IN_X(in_le16, 16, lhbrx);
 176 DEF_MMIO_IN_X(in_le32, 32, lwbrx);
 177
 178 DEF_MMIO_OUT_D(out_be16, 16, sth);
 179 DEF_MMIO_OUT_D(out_be32, 32, stw);
 180 DEF_MMIO_OUT_X(out_le16, 16, sthbrx);
 181 DEF_MMIO_OUT_X(out_le32, 32, stwbrx);
 182 #else
 183 DEF_MMIO_IN_X(in_be16, 16, lhbrx);
 184 DEF_MMIO_IN_X(in_be32, 32, lwbrx);
 185 DEF_MMIO_IN_D(in_le16, 16, lhz);
 186 DEF_MMIO_IN_D(in_le32, 32, lwz);
 187
 188 DEF_MMIO_OUT_X(out_be16, 16, sthbrx);
 189 DEF_MMIO_OUT_X(out_be32, 32, stwbrx);
 190 DEF_MMIO_OUT_D(out_le16, 16, sth);
 191 DEF_MMIO_OUT_D(out_le32, 32, stw);
 192
 193 #endif /* __BIG_ENDIAN */
 194
 195 /*
 196  * Cache inhibitied accessors for use in real mode, you don't want to use these
 197  * unless you know what you're doing.
 198  *
 199  * NB. These use the cpu byte ordering.
 200  */
 201 DEF_MMIO_OUT_X(out_rm8,   8, stbcix);
 202 DEF_MMIO_OUT_X(out_rm16, 16, sthcix);
 203 DEF_MMIO_OUT_X(out_rm32, 32, stwcix);
 204 DEF_MMIO_IN_X(in_rm8,   8, lbzcix);
 205 DEF_MMIO_IN_X(in_rm16, 16, lhzcix);
 206 DEF_MMIO_IN_X(in_rm32, 32, lwzcix);
 207
 208 #ifdef __powerpc64__
 209
 210 DEF_MMIO_OUT_X(out_rm64, 64, stdcix);
 211 DEF_MMIO_IN_X(in_rm64, 64, ldcix);
 212
 213 #ifdef __BIG_ENDIAN__
 214 DEF_MMIO_OUT_D(out_be64, 64, std);
 215 DEF_MMIO_IN_D(in_be64, 64, ld);
 216
 217 /* There is no asm instructions for 64 bits reverse loads and stores */
 218 static inline u64 in_le64(const volatile u64 __iomem *addr)
 219 {
 220         return swab64(in_be64(addr));
 221 }
 222
 223 static inline void out_le64(volatile u64 __iomem *addr, u64 val)
 224 {
 225         out_be64(addr, swab64(val));
 226 }
 227 #else
 228 DEF_MMIO_OUT_D(out_le64, 64, std);
 229 DEF_MMIO_IN_D(in_le64, 64, ld);
 230
 231 /* There is no asm instructions for 64 bits reverse loads and stores */
 232 static inline u64 in_be64(const volatile u64 __iomem *addr)
 233 {
 234         return swab64(in_le64(addr));
 235 }
 236
 237 static inline void out_be64(volatile u64 __iomem *addr, u64 val)
 238 {
 239         out_le64(addr, swab64(val));
 240 }
 241
 242 #endif
 243 #endif /* __powerpc64__ */
 244
 245
 246 /*
 247  * Simple Cache inhibited accessors
 248  * Unlike the DEF_MMIO_* macros, these don't include any h/w memory
 249  * barriers, callers need to manage memory barriers on their own.
 250  * These can only be used in hypervisor real mode.
 251  */
 252
 253 static inline u32 _lwzcix(unsigned long addr)
 254 {
 255         u32 ret;
 256
 257         __asm__ __volatile__("lwzcix %0,0, %1"
 258                              : "=r" (ret) : "r" (addr) : "memory");
 259         return ret;
 260 }
 261
 262 static inline void _stbcix(u64 addr, u8 val)
 263 {
 264         __asm__ __volatile__("stbcix %0,0,%1"
 265                 : : "r" (val), "r" (addr) : "memory");
 266 }
 267
 268 static inline void _stwcix(u64 addr, u32 val)
 269 {
 270         __asm__ __volatile__("stwcix %0,0,%1"
 271                 : : "r" (val), "r" (addr) : "memory");
 272 }
 273
 274 /*
 275  * Low level IO stream instructions are defined out of line for now
 276  */
 277 extern void _insb(const volatile u8 __iomem *addr, void *buf, long count);
 278 extern void _outsb(volatile u8 __iomem *addr,const void *buf,long count);
 279 extern void _insw_ns(const volatile u16 __iomem *addr, void *buf, long count);
 280 extern void _outsw_ns(volatile u16 __iomem *addr, const void *buf, long count);
 281 extern void _insl_ns(const volatile u32 __iomem *addr, void *buf, long count);
 282 extern void _outsl_ns(volatile u32 __iomem *addr, const void *buf, long count);
 283
 284 /* The _ns naming is historical and will be removed. For now, just #define
 285  * the non _ns equivalent names
 286  */
 287 #define _insw   _insw_ns
 288 #define _insl   _insl_ns
 289 #define _outsw  _outsw_ns
 290 #define _outsl  _outsl_ns
 291
 292
 293 /*
 294  * memset_io, memcpy_toio, memcpy_fromio base implementations are out of line
 295  */
 296
 297 extern void _memset_io(volatile void __iomem *addr, int c, unsigned long n);
 298 extern void _memcpy_fromio(void *dest, const volatile void __iomem *src,
 299                            unsigned long n);
 300 extern void _memcpy_toio(volatile void __iomem *dest, const void *src,
 301                          unsigned long n);
 302
 303 /*
 304  *
 305  * PCI and standard ISA accessors
 306  *
 307  * Those are globally defined linux accessors for devices on PCI or ISA
 308  * busses. They follow the Linux defined semantics. The current implementation
 309  * for PowerPC is as close as possible to the x86 version of these, and thus
 310  * provides fairly heavy weight barriers for the non-raw versions
 311  *
 312  * In addition, they support a hook mechanism when CONFIG_PPC_INDIRECT_MMIO
 313  * or CONFIG_PPC_INDIRECT_PIO are set allowing the platform to provide its
 314  * own implementation of some or all of the accessors.
 315  */
 316
 317 /*
 318  * Include the EEH definitions when EEH is enabled only so they don't get
 319  * in the way when building for 32 bits
 320  */
 321 #ifdef CONFIG_EEH
 322 #include <asm/eeh.h>
 323 #endif
 324
 325 /* Shortcut to the MMIO argument pointer */
 326 #define PCI_IO_ADDR     volatile void __iomem *
 327
 328 /* Indirect IO address tokens:
 329  *
 330  * When CONFIG_PPC_INDIRECT_MMIO is set, the platform can provide hooks
 331  * on all MMIOs. (Note that this is all 64 bits only for now)
 332  *
 333  * To help platforms who may need to differentiate MMIO addresses in
 334  * their hooks, a bitfield is reserved for use by the platform near the
 335  * top of MMIO addresses (not PIO, those have to cope the hard way).
 336  *
 337  * This bit field is 12 bits and is at the top of the IO virtual
 338  * addresses PCI_IO_INDIRECT_TOKEN_MASK.
 339  *
 340  * The kernel virtual space is thus:
 341  *
 342  *  0xD000000000000000          : vmalloc
 343  *  0xD000080000000000          : PCI PHB IO space
 344  *  0xD000080080000000          : ioremap
 345  *  0xD0000fffffffffff          : end of ioremap region
 346  *
 347  * Since the top 4 bits are reserved as the region ID, we use thus
 348  * the next 12 bits and keep 4 bits available for the future if the
 349  * virtual address space is ever to be extended.
 350  *
 351  * The direct IO mapping operations will then mask off those bits
 352  * before doing the actual access, though that only happen when
 353  * CONFIG_PPC_INDIRECT_MMIO is set, thus be careful when you use that
 354  * mechanism
 355  *
 356  * For PIO, there is a separate CONFIG_PPC_INDIRECT_PIO which makes
 357  * all PIO functions call through a hook.
 358  */
 359
 360 #ifdef CONFIG_PPC_INDIRECT_MMIO
 361 #define PCI_IO_IND_TOKEN_MASK   0x0fff000000000000ul
 362 #define PCI_IO_IND_TOKEN_SHIFT  48
 363 #define PCI_FIX_ADDR(addr)                                              \
 364         ((PCI_IO_ADDR)(((unsigned long)(addr)) & ~PCI_IO_IND_TOKEN_MASK))
 365 #define PCI_GET_ADDR_TOKEN(addr)                                        \
 366         (((unsigned long)(addr) & PCI_IO_IND_TOKEN_MASK) >>             \
 367                 PCI_IO_IND_TOKEN_SHIFT)
 368 #define PCI_SET_ADDR_TOKEN(addr, token)                                 \
 369 do {                                                                    \
 370         unsigned long __a = (unsigned long)(addr);                      \
 371         __a &= ~PCI_IO_IND_TOKEN_MASK;                                  \
 372         __a |= ((unsigned long)(token)) << PCI_IO_IND_TOKEN_SHIFT;      \
 373         (addr) = (void __iomem *)__a;                                   \
 374 } while(0)
 375 #else
 376 #define PCI_FIX_ADDR(addr) (addr)
 377 #endif
 378
 379
 380 /*
 381  * Non ordered and non-swapping "raw" accessors
 382  */
 383
 384 static inline unsigned char __raw_readb(const volatile void __iomem *addr)
 385 {
 386         return *(volatile unsigned char __force *)PCI_FIX_ADDR(addr);
 387 }
 388 static inline unsigned short __raw_readw(const volatile void __iomem *addr)
 389 {
 390         return *(volatile unsigned short __force *)PCI_FIX_ADDR(addr);
 391 }
 392 static inline unsigned int __raw_readl(const volatile void __iomem *addr)
 393 {
 394         return *(volatile unsigned int __force *)PCI_FIX_ADDR(addr);
 395 }
 396 static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
 397 {
 398         *(volatile unsigned char __force *)PCI_FIX_ADDR(addr) = v;
 399 }
 400 static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
 401 {
 402         *(volatile unsigned short __force *)PCI_FIX_ADDR(addr) = v;
 403 }
 404 static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
 405 {
 406         *(volatile unsigned int __force *)PCI_FIX_ADDR(addr) = v;
 407 }
 408
 409 #ifdef __powerpc64__
 410 static inline unsigned long __raw_readq(const volatile void __iomem *addr)
 411 {
 412         return *(volatile unsigned long __force *)PCI_FIX_ADDR(addr);
 413 }
 414 static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr)
 415 {
 416         *(volatile unsigned long __force *)PCI_FIX_ADDR(addr) = v;
 417 }
 418
 419 /*
 420  * Real mode version of the above. stdcix is only supposed to be used
 421  * in hypervisor real mode as per the architecture spec.
 422  */
 423 static inline void __raw_rm_writeq(u64 val, volatile void __iomem *paddr)
 424 {
 425         __asm__ __volatile__("stdcix %0,0,%1"
 426                 : : "r" (val), "r" (paddr) : "memory");
 427 }
 428
 429 #endif /* __powerpc64__ */
 430
 431 /*
 432  *
 433  * PCI PIO and MMIO accessors.
 434  *
 435  *
 436  * On 32 bits, PIO operations have a recovery mechanism in case they trigger
 437  * machine checks (which they occasionally do when probing non existing
 438  * IO ports on some platforms, like PowerMac and 8xx).
 439  * I always found it to be of dubious reliability and I am tempted to get
 440  * rid of it one of these days. So if you think it's important to keep it,
 441  * please voice up asap. We never had it for 64 bits and I do not intend
 442  * to port it over
 443  */
 444
 445 #ifdef CONFIG_PPC32
 446
 447 #define __do_in_asm(name, op)                           \
 448 static inline unsigned int name(unsigned int port)      \
 449 {                                                       \
 450         unsigned int x;                                 \
 451         __asm__ __volatile__(                           \
 452                 "sync\n"                                \
 453                 "0:"    op "    %0,0,%1\n"              \
 454                 "1:     twi     0,%0,0\n"               \
 455                 "2:     isync\n"                        \
 456                 "3:     nop\n"                          \
 457                 "4:\n"                                  \
 458                 ".section .fixup,\"ax\"\n"              \
 459                 "5:     li      %0,-1\n"                \
 460                 "       b       4b\n"                   \
 461                 ".previous\n"                           \
 462                 EX_TABLE(0b, 5b)                        \
 463                 EX_TABLE(1b, 5b)                        \
 464                 EX_TABLE(2b, 5b)                        \
 465                 EX_TABLE(3b, 5b)                        \
 466                 : "=&r" (x)                             \
 467                 : "r" (port + _IO_BASE)                 \
 468                 : "memory");                            \
 469         return x;                                       \
 470 }
 471
 472 #define __do_out_asm(name, op)                          \
 473 static inline void name(unsigned int val, unsigned int port) \
 474 {                                                       \
 475         __asm__ __volatile__(                           \
 476                 "sync\n"                                \
 477                 "0:" op " %0,0,%1\n"                    \
 478                 "1:     sync\n"                         \
 479                 "2:\n"                                  \
 480                 EX_TABLE(0b, 2b)                        \
 481                 EX_TABLE(1b, 2b)                        \
 482                 : : "r" (val), "r" (port + _IO_BASE)    \
 483                 : "memory");                            \
 484 }
 485
 486 __do_in_asm(_rec_inb, "lbzx")
 487 __do_in_asm(_rec_inw, "lhbrx")
 488 __do_in_asm(_rec_inl, "lwbrx")
 489 __do_out_asm(_rec_outb, "stbx")
 490 __do_out_asm(_rec_outw, "sthbrx")
 491 __do_out_asm(_rec_outl, "stwbrx")
 492
 493 #endif /* CONFIG_PPC32 */
 494
 495 /* The "__do_*" operations below provide the actual "base" implementation
 496  * for each of the defined accessors. Some of them use the out_* functions
 497  * directly, some of them still use EEH, though we might change that in the
 498  * future. Those macros below provide the necessary argument swapping and
 499  * handling of the IO base for PIO.
 500  *
 501  * They are themselves used by the macros that define the actual accessors
 502  * and can be used by the hooks if any.
 503  *
 504  * Note that PIO operations are always defined in terms of their corresonding
 505  * MMIO operations. That allows platforms like iSeries who want to modify the
 506  * behaviour of both to only hook on the MMIO version and get both. It's also
 507  * possible to hook directly at the toplevel PIO operation if they have to
 508  * be handled differently
 509  */
 510 #define __do_writeb(val, addr)  out_8(PCI_FIX_ADDR(addr), val)
 511 #define __do_writew(val, addr)  out_le16(PCI_FIX_ADDR(addr), val)
 512 #define __do_writel(val, addr)  out_le32(PCI_FIX_ADDR(addr), val)
 513 #define __do_writeq(val, addr)  out_le64(PCI_FIX_ADDR(addr), val)
 514 #define __do_writew_be(val, addr) out_be16(PCI_FIX_ADDR(addr), val)
 515 #define __do_writel_be(val, addr) out_be32(PCI_FIX_ADDR(addr), val)
 516 #define __do_writeq_be(val, addr) out_be64(PCI_FIX_ADDR(addr), val)
 517
 518 #ifdef CONFIG_EEH
 519 #define __do_readb(addr)        eeh_readb(PCI_FIX_ADDR(addr))
 520 #define __do_readw(addr)        eeh_readw(PCI_FIX_ADDR(addr))
 521 #define __do_readl(addr)        eeh_readl(PCI_FIX_ADDR(addr))
 522 #define __do_readq(addr)        eeh_readq(PCI_FIX_ADDR(addr))
 523 #define __do_readw_be(addr)     eeh_readw_be(PCI_FIX_ADDR(addr))
 524 #define __do_readl_be(addr)     eeh_readl_be(PCI_FIX_ADDR(addr))
 525 #define __do_readq_be(addr)     eeh_readq_be(PCI_FIX_ADDR(addr))
 526 #else /* CONFIG_EEH */
 527 #define __do_readb(addr)        in_8(PCI_FIX_ADDR(addr))
 528 #define __do_readw(addr)        in_le16(PCI_FIX_ADDR(addr))
 529 #define __do_readl(addr)        in_le32(PCI_FIX_ADDR(addr))
 530 #define __do_readq(addr)        in_le64(PCI_FIX_ADDR(addr))
 531 #define __do_readw_be(addr)     in_be16(PCI_FIX_ADDR(addr))
 532 #define __do_readl_be(addr)     in_be32(PCI_FIX_ADDR(addr))
 533 #define __do_readq_be(addr)     in_be64(PCI_FIX_ADDR(addr))
 534 #endif /* !defined(CONFIG_EEH) */
 535
 536 #ifdef CONFIG_PPC32
 537 #define __do_outb(val, port)    _rec_outb(val, port)
 538 #define __do_outw(val, port)    _rec_outw(val, port)
 539 #define __do_outl(val, port)    _rec_outl(val, port)
 540 #define __do_inb(port)          _rec_inb(port)
 541 #define __do_inw(port)          _rec_inw(port)
 542 #define __do_inl(port)          _rec_inl(port)
 543 #else /* CONFIG_PPC32 */
 544 #define __do_outb(val, port)    writeb(val,(PCI_IO_ADDR)_IO_BASE+port);
 545 #define __do_outw(val, port)    writew(val,(PCI_IO_ADDR)_IO_BASE+port);
 546 #define __do_outl(val, port)    writel(val,(PCI_IO_ADDR)_IO_BASE+port);
 547 #define __do_inb(port)          readb((PCI_IO_ADDR)_IO_BASE + port);
 548 #define __do_inw(port)          readw((PCI_IO_ADDR)_IO_BASE + port);
 549 #define __do_inl(port)          readl((PCI_IO_ADDR)_IO_BASE + port);
 550 #endif /* !CONFIG_PPC32 */
 551
 552 #ifdef CONFIG_EEH
 553 #define __do_readsb(a, b, n)    eeh_readsb(PCI_FIX_ADDR(a), (b), (n))
 554 #define __do_readsw(a, b, n)    eeh_readsw(PCI_FIX_ADDR(a), (b), (n))
 555 #define __do_readsl(a, b, n)    eeh_readsl(PCI_FIX_ADDR(a), (b), (n))
 556 #else /* CONFIG_EEH */
 557 #define __do_readsb(a, b, n)    _insb(PCI_FIX_ADDR(a), (b), (n))
 558 #define __do_readsw(a, b, n)    _insw(PCI_FIX_ADDR(a), (b), (n))
 559 #define __do_readsl(a, b, n)    _insl(PCI_FIX_ADDR(a), (b), (n))
 560 #endif /* !CONFIG_EEH */
 561 #define __do_writesb(a, b, n)   _outsb(PCI_FIX_ADDR(a),(b),(n))
 562 #define __do_writesw(a, b, n)   _outsw(PCI_FIX_ADDR(a),(b),(n))
 563 #define __do_writesl(a, b, n)   _outsl(PCI_FIX_ADDR(a),(b),(n))
 564
 565 #define __do_insb(p, b, n)      readsb((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
 566 #define __do_insw(p, b, n)      readsw((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
 567 #define __do_insl(p, b, n)      readsl((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
 568 #define __do_outsb(p, b, n)     writesb((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
 569 #define __do_outsw(p, b, n)     writesw((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
 570 #define __do_outsl(p, b, n)     writesl((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
 571
 572 #define __do_memset_io(addr, c, n)      \
 573                                 _memset_io(PCI_FIX_ADDR(addr), c, n)
 574 #define __do_memcpy_toio(dst, src, n)   \
 575                                 _memcpy_toio(PCI_FIX_ADDR(dst), src, n)
 576
 577 #ifdef CONFIG_EEH
 578 #define __do_memcpy_fromio(dst, src, n) \
 579                                 eeh_memcpy_fromio(dst, PCI_FIX_ADDR(src), n)
 580 #else /* CONFIG_EEH */
 581 #define __do_memcpy_fromio(dst, src, n) \
 582                                 _memcpy_fromio(dst,PCI_FIX_ADDR(src),n)
 583 #endif /* !CONFIG_EEH */
 584
 585 #ifdef CONFIG_PPC_INDIRECT_PIO
 586 #define DEF_PCI_HOOK_pio(x)     x
 587 #else
 588 #define DEF_PCI_HOOK_pio(x)     NULL
 589 #endif
 590
 591 #ifdef CONFIG_PPC_INDIRECT_MMIO
 592 #define DEF_PCI_HOOK_mem(x)     x
 593 #else
 594 #define DEF_PCI_HOOK_mem(x)     NULL
 595 #endif
 596
 597 /* Structure containing all the hooks */
 598 extern struct ppc_pci_io {
 599
 600 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa)    ret (*name) at;
 601 #define DEF_PCI_AC_NORET(name, at, al, space, aa)       void (*name) at;
 602
 603 #include <asm/io-defs.h>
 604
 605 #undef DEF_PCI_AC_RET
 606 #undef DEF_PCI_AC_NORET
 607
 608 } ppc_pci_io;
 609
 610 /* The inline wrappers */
 611 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa)            \
 612 static inline ret name at                                       \
 613 {                                                               \
 614         if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL)      \
 615                 return ppc_pci_io.name al;                      \
 616         return __do_##name al;                                  \
 617 }
 618
 619 #define DEF_PCI_AC_NORET(name, at, al, space, aa)               \
 620 static inline void name at                                      \
 621 {                                                               \
 622         if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL)              \
 623                 ppc_pci_io.name al;                             \
 624         else                                                    \
 625                 __do_##name al;                                 \
 626 }
 627
 628 #include <asm/io-defs.h>
 629
 630 #undef DEF_PCI_AC_RET
 631 #undef DEF_PCI_AC_NORET
 632
 633 /* Some drivers check for the presence of readq & writeq with
 634  * a #ifdef, so we make them happy here.
 635  */
 636 #ifdef __powerpc64__
 637 #define readq   readq
 638 #define writeq  writeq
 639 #endif
 640
 641 /*
 642  * Convert a physical pointer to a virtual kernel pointer for /dev/mem
 643  * access
 644  */
 645 #define xlate_dev_mem_ptr(p)    __va(p)
 646
 647 /*
 648  * Convert a virtual cached pointer to an uncached pointer
 649  */
 650 #define xlate_dev_kmem_ptr(p)   p
 651
 652 /*
 653  * We don't do relaxed operations yet, at least not with this semantic
 654  */
 655 #define readb_relaxed(addr)     readb(addr)
 656 #define readw_relaxed(addr)     readw(addr)
 657 #define readl_relaxed(addr)     readl(addr)
 658 #define readq_relaxed(addr)     readq(addr)
 659 #define writeb_relaxed(v, addr) writeb(v, addr)
 660 #define writew_relaxed(v, addr) writew(v, addr)
 661 #define writel_relaxed(v, addr) writel(v, addr)
 662 #define writeq_relaxed(v, addr) writeq(v, addr)
 663
 664 #ifdef CONFIG_PPC32
 665 #define mmiowb()
 666 #else
 667 /*
 668  * Enforce synchronisation of stores vs. spin_unlock
 669  * (this does it explicitly, though our implementation of spin_unlock
 670  * does it implicitely too)
 671  */
 672 static inline void mmiowb(void)
 673 {
 674         unsigned long tmp;
 675
 676         __asm__ __volatile__("sync; li %0,0; stb %0,%1(13)"
 677         : "=&r" (tmp) : "i" (offsetof(struct paca_struct, io_sync))
 678         : "memory");
 679 }
 680 #endif /* !CONFIG_PPC32 */
 681
 682 static inline void iosync(void)
 683 {
 684         __asm__ __volatile__ ("sync" : : : "memory");
 685 }
 686
 687 /* Enforce in-order execution of data I/O.
 688  * No distinction between read/write on PPC; use eieio for all three.
 689  * Those are fairly week though. They don't provide a barrier between
 690  * MMIO and cacheable storage nor do they provide a barrier vs. locks,
 691  * they only provide barriers between 2 __raw MMIO operations and
 692  * possibly break write combining.
 693  */
 694 #define iobarrier_rw() eieio()
 695 #define iobarrier_r()  eieio()
 696 #define iobarrier_w()  eieio()
 697
 698
 699 /*
 700  * output pause versions need a delay at least for the
 701  * w83c105 ide controller in a p610.
 702  */
 703 #define inb_p(port)             inb(port)
 704 #define outb_p(val, port)       (udelay(1), outb((val), (port)))
 705 #define inw_p(port)             inw(port)
 706 #define outw_p(val, port)       (udelay(1), outw((val), (port)))
 707 #define inl_p(port)             inl(port)
 708 #define outl_p(val, port)       (udelay(1), outl((val), (port)))
 709
 710
 711 #define IO_SPACE_LIMIT ~(0UL)
 712
 713
 714 /**
 715  * ioremap     -   map bus memory into CPU space
 716  * @address:   bus address of the memory
 717  * @size:      size of the resource to map
 718  *
 719  * ioremap performs a platform specific sequence of operations to
 720  * make bus memory CPU accessible via the readb/readw/readl/writeb/
 721  * writew/writel functions and the other mmio helpers. The returned
 722  * address is not guaranteed to be usable directly as a virtual
 723  * address.
 724  *
 725  * We provide a few variations of it:
 726  *
 727  * * ioremap is the standard one and provides non-cacheable guarded mappings
 728  *   and can be hooked by the platform via ppc_md
 729  *
 730  * * ioremap_prot allows to specify the page flags as an argument and can
 731  *   also be hooked by the platform via ppc_md.
 732  *
 733  * * ioremap_nocache is identical to ioremap
 734  *
 735  * * ioremap_wc enables write combining
 736  *
 737  * * iounmap undoes such a mapping and can be hooked
 738  *
 739  * * __ioremap_at (and the pending __iounmap_at) are low level functions to
 740  *   create hand-made mappings for use only by the PCI code and cannot
 741  *   currently be hooked. Must be page aligned.
 742  *
 743  * * __ioremap is the low level implementation used by ioremap and
 744  *   ioremap_prot and cannot be hooked (but can be used by a hook on one
 745  *   of the previous ones)
 746  *
 747  * * __ioremap_caller is the same as above but takes an explicit caller
 748  *   reference rather than using __builtin_return_address(0)
 749  *
 750  * * __iounmap, is the low level implementation used by iounmap and cannot
 751  *   be hooked (but can be used by a hook on iounmap)
 752  *
 753  */
 754 extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
 755 extern void __iomem *ioremap_prot(phys_addr_t address, unsigned long size,
 756                                   unsigned long flags);
 757 extern void __iomem *ioremap_wc(phys_addr_t address, unsigned long size);
 758 #define ioremap_nocache(addr, size)     ioremap((addr), (size))
 759 #define ioremap_uc(addr, size)          ioremap((addr), (size))
 760
 761 extern void iounmap(volatile void __iomem *addr);
 762
 763 extern void __iomem *__ioremap(phys_addr_t, unsigned long size,
 764                                unsigned long flags);
 765 extern void __iomem *__ioremap_caller(phys_addr_t, unsigned long size,
 766                                       unsigned long flags, void *caller);
 767
 768 extern void __iounmap(volatile void __iomem *addr);
 769
 770 extern void __iomem * __ioremap_at(phys_addr_t pa, void *ea,
 771                                    unsigned long size, unsigned long flags);
 772 extern void __iounmap_at(void *ea, unsigned long size);
 773
 774 /*
 775  * When CONFIG_PPC_INDIRECT_PIO is set, we use the generic iomap implementation
 776  * which needs some additional definitions here. They basically allow PIO
 777  * space overall to be 1GB. This will work as long as we never try to use
 778  * iomap to map MMIO below 1GB which should be fine on ppc64
 779  */
 780 #define HAVE_ARCH_PIO_SIZE              1
 781 #define PIO_OFFSET                      0x00000000UL
 782 #define PIO_MASK                        (FULL_IO_SIZE - 1)
 783 #define PIO_RESERVED                    (FULL_IO_SIZE)
 784
 785 #define mmio_read16be(addr)             readw_be(addr)
 786 #define mmio_read32be(addr)             readl_be(addr)
 787 #define mmio_write16be(val, addr)       writew_be(val, addr)
 788 #define mmio_write32be(val, addr)       writel_be(val, addr)
 789 #define mmio_insb(addr, dst, count)     readsb(addr, dst, count)
 790 #define mmio_insw(addr, dst, count)     readsw(addr, dst, count)
 791 #define mmio_insl(addr, dst, count)     readsl(addr, dst, count)
 792 #define mmio_outsb(addr, src, count)    writesb(addr, src, count)
 793 #define mmio_outsw(addr, src, count)    writesw(addr, src, count)
 794 #define mmio_outsl(addr, src, count)    writesl(addr, src, count)
 795
 796 /**
 797  *      virt_to_phys    -       map virtual addresses to physical
 798  *      @address: address to remap
 799  *
 800  *      The returned physical address is the physical (CPU) mapping for
 801  *      the memory address given. It is only valid to use this function on
 802  *      addresses directly mapped or allocated via kmalloc.
 803  *
 804  *      This function does not give bus mappings for DMA transfers. In
 805  *      almost all conceivable cases a device driver should not be using
 806  *      this function
 807  */
 808 static inline unsigned long virt_to_phys(volatile void * address)
 809 {
 810         return __pa((unsigned long)address);
 811 }
 812
 813 /**
 814  *      phys_to_virt    -       map physical address to virtual
 815  *      @address: address to remap
 816  *
 817  *      The returned virtual address is a current CPU mapping for
 818  *      the memory address given. It is only valid to use this function on
 819  *      addresses that have a kernel mapping
 820  *
 821  *      This function does not handle bus mappings for DMA transfers. In
 822  *      almost all conceivable cases a device driver should not be using
 823  *      this function
 824  */
 825 static inline void * phys_to_virt(unsigned long address)
 826 {
 827         return (void *)__va(address);
 828 }
 829
 830 /*
 831  * Change "struct page" to physical address.
 832  */
 833 #define page_to_phys(page)      ((phys_addr_t)page_to_pfn(page) << PAGE_SHIFT)
 834
 835 /*
 836  * 32 bits still uses virt_to_bus() for it's implementation of DMA
 837  * mappings se we have to keep it defined here. We also have some old
 838  * drivers (shame shame shame) that use bus_to_virt() and haven't been
 839  * fixed yet so I need to define it here.
 840  */
 841 #ifdef CONFIG_PPC32
 842
 843 static inline unsigned long virt_to_bus(volatile void * address)
 844 {
 845         if (address == NULL)
 846                 return 0;
 847         return __pa(address) + PCI_DRAM_OFFSET;
 848 }
 849
 850 static inline void * bus_to_virt(unsigned long address)
 851 {
 852         if (address == 0)
 853                 return NULL;
 854         return __va(address - PCI_DRAM_OFFSET);
 855 }
 856
 857 #define page_to_bus(page)       (page_to_phys(page) + PCI_DRAM_OFFSET)
 858
 859 #endif /* CONFIG_PPC32 */
 860
 861 /* access ports */
 862 #define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) |  (_v))
 863 #define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))
 864
 865 #define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) |  (_v))
 866 #define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v))
 867
 868 #define setbits8(_addr, _v) out_8((_addr), in_8(_addr) |  (_v))
 869 #define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v))
 870
 871 /* Clear and set bits in one shot.  These macros can be used to clear and
 872  * set multiple bits in a register using a single read-modify-write.  These
 873  * macros can also be used to set a multiple-bit bit pattern using a mask,
 874  * by specifying the mask in the 'clear' parameter and the new bit pattern
 875  * in the 'set' parameter.
 876  */
 877
 878 #define clrsetbits(type, addr, clear, set) \
 879         out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
 880
 881 #ifdef __powerpc64__
 882 #define clrsetbits_be64(addr, clear, set) clrsetbits(be64, addr, clear, set)
 883 #define clrsetbits_le64(addr, clear, set) clrsetbits(le64, addr, clear, set)
 884 #endif
 885
 886 #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
 887 #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
 888
 889 #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
 890 #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
 891
 892 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
 893
 894 #endif /* __KERNEL__ */
 895
 896 #endif /* _ASM_POWERPC_IO_H */