x86/mm/pat: Don't report PAT on CPUs that don't support it
[linux/fpc-iii.git] / arch / powerpc / include / asm / mce.h
blobed62efe01e49ed1a2e37c6bbd6efbf41fed3e925
1 /*
2 * Machine check exception header file.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 * Copyright 2013 IBM Corporation
19 * Author: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
22 #ifndef __ASM_PPC64_MCE_H__
23 #define __ASM_PPC64_MCE_H__
25 #include <linux/bitops.h>
28 * Machine Check bits on power7 and power8
30 #define P7_SRR1_MC_LOADSTORE(srr1) ((srr1) & PPC_BIT(42)) /* P8 too */
32 /* SRR1 bits for machine check (On Power7 and Power8) */
33 #define P7_SRR1_MC_IFETCH(srr1) ((srr1) & PPC_BITMASK(43, 45)) /* P8 too */
35 #define P7_SRR1_MC_IFETCH_UE (0x1 << PPC_BITLSHIFT(45)) /* P8 too */
36 #define P7_SRR1_MC_IFETCH_SLB_PARITY (0x2 << PPC_BITLSHIFT(45)) /* P8 too */
37 #define P7_SRR1_MC_IFETCH_SLB_MULTIHIT (0x3 << PPC_BITLSHIFT(45)) /* P8 too */
38 #define P7_SRR1_MC_IFETCH_SLB_BOTH (0x4 << PPC_BITLSHIFT(45))
39 #define P7_SRR1_MC_IFETCH_TLB_MULTIHIT (0x5 << PPC_BITLSHIFT(45)) /* P8 too */
40 #define P7_SRR1_MC_IFETCH_UE_TLB_RELOAD (0x6 << PPC_BITLSHIFT(45)) /* P8 too */
41 #define P7_SRR1_MC_IFETCH_UE_IFU_INTERNAL (0x7 << PPC_BITLSHIFT(45))
43 /* SRR1 bits for machine check (On Power8) */
44 #define P8_SRR1_MC_IFETCH_ERAT_MULTIHIT (0x4 << PPC_BITLSHIFT(45))
46 /* DSISR bits for machine check (On Power7 and Power8) */
47 #define P7_DSISR_MC_UE (PPC_BIT(48)) /* P8 too */
48 #define P7_DSISR_MC_UE_TABLEWALK (PPC_BIT(49)) /* P8 too */
49 #define P7_DSISR_MC_ERAT_MULTIHIT (PPC_BIT(52)) /* P8 too */
50 #define P7_DSISR_MC_TLB_MULTIHIT_MFTLB (PPC_BIT(53)) /* P8 too */
51 #define P7_DSISR_MC_SLB_PARITY_MFSLB (PPC_BIT(55)) /* P8 too */
52 #define P7_DSISR_MC_SLB_MULTIHIT (PPC_BIT(56)) /* P8 too */
53 #define P7_DSISR_MC_SLB_MULTIHIT_PARITY (PPC_BIT(57)) /* P8 too */
56 * DSISR bits for machine check (Power8) in addition to above.
57 * Secondary DERAT Multihit
59 #define P8_DSISR_MC_ERAT_MULTIHIT_SEC (PPC_BIT(54))
61 /* SLB error bits */
62 #define P7_DSISR_MC_SLB_ERRORS (P7_DSISR_MC_ERAT_MULTIHIT | \
63 P7_DSISR_MC_SLB_PARITY_MFSLB | \
64 P7_DSISR_MC_SLB_MULTIHIT | \
65 P7_DSISR_MC_SLB_MULTIHIT_PARITY)
67 #define P8_DSISR_MC_SLB_ERRORS (P7_DSISR_MC_SLB_ERRORS | \
68 P8_DSISR_MC_ERAT_MULTIHIT_SEC)
71 * Machine Check bits on power9
73 #define P9_SRR1_MC_LOADSTORE(srr1) (((srr1) >> PPC_BITLSHIFT(42)) & 1)
75 #define P9_SRR1_MC_IFETCH(srr1) ( \
76 PPC_BITEXTRACT(srr1, 45, 0) | \
77 PPC_BITEXTRACT(srr1, 44, 1) | \
78 PPC_BITEXTRACT(srr1, 43, 2) | \
79 PPC_BITEXTRACT(srr1, 36, 3) )
81 /* 0 is reserved */
82 #define P9_SRR1_MC_IFETCH_UE 1
83 #define P9_SRR1_MC_IFETCH_SLB_PARITY 2
84 #define P9_SRR1_MC_IFETCH_SLB_MULTIHIT 3
85 #define P9_SRR1_MC_IFETCH_ERAT_MULTIHIT 4
86 #define P9_SRR1_MC_IFETCH_TLB_MULTIHIT 5
87 #define P9_SRR1_MC_IFETCH_UE_TLB_RELOAD 6
88 /* 7 is reserved */
89 #define P9_SRR1_MC_IFETCH_LINK_TIMEOUT 8
90 #define P9_SRR1_MC_IFETCH_LINK_TABLEWALK_TIMEOUT 9
91 /* 10 ? */
92 #define P9_SRR1_MC_IFETCH_RA 11
93 #define P9_SRR1_MC_IFETCH_RA_TABLEWALK 12
94 #define P9_SRR1_MC_IFETCH_RA_ASYNC_STORE 13
95 #define P9_SRR1_MC_IFETCH_LINK_ASYNC_STORE_TIMEOUT 14
96 #define P9_SRR1_MC_IFETCH_RA_TABLEWALK_FOREIGN 15
98 /* DSISR bits for machine check (On Power9) */
99 #define P9_DSISR_MC_UE (PPC_BIT(48))
100 #define P9_DSISR_MC_UE_TABLEWALK (PPC_BIT(49))
101 #define P9_DSISR_MC_LINK_LOAD_TIMEOUT (PPC_BIT(50))
102 #define P9_DSISR_MC_LINK_TABLEWALK_TIMEOUT (PPC_BIT(51))
103 #define P9_DSISR_MC_ERAT_MULTIHIT (PPC_BIT(52))
104 #define P9_DSISR_MC_TLB_MULTIHIT_MFTLB (PPC_BIT(53))
105 #define P9_DSISR_MC_USER_TLBIE (PPC_BIT(54))
106 #define P9_DSISR_MC_SLB_PARITY_MFSLB (PPC_BIT(55))
107 #define P9_DSISR_MC_SLB_MULTIHIT_MFSLB (PPC_BIT(56))
108 #define P9_DSISR_MC_RA_LOAD (PPC_BIT(57))
109 #define P9_DSISR_MC_RA_TABLEWALK (PPC_BIT(58))
110 #define P9_DSISR_MC_RA_TABLEWALK_FOREIGN (PPC_BIT(59))
111 #define P9_DSISR_MC_RA_FOREIGN (PPC_BIT(60))
113 /* SLB error bits */
114 #define P9_DSISR_MC_SLB_ERRORS (P9_DSISR_MC_ERAT_MULTIHIT | \
115 P9_DSISR_MC_SLB_PARITY_MFSLB | \
116 P9_DSISR_MC_SLB_MULTIHIT_MFSLB)
118 enum MCE_Version {
119 MCE_V1 = 1,
122 enum MCE_Severity {
123 MCE_SEV_NO_ERROR = 0,
124 MCE_SEV_WARNING = 1,
125 MCE_SEV_ERROR_SYNC = 2,
126 MCE_SEV_FATAL = 3,
129 enum MCE_Disposition {
130 MCE_DISPOSITION_RECOVERED = 0,
131 MCE_DISPOSITION_NOT_RECOVERED = 1,
134 enum MCE_Initiator {
135 MCE_INITIATOR_UNKNOWN = 0,
136 MCE_INITIATOR_CPU = 1,
139 enum MCE_ErrorType {
140 MCE_ERROR_TYPE_UNKNOWN = 0,
141 MCE_ERROR_TYPE_UE = 1,
142 MCE_ERROR_TYPE_SLB = 2,
143 MCE_ERROR_TYPE_ERAT = 3,
144 MCE_ERROR_TYPE_TLB = 4,
145 MCE_ERROR_TYPE_USER = 5,
146 MCE_ERROR_TYPE_RA = 6,
147 MCE_ERROR_TYPE_LINK = 7,
150 enum MCE_UeErrorType {
151 MCE_UE_ERROR_INDETERMINATE = 0,
152 MCE_UE_ERROR_IFETCH = 1,
153 MCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH = 2,
154 MCE_UE_ERROR_LOAD_STORE = 3,
155 MCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE = 4,
158 enum MCE_SlbErrorType {
159 MCE_SLB_ERROR_INDETERMINATE = 0,
160 MCE_SLB_ERROR_PARITY = 1,
161 MCE_SLB_ERROR_MULTIHIT = 2,
164 enum MCE_EratErrorType {
165 MCE_ERAT_ERROR_INDETERMINATE = 0,
166 MCE_ERAT_ERROR_PARITY = 1,
167 MCE_ERAT_ERROR_MULTIHIT = 2,
170 enum MCE_TlbErrorType {
171 MCE_TLB_ERROR_INDETERMINATE = 0,
172 MCE_TLB_ERROR_PARITY = 1,
173 MCE_TLB_ERROR_MULTIHIT = 2,
176 enum MCE_UserErrorType {
177 MCE_USER_ERROR_INDETERMINATE = 0,
178 MCE_USER_ERROR_TLBIE = 1,
181 enum MCE_RaErrorType {
182 MCE_RA_ERROR_INDETERMINATE = 0,
183 MCE_RA_ERROR_IFETCH = 1,
184 MCE_RA_ERROR_PAGE_TABLE_WALK_IFETCH = 2,
185 MCE_RA_ERROR_PAGE_TABLE_WALK_IFETCH_FOREIGN = 3,
186 MCE_RA_ERROR_LOAD = 4,
187 MCE_RA_ERROR_STORE = 5,
188 MCE_RA_ERROR_PAGE_TABLE_WALK_LOAD_STORE = 6,
189 MCE_RA_ERROR_PAGE_TABLE_WALK_LOAD_STORE_FOREIGN = 7,
190 MCE_RA_ERROR_LOAD_STORE_FOREIGN = 8,
193 enum MCE_LinkErrorType {
194 MCE_LINK_ERROR_INDETERMINATE = 0,
195 MCE_LINK_ERROR_IFETCH_TIMEOUT = 1,
196 MCE_LINK_ERROR_PAGE_TABLE_WALK_IFETCH_TIMEOUT = 2,
197 MCE_LINK_ERROR_LOAD_TIMEOUT = 3,
198 MCE_LINK_ERROR_STORE_TIMEOUT = 4,
199 MCE_LINK_ERROR_PAGE_TABLE_WALK_LOAD_STORE_TIMEOUT = 5,
202 struct machine_check_event {
203 enum MCE_Version version:8; /* 0x00 */
204 uint8_t in_use; /* 0x01 */
205 enum MCE_Severity severity:8; /* 0x02 */
206 enum MCE_Initiator initiator:8; /* 0x03 */
207 enum MCE_ErrorType error_type:8; /* 0x04 */
208 enum MCE_Disposition disposition:8; /* 0x05 */
209 uint8_t reserved_1[2]; /* 0x06 */
210 uint64_t gpr3; /* 0x08 */
211 uint64_t srr0; /* 0x10 */
212 uint64_t srr1; /* 0x18 */
213 union { /* 0x20 */
214 struct {
215 enum MCE_UeErrorType ue_error_type:8;
216 uint8_t effective_address_provided;
217 uint8_t physical_address_provided;
218 uint8_t reserved_1[5];
219 uint64_t effective_address;
220 uint64_t physical_address;
221 uint8_t reserved_2[8];
222 } ue_error;
224 struct {
225 enum MCE_SlbErrorType slb_error_type:8;
226 uint8_t effective_address_provided;
227 uint8_t reserved_1[6];
228 uint64_t effective_address;
229 uint8_t reserved_2[16];
230 } slb_error;
232 struct {
233 enum MCE_EratErrorType erat_error_type:8;
234 uint8_t effective_address_provided;
235 uint8_t reserved_1[6];
236 uint64_t effective_address;
237 uint8_t reserved_2[16];
238 } erat_error;
240 struct {
241 enum MCE_TlbErrorType tlb_error_type:8;
242 uint8_t effective_address_provided;
243 uint8_t reserved_1[6];
244 uint64_t effective_address;
245 uint8_t reserved_2[16];
246 } tlb_error;
248 struct {
249 enum MCE_UserErrorType user_error_type:8;
250 uint8_t effective_address_provided;
251 uint8_t reserved_1[6];
252 uint64_t effective_address;
253 uint8_t reserved_2[16];
254 } user_error;
256 struct {
257 enum MCE_RaErrorType ra_error_type:8;
258 uint8_t effective_address_provided;
259 uint8_t reserved_1[6];
260 uint64_t effective_address;
261 uint8_t reserved_2[16];
262 } ra_error;
264 struct {
265 enum MCE_LinkErrorType link_error_type:8;
266 uint8_t effective_address_provided;
267 uint8_t reserved_1[6];
268 uint64_t effective_address;
269 uint8_t reserved_2[16];
270 } link_error;
271 } u;
274 struct mce_error_info {
275 enum MCE_ErrorType error_type:8;
276 union {
277 enum MCE_UeErrorType ue_error_type:8;
278 enum MCE_SlbErrorType slb_error_type:8;
279 enum MCE_EratErrorType erat_error_type:8;
280 enum MCE_TlbErrorType tlb_error_type:8;
281 enum MCE_UserErrorType user_error_type:8;
282 enum MCE_RaErrorType ra_error_type:8;
283 enum MCE_LinkErrorType link_error_type:8;
284 } u;
285 enum MCE_Severity severity:8;
286 enum MCE_Initiator initiator:8;
289 #define MAX_MC_EVT 100
291 /* Release flags for get_mce_event() */
292 #define MCE_EVENT_RELEASE true
293 #define MCE_EVENT_DONTRELEASE false
295 extern void save_mce_event(struct pt_regs *regs, long handled,
296 struct mce_error_info *mce_err, uint64_t nip,
297 uint64_t addr);
298 extern int get_mce_event(struct machine_check_event *mce, bool release);
299 extern void release_mce_event(void);
300 extern void machine_check_queue_event(void);
301 extern void machine_check_print_event_info(struct machine_check_event *evt);
302 extern uint64_t get_mce_fault_addr(struct machine_check_event *evt);
304 #endif /* __ASM_PPC64_MCE_H__ */