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x86/mm/pat: Don't report PAT on CPUs that don't support it
[linux/fpc-iii.git] / arch / powerpc / include / asm / opal-api.h
bloba0aa285869b58503dcfa99e2e0d72040b723f1f3
1 /*
2 * OPAL API definitions.
3 *
4 * Copyright 2011-2015 IBM Corp.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12 #ifndef __OPAL_API_H
13 #define __OPAL_API_H
14
15 /****** OPAL APIs ******/
16
17 /* Return codes */
18 #define OPAL_SUCCESS 0
19 #define OPAL_PARAMETER -1
20 #define OPAL_BUSY -2
21 #define OPAL_PARTIAL -3
22 #define OPAL_CONSTRAINED -4
23 #define OPAL_CLOSED -5
24 #define OPAL_HARDWARE -6
25 #define OPAL_UNSUPPORTED -7
26 #define OPAL_PERMISSION -8
27 #define OPAL_NO_MEM -9
28 #define OPAL_RESOURCE -10
29 #define OPAL_INTERNAL_ERROR -11
30 #define OPAL_BUSY_EVENT -12
31 #define OPAL_HARDWARE_FROZEN -13
32 #define OPAL_WRONG_STATE -14
33 #define OPAL_ASYNC_COMPLETION -15
34 #define OPAL_EMPTY -16
35 #define OPAL_I2C_TIMEOUT -17
36 #define OPAL_I2C_INVALID_CMD -18
37 #define OPAL_I2C_LBUS_PARITY -19
38 #define OPAL_I2C_BKEND_OVERRUN -20
39 #define OPAL_I2C_BKEND_ACCESS -21
40 #define OPAL_I2C_ARBT_LOST -22
41 #define OPAL_I2C_NACK_RCVD -23
42 #define OPAL_I2C_STOP_ERR -24
43
44 /* API Tokens (in r0) */
45 #define OPAL_INVALID_CALL -1
46 #define OPAL_TEST 0
47 #define OPAL_CONSOLE_WRITE 1
48 #define OPAL_CONSOLE_READ 2
49 #define OPAL_RTC_READ 3
50 #define OPAL_RTC_WRITE 4
51 #define OPAL_CEC_POWER_DOWN 5
52 #define OPAL_CEC_REBOOT 6
53 #define OPAL_READ_NVRAM 7
54 #define OPAL_WRITE_NVRAM 8
55 #define OPAL_HANDLE_INTERRUPT 9
56 #define OPAL_POLL_EVENTS 10
57 #define OPAL_PCI_SET_HUB_TCE_MEMORY 11
58 #define OPAL_PCI_SET_PHB_TCE_MEMORY 12
59 #define OPAL_PCI_CONFIG_READ_BYTE 13
60 #define OPAL_PCI_CONFIG_READ_HALF_WORD 14
61 #define OPAL_PCI_CONFIG_READ_WORD 15
62 #define OPAL_PCI_CONFIG_WRITE_BYTE 16
63 #define OPAL_PCI_CONFIG_WRITE_HALF_WORD 17
64 #define OPAL_PCI_CONFIG_WRITE_WORD 18
65 #define OPAL_SET_XIVE 19
66 #define OPAL_GET_XIVE 20
67 #define OPAL_GET_COMPLETION_TOKEN_STATUS 21 /* obsolete */
68 #define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER 22
69 #define OPAL_PCI_EEH_FREEZE_STATUS 23
70 #define OPAL_PCI_SHPC 24
71 #define OPAL_CONSOLE_WRITE_BUFFER_SPACE 25
72 #define OPAL_PCI_EEH_FREEZE_CLEAR 26
73 #define OPAL_PCI_PHB_MMIO_ENABLE 27
74 #define OPAL_PCI_SET_PHB_MEM_WINDOW 28
75 #define OPAL_PCI_MAP_PE_MMIO_WINDOW 29
76 #define OPAL_PCI_SET_PHB_TABLE_MEMORY 30
77 #define OPAL_PCI_SET_PE 31
78 #define OPAL_PCI_SET_PELTV 32
79 #define OPAL_PCI_SET_MVE 33
80 #define OPAL_PCI_SET_MVE_ENABLE 34
81 #define OPAL_PCI_GET_XIVE_REISSUE 35
82 #define OPAL_PCI_SET_XIVE_REISSUE 36
83 #define OPAL_PCI_SET_XIVE_PE 37
84 #define OPAL_GET_XIVE_SOURCE 38
85 #define OPAL_GET_MSI_32 39
86 #define OPAL_GET_MSI_64 40
87 #define OPAL_START_CPU 41
88 #define OPAL_QUERY_CPU_STATUS 42
89 #define OPAL_WRITE_OPPANEL 43 /* unimplemented */
90 #define OPAL_PCI_MAP_PE_DMA_WINDOW 44
91 #define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL 45
92 #define OPAL_PCI_RESET 49
93 #define OPAL_PCI_GET_HUB_DIAG_DATA 50
94 #define OPAL_PCI_GET_PHB_DIAG_DATA 51
95 #define OPAL_PCI_FENCE_PHB 52
96 #define OPAL_PCI_REINIT 53
97 #define OPAL_PCI_MASK_PE_ERROR 54
98 #define OPAL_SET_SLOT_LED_STATUS 55
99 #define OPAL_GET_EPOW_STATUS 56
100 #define OPAL_SET_SYSTEM_ATTENTION_LED 57
101 #define OPAL_RESERVED1 58
102 #define OPAL_RESERVED2 59
103 #define OPAL_PCI_NEXT_ERROR 60
104 #define OPAL_PCI_EEH_FREEZE_STATUS2 61
105 #define OPAL_PCI_POLL 62
106 #define OPAL_PCI_MSI_EOI 63
107 #define OPAL_PCI_GET_PHB_DIAG_DATA2 64
108 #define OPAL_XSCOM_READ 65
109 #define OPAL_XSCOM_WRITE 66
110 #define OPAL_LPC_READ 67
111 #define OPAL_LPC_WRITE 68
112 #define OPAL_RETURN_CPU 69
113 #define OPAL_REINIT_CPUS 70
114 #define OPAL_ELOG_READ 71
115 #define OPAL_ELOG_WRITE 72
116 #define OPAL_ELOG_ACK 73
117 #define OPAL_ELOG_RESEND 74
118 #define OPAL_ELOG_SIZE 75
119 #define OPAL_FLASH_VALIDATE 76
120 #define OPAL_FLASH_MANAGE 77
121 #define OPAL_FLASH_UPDATE 78
122 #define OPAL_RESYNC_TIMEBASE 79
123 #define OPAL_CHECK_TOKEN 80
124 #define OPAL_DUMP_INIT 81
125 #define OPAL_DUMP_INFO 82
126 #define OPAL_DUMP_READ 83
127 #define OPAL_DUMP_ACK 84
128 #define OPAL_GET_MSG 85
129 #define OPAL_CHECK_ASYNC_COMPLETION 86
130 #define OPAL_SYNC_HOST_REBOOT 87
131 #define OPAL_SENSOR_READ 88
132 #define OPAL_GET_PARAM 89
133 #define OPAL_SET_PARAM 90
134 #define OPAL_DUMP_RESEND 91
135 #define OPAL_ELOG_SEND 92 /* Deprecated */
136 #define OPAL_PCI_SET_PHB_CAPI_MODE 93
137 #define OPAL_DUMP_INFO2 94
138 #define OPAL_WRITE_OPPANEL_ASYNC 95
139 #define OPAL_PCI_ERR_INJECT 96
140 #define OPAL_PCI_EEH_FREEZE_SET 97
141 #define OPAL_HANDLE_HMI 98
142 #define OPAL_CONFIG_CPU_IDLE_STATE 99
143 #define OPAL_SLW_SET_REG 100
144 #define OPAL_REGISTER_DUMP_REGION 101
145 #define OPAL_UNREGISTER_DUMP_REGION 102
146 #define OPAL_WRITE_TPO 103
147 #define OPAL_READ_TPO 104
148 #define OPAL_GET_DPO_STATUS 105
149 #define OPAL_OLD_I2C_REQUEST 106 /* Deprecated */
150 #define OPAL_IPMI_SEND 107
151 #define OPAL_IPMI_RECV 108
152 #define OPAL_I2C_REQUEST 109
153 #define OPAL_FLASH_READ 110
154 #define OPAL_FLASH_WRITE 111
155 #define OPAL_FLASH_ERASE 112
156 #define OPAL_PRD_MSG 113
157 #define OPAL_LEDS_GET_INDICATOR 114
158 #define OPAL_LEDS_SET_INDICATOR 115
159 #define OPAL_CEC_REBOOT2 116
160 #define OPAL_CONSOLE_FLUSH 117
161 #define OPAL_GET_DEVICE_TREE 118
162 #define OPAL_PCI_GET_PRESENCE_STATE 119
163 #define OPAL_PCI_GET_POWER_STATE 120
164 #define OPAL_PCI_SET_POWER_STATE 121
165 #define OPAL_INT_GET_XIRR 122
166 #define OPAL_INT_SET_CPPR 123
167 #define OPAL_INT_EOI 124
168 #define OPAL_INT_SET_MFRR 125
169 #define OPAL_PCI_TCE_KILL 126
170 #define OPAL_NMMU_SET_PTCR 127
171 #define OPAL_LAST 127
172
173 /* Device tree flags */
174
175 /*
176 * Flags set in power-mgmt nodes in device tree describing
177 * idle states that are supported in the platform.
178 */
179
180 #define OPAL_PM_TIMEBASE_STOP 0x00000002
181 #define OPAL_PM_LOSE_HYP_CONTEXT 0x00002000
182 #define OPAL_PM_LOSE_FULL_CONTEXT 0x00004000
183 #define OPAL_PM_NAP_ENABLED 0x00010000
184 #define OPAL_PM_SLEEP_ENABLED 0x00020000
185 #define OPAL_PM_WINKLE_ENABLED 0x00040000
186 #define OPAL_PM_SLEEP_ENABLED_ER1 0x00080000 /* with workaround */
187 #define OPAL_PM_STOP_INST_FAST 0x00100000
188 #define OPAL_PM_STOP_INST_DEEP 0x00200000
189
190 /*
191 * OPAL_CONFIG_CPU_IDLE_STATE parameters
192 */
193 #define OPAL_CONFIG_IDLE_FASTSLEEP 1
194 #define OPAL_CONFIG_IDLE_UNDO 0
195 #define OPAL_CONFIG_IDLE_APPLY 1
196
197 #ifndef __ASSEMBLY__
198
199 /* Other enums */
200 enum OpalFreezeState {
201 OPAL_EEH_STOPPED_NOT_FROZEN = 0,
202 OPAL_EEH_STOPPED_MMIO_FREEZE = 1,
203 OPAL_EEH_STOPPED_DMA_FREEZE = 2,
204 OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3,
205 OPAL_EEH_STOPPED_RESET = 4,
206 OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5,
207 OPAL_EEH_STOPPED_PERM_UNAVAIL = 6
208 };
209
210 enum OpalEehFreezeActionToken {
211 OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1,
212 OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2,
213 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3,
214
215 OPAL_EEH_ACTION_SET_FREEZE_MMIO = 1,
216 OPAL_EEH_ACTION_SET_FREEZE_DMA = 2,
217 OPAL_EEH_ACTION_SET_FREEZE_ALL = 3
218 };
219
220 enum OpalPciStatusToken {
221 OPAL_EEH_NO_ERROR = 0,
222 OPAL_EEH_IOC_ERROR = 1,
223 OPAL_EEH_PHB_ERROR = 2,
224 OPAL_EEH_PE_ERROR = 3,
225 OPAL_EEH_PE_MMIO_ERROR = 4,
226 OPAL_EEH_PE_DMA_ERROR = 5
227 };
228
229 enum OpalPciErrorSeverity {
230 OPAL_EEH_SEV_NO_ERROR = 0,
231 OPAL_EEH_SEV_IOC_DEAD = 1,
232 OPAL_EEH_SEV_PHB_DEAD = 2,
233 OPAL_EEH_SEV_PHB_FENCED = 3,
234 OPAL_EEH_SEV_PE_ER = 4,
235 OPAL_EEH_SEV_INF = 5
236 };
237
238 enum OpalErrinjectType {
239 OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR = 0,
240 OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64 = 1,
241 };
242
243 enum OpalErrinjectFunc {
244 /* IOA bus specific errors */
245 OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR = 0,
246 OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_DATA = 1,
247 OPAL_ERR_INJECT_FUNC_IOA_LD_IO_ADDR = 2,
248 OPAL_ERR_INJECT_FUNC_IOA_LD_IO_DATA = 3,
249 OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_ADDR = 4,
250 OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_DATA = 5,
251 OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_ADDR = 6,
252 OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_DATA = 7,
253 OPAL_ERR_INJECT_FUNC_IOA_ST_IO_ADDR = 8,
254 OPAL_ERR_INJECT_FUNC_IOA_ST_IO_DATA = 9,
255 OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_ADDR = 10,
256 OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_DATA = 11,
257 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_ADDR = 12,
258 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_DATA = 13,
259 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_MASTER = 14,
260 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_TARGET = 15,
261 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_ADDR = 16,
262 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_DATA = 17,
263 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_MASTER = 18,
264 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET = 19,
265 };
266
267 enum OpalMmioWindowType {
268 OPAL_M32_WINDOW_TYPE = 1,
269 OPAL_M64_WINDOW_TYPE = 2,
270 OPAL_IO_WINDOW_TYPE = 3
271 };
272
273 enum OpalExceptionHandler {
274 OPAL_MACHINE_CHECK_HANDLER = 1,
275 OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2,
276 OPAL_SOFTPATCH_HANDLER = 3
277 };
278
279 enum OpalPendingState {
280 OPAL_EVENT_OPAL_INTERNAL = 0x1,
281 OPAL_EVENT_NVRAM = 0x2,
282 OPAL_EVENT_RTC = 0x4,
283 OPAL_EVENT_CONSOLE_OUTPUT = 0x8,
284 OPAL_EVENT_CONSOLE_INPUT = 0x10,
285 OPAL_EVENT_ERROR_LOG_AVAIL = 0x20,
286 OPAL_EVENT_ERROR_LOG = 0x40,
287 OPAL_EVENT_EPOW = 0x80,
288 OPAL_EVENT_LED_STATUS = 0x100,
289 OPAL_EVENT_PCI_ERROR = 0x200,
290 OPAL_EVENT_DUMP_AVAIL = 0x400,
291 OPAL_EVENT_MSG_PENDING = 0x800,
292 };
293
294 enum OpalThreadStatus {
295 OPAL_THREAD_INACTIVE = 0x0,
296 OPAL_THREAD_STARTED = 0x1,
297 OPAL_THREAD_UNAVAILABLE = 0x2 /* opal-v3 */
298 };
299
300 enum OpalPciBusCompare {
301 OpalPciBusAny = 0, /* Any bus number match */
302 OpalPciBus3Bits = 2, /* Match top 3 bits of bus number */
303 OpalPciBus4Bits = 3, /* Match top 4 bits of bus number */
304 OpalPciBus5Bits = 4, /* Match top 5 bits of bus number */
305 OpalPciBus6Bits = 5, /* Match top 6 bits of bus number */
306 OpalPciBus7Bits = 6, /* Match top 7 bits of bus number */
307 OpalPciBusAll = 7, /* Match bus number exactly */
308 };
309
310 enum OpalDeviceCompare {
311 OPAL_IGNORE_RID_DEVICE_NUMBER = 0,
312 OPAL_COMPARE_RID_DEVICE_NUMBER = 1
313 };
314
315 enum OpalFuncCompare {
316 OPAL_IGNORE_RID_FUNCTION_NUMBER = 0,
317 OPAL_COMPARE_RID_FUNCTION_NUMBER = 1
318 };
319
320 enum OpalPeAction {
321 OPAL_UNMAP_PE = 0,
322 OPAL_MAP_PE = 1
323 };
324
325 enum OpalPeltvAction {
326 OPAL_REMOVE_PE_FROM_DOMAIN = 0,
327 OPAL_ADD_PE_TO_DOMAIN = 1
328 };
329
330 enum OpalMveEnableAction {
331 OPAL_DISABLE_MVE = 0,
332 OPAL_ENABLE_MVE = 1
333 };
334
335 enum OpalM64Action {
336 OPAL_DISABLE_M64 = 0,
337 OPAL_ENABLE_M64_SPLIT = 1,
338 OPAL_ENABLE_M64_NON_SPLIT = 2
339 };
340
341 enum OpalPciResetScope {
342 OPAL_RESET_PHB_COMPLETE = 1,
343 OPAL_RESET_PCI_LINK = 2,
344 OPAL_RESET_PHB_ERROR = 3,
345 OPAL_RESET_PCI_HOT = 4,
346 OPAL_RESET_PCI_FUNDAMENTAL = 5,
347 OPAL_RESET_PCI_IODA_TABLE = 6
348 };
349
350 enum OpalPciReinitScope {
351 /*
352 * Note: we chose values that do not overlap
353 * OpalPciResetScope as OPAL v2 used the same
354 * enum for both
355 */
356 OPAL_REINIT_PCI_DEV = 1000
357 };
358
359 enum OpalPciResetState {
360 OPAL_DEASSERT_RESET = 0,
361 OPAL_ASSERT_RESET = 1
362 };
363
364 enum OpalPciSlotPresence {
365 OPAL_PCI_SLOT_EMPTY = 0,
366 OPAL_PCI_SLOT_PRESENT = 1
367 };
368
369 enum OpalPciSlotPower {
370 OPAL_PCI_SLOT_POWER_OFF = 0,
371 OPAL_PCI_SLOT_POWER_ON = 1,
372 OPAL_PCI_SLOT_OFFLINE = 2,
373 OPAL_PCI_SLOT_ONLINE = 3
374 };
375
376 enum OpalSlotLedType {
377 OPAL_SLOT_LED_TYPE_ID = 0, /* IDENTIFY LED */
378 OPAL_SLOT_LED_TYPE_FAULT = 1, /* FAULT LED */
379 OPAL_SLOT_LED_TYPE_ATTN = 2, /* System Attention LED */
380 OPAL_SLOT_LED_TYPE_MAX = 3
381 };
382
383 enum OpalSlotLedState {
384 OPAL_SLOT_LED_STATE_OFF = 0, /* LED is OFF */
385 OPAL_SLOT_LED_STATE_ON = 1 /* LED is ON */
386 };
387
388 /*
389 * Address cycle types for LPC accesses. These also correspond
390 * to the content of the first cell of the "reg" property for
391 * device nodes on the LPC bus
392 */
393 enum OpalLPCAddressType {
394 OPAL_LPC_MEM = 0,
395 OPAL_LPC_IO = 1,
396 OPAL_LPC_FW = 2,
397 };
398
399 enum opal_msg_type {
400 OPAL_MSG_ASYNC_COMP = 0, /* params[0] = token, params[1] = rc,
401 * additional params function-specific
402 */
403 OPAL_MSG_MEM_ERR = 1,
404 OPAL_MSG_EPOW = 2,
405 OPAL_MSG_SHUTDOWN = 3, /* params[0] = 1 reboot, 0 shutdown */
406 OPAL_MSG_HMI_EVT = 4,
407 OPAL_MSG_DPO = 5,
408 OPAL_MSG_PRD = 6,
409 OPAL_MSG_OCC = 7,
410 OPAL_MSG_TYPE_MAX,
411 };
412
413 struct opal_msg {
414 __be32 msg_type;
415 __be32 reserved;
416 __be64 params[8];
417 };
418
419 /* System parameter permission */
420 enum OpalSysparamPerm {
421 OPAL_SYSPARAM_READ = 0x1,
422 OPAL_SYSPARAM_WRITE = 0x2,
423 OPAL_SYSPARAM_RW = (OPAL_SYSPARAM_READ | OPAL_SYSPARAM_WRITE),
424 };
425
426 enum {
427 OPAL_IPMI_MSG_FORMAT_VERSION_1 = 1,
428 };
429
430 struct opal_ipmi_msg {
431 uint8_t version;
432 uint8_t netfn;
433 uint8_t cmd;
434 uint8_t data[];
435 };
436
437 /* FSP memory errors handling */
438 enum OpalMemErr_Version {
439 OpalMemErr_V1 = 1,
440 };
441
442 enum OpalMemErrType {
443 OPAL_MEM_ERR_TYPE_RESILIENCE = 0,
444 OPAL_MEM_ERR_TYPE_DYN_DALLOC,
445 };
446
447 /* Memory Reilience error type */
448 enum OpalMemErr_ResilErrType {
449 OPAL_MEM_RESILIENCE_CE = 0,
450 OPAL_MEM_RESILIENCE_UE,
451 OPAL_MEM_RESILIENCE_UE_SCRUB,
452 };
453
454 /* Dynamic Memory Deallocation type */
455 enum OpalMemErr_DynErrType {
456 OPAL_MEM_DYNAMIC_DEALLOC = 0,
457 };
458
459 struct OpalMemoryErrorData {
460 enum OpalMemErr_Version version:8; /* 0x00 */
461 enum OpalMemErrType type:8; /* 0x01 */
462 __be16 flags; /* 0x02 */
463 uint8_t reserved_1[4]; /* 0x04 */
464
465 union {
466 /* Memory Resilience corrected/uncorrected error info */
467 struct {
468 enum OpalMemErr_ResilErrType resil_err_type:8;
469 uint8_t reserved_1[7];
470 __be64 physical_address_start;
471 __be64 physical_address_end;
472 } resilience;
473 /* Dynamic memory deallocation error info */
474 struct {
475 enum OpalMemErr_DynErrType dyn_err_type:8;
476 uint8_t reserved_1[7];
477 __be64 physical_address_start;
478 __be64 physical_address_end;
479 } dyn_dealloc;
480 } u;
481 };
482
483 /* HMI interrupt event */
484 enum OpalHMI_Version {
485 OpalHMIEvt_V1 = 1,
486 OpalHMIEvt_V2 = 2,
487 };
488
489 enum OpalHMI_Severity {
490 OpalHMI_SEV_NO_ERROR = 0,
491 OpalHMI_SEV_WARNING = 1,
492 OpalHMI_SEV_ERROR_SYNC = 2,
493 OpalHMI_SEV_FATAL = 3,
494 };
495
496 enum OpalHMI_Disposition {
497 OpalHMI_DISPOSITION_RECOVERED = 0,
498 OpalHMI_DISPOSITION_NOT_RECOVERED = 1,
499 };
500
501 enum OpalHMI_ErrType {
502 OpalHMI_ERROR_MALFUNC_ALERT = 0,
503 OpalHMI_ERROR_PROC_RECOV_DONE,
504 OpalHMI_ERROR_PROC_RECOV_DONE_AGAIN,
505 OpalHMI_ERROR_PROC_RECOV_MASKED,
506 OpalHMI_ERROR_TFAC,
507 OpalHMI_ERROR_TFMR_PARITY,
508 OpalHMI_ERROR_HA_OVERFLOW_WARN,
509 OpalHMI_ERROR_XSCOM_FAIL,
510 OpalHMI_ERROR_XSCOM_DONE,
511 OpalHMI_ERROR_SCOM_FIR,
512 OpalHMI_ERROR_DEBUG_TRIG_FIR,
513 OpalHMI_ERROR_HYP_RESOURCE,
514 OpalHMI_ERROR_CAPP_RECOVERY,
515 };
516
517 enum OpalHMI_XstopType {
518 CHECKSTOP_TYPE_UNKNOWN = 0,
519 CHECKSTOP_TYPE_CORE = 1,
520 CHECKSTOP_TYPE_NX = 2,
521 };
522
523 enum OpalHMI_CoreXstopReason {
524 CORE_CHECKSTOP_IFU_REGFILE = 0x00000001,
525 CORE_CHECKSTOP_IFU_LOGIC = 0x00000002,
526 CORE_CHECKSTOP_PC_DURING_RECOV = 0x00000004,
527 CORE_CHECKSTOP_ISU_REGFILE = 0x00000008,
528 CORE_CHECKSTOP_ISU_LOGIC = 0x00000010,
529 CORE_CHECKSTOP_FXU_LOGIC = 0x00000020,
530 CORE_CHECKSTOP_VSU_LOGIC = 0x00000040,
531 CORE_CHECKSTOP_PC_RECOV_IN_MAINT_MODE = 0x00000080,
532 CORE_CHECKSTOP_LSU_REGFILE = 0x00000100,
533 CORE_CHECKSTOP_PC_FWD_PROGRESS = 0x00000200,
534 CORE_CHECKSTOP_LSU_LOGIC = 0x00000400,
535 CORE_CHECKSTOP_PC_LOGIC = 0x00000800,
536 CORE_CHECKSTOP_PC_HYP_RESOURCE = 0x00001000,
537 CORE_CHECKSTOP_PC_HANG_RECOV_FAILED = 0x00002000,
538 CORE_CHECKSTOP_PC_AMBI_HANG_DETECTED = 0x00004000,
539 CORE_CHECKSTOP_PC_DEBUG_TRIG_ERR_INJ = 0x00008000,
540 CORE_CHECKSTOP_PC_SPRD_HYP_ERR_INJ = 0x00010000,
541 };
542
543 enum OpalHMI_NestAccelXstopReason {
544 NX_CHECKSTOP_SHM_INVAL_STATE_ERR = 0x00000001,
545 NX_CHECKSTOP_DMA_INVAL_STATE_ERR_1 = 0x00000002,
546 NX_CHECKSTOP_DMA_INVAL_STATE_ERR_2 = 0x00000004,
547 NX_CHECKSTOP_DMA_CH0_INVAL_STATE_ERR = 0x00000008,
548 NX_CHECKSTOP_DMA_CH1_INVAL_STATE_ERR = 0x00000010,
549 NX_CHECKSTOP_DMA_CH2_INVAL_STATE_ERR = 0x00000020,
550 NX_CHECKSTOP_DMA_CH3_INVAL_STATE_ERR = 0x00000040,
551 NX_CHECKSTOP_DMA_CH4_INVAL_STATE_ERR = 0x00000080,
552 NX_CHECKSTOP_DMA_CH5_INVAL_STATE_ERR = 0x00000100,
553 NX_CHECKSTOP_DMA_CH6_INVAL_STATE_ERR = 0x00000200,
554 NX_CHECKSTOP_DMA_CH7_INVAL_STATE_ERR = 0x00000400,
555 NX_CHECKSTOP_DMA_CRB_UE = 0x00000800,
556 NX_CHECKSTOP_DMA_CRB_SUE = 0x00001000,
557 NX_CHECKSTOP_PBI_ISN_UE = 0x00002000,
558 };
559
560 struct OpalHMIEvent {
561 uint8_t version; /* 0x00 */
562 uint8_t severity; /* 0x01 */
563 uint8_t type; /* 0x02 */
564 uint8_t disposition; /* 0x03 */
565 uint8_t reserved_1[4]; /* 0x04 */
566
567 __be64 hmer;
568 /* TFMR register. Valid only for TFAC and TFMR_PARITY error type. */
569 __be64 tfmr;
570
571 /* version 2 and later */
572 union {
573 /*
574 * checkstop info (Core/NX).
575 * Valid for OpalHMI_ERROR_MALFUNC_ALERT.
576 */
577 struct {
578 uint8_t xstop_type; /* enum OpalHMI_XstopType */
579 uint8_t reserved_1[3];
580 __be32 xstop_reason;
581 union {
582 __be32 pir; /* for CHECKSTOP_TYPE_CORE */
583 __be32 chip_id; /* for CHECKSTOP_TYPE_NX */
584 } u;
585 } xstop_error;
586 } u;
587 };
588
589 enum {
590 OPAL_P7IOC_DIAG_TYPE_NONE = 0,
591 OPAL_P7IOC_DIAG_TYPE_RGC = 1,
592 OPAL_P7IOC_DIAG_TYPE_BI = 2,
593 OPAL_P7IOC_DIAG_TYPE_CI = 3,
594 OPAL_P7IOC_DIAG_TYPE_MISC = 4,
595 OPAL_P7IOC_DIAG_TYPE_I2C = 5,
596 OPAL_P7IOC_DIAG_TYPE_LAST = 6
597 };
598
599 struct OpalIoP7IOCErrorData {
600 __be16 type;
601
602 /* GEM */
603 __be64 gemXfir;
604 __be64 gemRfir;
605 __be64 gemRirqfir;
606 __be64 gemMask;
607 __be64 gemRwof;
608
609 /* LEM */
610 __be64 lemFir;
611 __be64 lemErrMask;
612 __be64 lemAction0;
613 __be64 lemAction1;
614 __be64 lemWof;
615
616 union {
617 struct OpalIoP7IOCRgcErrorData {
618 __be64 rgcStatus; /* 3E1C10 */
619 __be64 rgcLdcp; /* 3E1C18 */
620 }rgc;
621 struct OpalIoP7IOCBiErrorData {
622 __be64 biLdcp0; /* 3C0100, 3C0118 */
623 __be64 biLdcp1; /* 3C0108, 3C0120 */
624 __be64 biLdcp2; /* 3C0110, 3C0128 */
625 __be64 biFenceStatus; /* 3C0130, 3C0130 */
626
627 uint8_t biDownbound; /* BI Downbound or Upbound */
628 }bi;
629 struct OpalIoP7IOCCiErrorData {
630 __be64 ciPortStatus; /* 3Dn008 */
631 __be64 ciPortLdcp; /* 3Dn010 */
632
633 uint8_t ciPort; /* Index of CI port: 0/1 */
634 }ci;
635 };
636 };
637
638 /**
639 * This structure defines the overlay which will be used to store PHB error
640 * data upon request.
641 */
642 enum {
643 OPAL_PHB_ERROR_DATA_VERSION_1 = 1,
644 };
645
646 enum {
647 OPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1,
648 OPAL_PHB_ERROR_DATA_TYPE_PHB3 = 2
649 };
650
651 enum {
652 OPAL_P7IOC_NUM_PEST_REGS = 128,
653 OPAL_PHB3_NUM_PEST_REGS = 256
654 };
655
656 struct OpalIoPhbErrorCommon {
657 __be32 version;
658 __be32 ioType;
659 __be32 len;
660 };
661
662 struct OpalIoP7IOCPhbErrorData {
663 struct OpalIoPhbErrorCommon common;
664
665 __be32 brdgCtl;
666
667 // P7IOC utl regs
668 __be32 portStatusReg;
669 __be32 rootCmplxStatus;
670 __be32 busAgentStatus;
671
672 // P7IOC cfg regs
673 __be32 deviceStatus;
674 __be32 slotStatus;
675 __be32 linkStatus;
676 __be32 devCmdStatus;
677 __be32 devSecStatus;
678
679 // cfg AER regs
680 __be32 rootErrorStatus;
681 __be32 uncorrErrorStatus;
682 __be32 corrErrorStatus;
683 __be32 tlpHdr1;
684 __be32 tlpHdr2;
685 __be32 tlpHdr3;
686 __be32 tlpHdr4;
687 __be32 sourceId;
688
689 __be32 rsv3;
690
691 // Record data about the call to allocate a buffer.
692 __be64 errorClass;
693 __be64 correlator;
694
695 //P7IOC MMIO Error Regs
696 __be64 p7iocPlssr; // n120
697 __be64 p7iocCsr; // n110
698 __be64 lemFir; // nC00
699 __be64 lemErrorMask; // nC18
700 __be64 lemWOF; // nC40
701 __be64 phbErrorStatus; // nC80
702 __be64 phbFirstErrorStatus; // nC88
703 __be64 phbErrorLog0; // nCC0
704 __be64 phbErrorLog1; // nCC8
705 __be64 mmioErrorStatus; // nD00
706 __be64 mmioFirstErrorStatus; // nD08
707 __be64 mmioErrorLog0; // nD40
708 __be64 mmioErrorLog1; // nD48
709 __be64 dma0ErrorStatus; // nD80
710 __be64 dma0FirstErrorStatus; // nD88
711 __be64 dma0ErrorLog0; // nDC0
712 __be64 dma0ErrorLog1; // nDC8
713 __be64 dma1ErrorStatus; // nE00
714 __be64 dma1FirstErrorStatus; // nE08
715 __be64 dma1ErrorLog0; // nE40
716 __be64 dma1ErrorLog1; // nE48
717 __be64 pestA[OPAL_P7IOC_NUM_PEST_REGS];
718 __be64 pestB[OPAL_P7IOC_NUM_PEST_REGS];
719 };
720
721 struct OpalIoPhb3ErrorData {
722 struct OpalIoPhbErrorCommon common;
723
724 __be32 brdgCtl;
725
726 /* PHB3 UTL regs */
727 __be32 portStatusReg;
728 __be32 rootCmplxStatus;
729 __be32 busAgentStatus;
730
731 /* PHB3 cfg regs */
732 __be32 deviceStatus;
733 __be32 slotStatus;
734 __be32 linkStatus;
735 __be32 devCmdStatus;
736 __be32 devSecStatus;
737
738 /* cfg AER regs */
739 __be32 rootErrorStatus;
740 __be32 uncorrErrorStatus;
741 __be32 corrErrorStatus;
742 __be32 tlpHdr1;
743 __be32 tlpHdr2;
744 __be32 tlpHdr3;
745 __be32 tlpHdr4;
746 __be32 sourceId;
747
748 __be32 rsv3;
749
750 /* Record data about the call to allocate a buffer */
751 __be64 errorClass;
752 __be64 correlator;
753
754 /* PHB3 MMIO Error Regs */
755 __be64 nFir; /* 000 */
756 __be64 nFirMask; /* 003 */
757 __be64 nFirWOF; /* 008 */
758 __be64 phbPlssr; /* 120 */
759 __be64 phbCsr; /* 110 */
760 __be64 lemFir; /* C00 */
761 __be64 lemErrorMask; /* C18 */
762 __be64 lemWOF; /* C40 */
763 __be64 phbErrorStatus; /* C80 */
764 __be64 phbFirstErrorStatus; /* C88 */
765 __be64 phbErrorLog0; /* CC0 */
766 __be64 phbErrorLog1; /* CC8 */
767 __be64 mmioErrorStatus; /* D00 */
768 __be64 mmioFirstErrorStatus; /* D08 */
769 __be64 mmioErrorLog0; /* D40 */
770 __be64 mmioErrorLog1; /* D48 */
771 __be64 dma0ErrorStatus; /* D80 */
772 __be64 dma0FirstErrorStatus; /* D88 */
773 __be64 dma0ErrorLog0; /* DC0 */
774 __be64 dma0ErrorLog1; /* DC8 */
775 __be64 dma1ErrorStatus; /* E00 */
776 __be64 dma1FirstErrorStatus; /* E08 */
777 __be64 dma1ErrorLog0; /* E40 */
778 __be64 dma1ErrorLog1; /* E48 */
779 __be64 pestA[OPAL_PHB3_NUM_PEST_REGS];
780 __be64 pestB[OPAL_PHB3_NUM_PEST_REGS];
781 };
782
783 enum {
784 OPAL_REINIT_CPUS_HILE_BE = (1 << 0),
785 OPAL_REINIT_CPUS_HILE_LE = (1 << 1),
786 };
787
788 typedef struct oppanel_line {
789 __be64 line;
790 __be64 line_len;
791 } oppanel_line_t;
792
793 enum opal_prd_msg_type {
794 OPAL_PRD_MSG_TYPE_INIT = 0, /* HBRT --> OPAL */
795 OPAL_PRD_MSG_TYPE_FINI, /* HBRT/kernel --> OPAL */
796 OPAL_PRD_MSG_TYPE_ATTN, /* HBRT <-- OPAL */
797 OPAL_PRD_MSG_TYPE_ATTN_ACK, /* HBRT --> OPAL */
798 OPAL_PRD_MSG_TYPE_OCC_ERROR, /* HBRT <-- OPAL */
799 OPAL_PRD_MSG_TYPE_OCC_RESET, /* HBRT <-- OPAL */
800 };
801
802 struct opal_prd_msg_header {
803 uint8_t type;
804 uint8_t pad[1];
805 __be16 size;
806 };
807
808 struct opal_prd_msg;
809
810 #define OCC_RESET 0
811 #define OCC_LOAD 1
812 #define OCC_THROTTLE 2
813 #define OCC_MAX_THROTTLE_STATUS 5
814
815 struct opal_occ_msg {
816 __be64 type;
817 __be64 chip;
818 __be64 throttle_status;
819 };
820
821 /*
822 * SG entries
823 *
824 * WARNING: The current implementation requires each entry
825 * to represent a block that is 4k aligned *and* each block
826 * size except the last one in the list to be as well.
827 */
828 struct opal_sg_entry {
829 __be64 data;
830 __be64 length;
831 };
832
833 /*
834 * Candidate image SG list.
835 *
836 * length = VER | length
837 */
838 struct opal_sg_list {
839 __be64 length;
840 __be64 next;
841 struct opal_sg_entry entry[];
842 };
843
844 /*
845 * Dump region ID range usable by the OS
846 */
847 #define OPAL_DUMP_REGION_HOST_START 0x80
848 #define OPAL_DUMP_REGION_LOG_BUF 0x80
849 #define OPAL_DUMP_REGION_HOST_END 0xFF
850
851 /* CAPI modes for PHB */
852 enum {
853 OPAL_PHB_CAPI_MODE_PCIE = 0,
854 OPAL_PHB_CAPI_MODE_CAPI = 1,
855 OPAL_PHB_CAPI_MODE_SNOOP_OFF = 2,
856 OPAL_PHB_CAPI_MODE_SNOOP_ON = 3,
857 OPAL_PHB_CAPI_MODE_DMA = 4,
858 };
859
860 /* OPAL I2C request */
861 struct opal_i2c_request {
862 uint8_t type;
863 #define OPAL_I2C_RAW_READ 0
864 #define OPAL_I2C_RAW_WRITE 1
865 #define OPAL_I2C_SM_READ 2
866 #define OPAL_I2C_SM_WRITE 3
867 uint8_t flags;
868 #define OPAL_I2C_ADDR_10 0x01 /* Not supported yet */
869 uint8_t subaddr_sz; /* Max 4 */
870 uint8_t reserved;
871 __be16 addr; /* 7 or 10 bit address */
872 __be16 reserved2;
873 __be32 subaddr; /* Sub-address if any */
874 __be32 size; /* Data size */
875 __be64 buffer_ra; /* Buffer real address */
876 };
877
878 /*
879 * EPOW status sharing (OPAL and the host)
880 *
881 * The host will pass on OPAL, a buffer of length OPAL_SYSEPOW_MAX
882 * with individual elements being 16 bits wide to fetch the system
883 * wide EPOW status. Each element in the buffer will contain the
884 * EPOW status in it's bit representation for a particular EPOW sub
885 * class as defined here. So multiple detailed EPOW status bits
886 * specific for any sub class can be represented in a single buffer
887 * element as it's bit representation.
888 */
889
890 /* System EPOW type */
891 enum OpalSysEpow {
892 OPAL_SYSEPOW_POWER = 0, /* Power EPOW */
893 OPAL_SYSEPOW_TEMP = 1, /* Temperature EPOW */
894 OPAL_SYSEPOW_COOLING = 2, /* Cooling EPOW */
895 OPAL_SYSEPOW_MAX = 3, /* Max EPOW categories */
896 };
897
898 /* Power EPOW */
899 enum OpalSysPower {
900 OPAL_SYSPOWER_UPS = 0x0001, /* System on UPS power */
901 OPAL_SYSPOWER_CHNG = 0x0002, /* System power config change */
902 OPAL_SYSPOWER_FAIL = 0x0004, /* System impending power failure */
903 OPAL_SYSPOWER_INCL = 0x0008, /* System incomplete power */
904 };
905
906 /* Temperature EPOW */
907 enum OpalSysTemp {
908 OPAL_SYSTEMP_AMB = 0x0001, /* System over ambient temperature */
909 OPAL_SYSTEMP_INT = 0x0002, /* System over internal temperature */
910 OPAL_SYSTEMP_HMD = 0x0004, /* System over ambient humidity */
911 };
912
913 /* Cooling EPOW */
914 enum OpalSysCooling {
915 OPAL_SYSCOOL_INSF = 0x0001, /* System insufficient cooling */
916 };
917
918 /* Argument to OPAL_CEC_REBOOT2() */
919 enum {
920 OPAL_REBOOT_NORMAL = 0,
921 OPAL_REBOOT_PLATFORM_ERROR = 1,
922 };
923
924 /* Argument to OPAL_PCI_TCE_KILL */
925 enum {
926 OPAL_PCI_TCE_KILL_PAGES,
927 OPAL_PCI_TCE_KILL_PE,
928 OPAL_PCI_TCE_KILL_ALL,
929 };
930
931 #endif /* __ASSEMBLY__ */
932
933 #endif /* __OPAL_API_H */
Linux with added FPC-III support