arch/powerpc/include/uapi/asm/ptrace.h

   1 /*
   2  * Copyright (C) 2001 PPC64 Team, IBM Corp
   3  *
   4  * This struct defines the way the registers are stored on the
   5  * kernel stack during a system call or other kernel entry.
   6  *
   7  * this should only contain volatile regs
   8  * since we can keep non-volatile in the thread_struct
   9  * should set this up when only volatiles are saved
  10  * by intr code.
  11  *
  12  * Since this is going on the stack, *CARE MUST BE TAKEN* to insure
  13  * that the overall structure is a multiple of 16 bytes in length.
  14  *
  15  * Note that the offsets of the fields in this struct correspond with
  16  * the PT_* values below.  This simplifies arch/powerpc/kernel/ptrace.c.
  17  *
  18  * This program is free software; you can redistribute it and/or
  19  * modify it under the terms of the GNU General Public License
  20  * as published by the Free Software Foundation; either version
  21  * 2 of the License, or (at your option) any later version.
  22  */
  23 #ifndef _UAPI_ASM_POWERPC_PTRACE_H
  24 #define _UAPI_ASM_POWERPC_PTRACE_H
  25
  26
  27 #include <linux/types.h>
  28
  29 #ifndef __ASSEMBLY__
  30
  31 struct pt_regs {
  32         unsigned long gpr[32];
  33         unsigned long nip;
  34         unsigned long msr;
  35         unsigned long orig_gpr3;        /* Used for restarting system calls */
  36         unsigned long ctr;
  37         unsigned long link;
  38         unsigned long xer;
  39         unsigned long ccr;
  40 #ifdef __powerpc64__
  41         unsigned long softe;            /* Soft enabled/disabled */
  42 #else
  43         unsigned long mq;               /* 601 only (not used at present) */
  44                                         /* Used on APUS to hold IPL value. */
  45 #endif
  46         unsigned long trap;             /* Reason for being here */
  47         /* N.B. for critical exceptions on 4xx, the dar and dsisr
  48            fields are overloaded to hold srr0 and srr1. */
  49         unsigned long dar;              /* Fault registers */
  50         unsigned long dsisr;            /* on 4xx/Book-E used for ESR */
  51         unsigned long result;           /* Result of a system call */
  52 };
  53
  54 #endif /* __ASSEMBLY__ */
  55
  56
  57 /*
  58  * Offsets used by 'ptrace' system call interface.
  59  * These can't be changed without breaking binary compatibility
  60  * with MkLinux, etc.
  61  */
  62 #define PT_R0   0
  63 #define PT_R1   1
  64 #define PT_R2   2
  65 #define PT_R3   3
  66 #define PT_R4   4
  67 #define PT_R5   5
  68 #define PT_R6   6
  69 #define PT_R7   7
  70 #define PT_R8   8
  71 #define PT_R9   9
  72 #define PT_R10  10
  73 #define PT_R11  11
  74 #define PT_R12  12
  75 #define PT_R13  13
  76 #define PT_R14  14
  77 #define PT_R15  15
  78 #define PT_R16  16
  79 #define PT_R17  17
  80 #define PT_R18  18
  81 #define PT_R19  19
  82 #define PT_R20  20
  83 #define PT_R21  21
  84 #define PT_R22  22
  85 #define PT_R23  23
  86 #define PT_R24  24
  87 #define PT_R25  25
  88 #define PT_R26  26
  89 #define PT_R27  27
  90 #define PT_R28  28
  91 #define PT_R29  29
  92 #define PT_R30  30
  93 #define PT_R31  31
  94
  95 #define PT_NIP  32
  96 #define PT_MSR  33
  97 #define PT_ORIG_R3 34
  98 #define PT_CTR  35
  99 #define PT_LNK  36
 100 #define PT_XER  37
 101 #define PT_CCR  38
 102 #ifndef __powerpc64__
 103 #define PT_MQ   39
 104 #else
 105 #define PT_SOFTE 39
 106 #endif
 107 #define PT_TRAP 40
 108 #define PT_DAR  41
 109 #define PT_DSISR 42
 110 #define PT_RESULT 43
 111 #define PT_DSCR 44
 112 #define PT_REGS_COUNT 44
 113
 114 #define PT_FPR0 48      /* each FP reg occupies 2 slots in this space */
 115
 116 #ifndef __powerpc64__
 117
 118 #define PT_FPR31 (PT_FPR0 + 2*31)
 119 #define PT_FPSCR (PT_FPR0 + 2*32 + 1)
 120
 121 #else /* __powerpc64__ */
 122
 123 #define PT_FPSCR (PT_FPR0 + 32) /* each FP reg occupies 1 slot in 64-bit space */
 124
 125
 126 #define PT_VR0 82       /* each Vector reg occupies 2 slots in 64-bit */
 127 #define PT_VSCR (PT_VR0 + 32*2 + 1)
 128 #define PT_VRSAVE (PT_VR0 + 33*2)
 129
 130
 131 /*
 132  * Only store first 32 VSRs here. The second 32 VSRs in VR0-31
 133  */
 134 #define PT_VSR0 150     /* each VSR reg occupies 2 slots in 64-bit */
 135 #define PT_VSR31 (PT_VSR0 + 2*31)
 136 #endif /* __powerpc64__ */
 137
 138 /*
 139  * Get/set all the altivec registers v0..v31, vscr, vrsave, in one go.
 140  * The transfer totals 34 quadword.  Quadwords 0-31 contain the
 141  * corresponding vector registers.  Quadword 32 contains the vscr as the
 142  * last word (offset 12) within that quadword.  Quadword 33 contains the
 143  * vrsave as the first word (offset 0) within the quadword.
 144  *
 145  * This definition of the VMX state is compatible with the current PPC32
 146  * ptrace interface.  This allows signal handling and ptrace to use the same
 147  * structures.  This also simplifies the implementation of a bi-arch
 148  * (combined (32- and 64-bit) gdb.
 149  */
 150 #define PTRACE_GETVRREGS        0x12
 151 #define PTRACE_SETVRREGS        0x13
 152
 153 /* Get/set all the upper 32-bits of the SPE registers, accumulator, and
 154  * spefscr, in one go */
 155 #define PTRACE_GETEVRREGS       0x14
 156 #define PTRACE_SETEVRREGS       0x15
 157
 158 /* Get the first 32 128bit VSX registers */
 159 #define PTRACE_GETVSRREGS       0x1b
 160 #define PTRACE_SETVSRREGS       0x1c
 161
 162 /*
 163  * Get or set a debug register. The first 16 are DABR registers and the
 164  * second 16 are IABR registers.
 165  */
 166 #define PTRACE_GET_DEBUGREG     0x19
 167 #define PTRACE_SET_DEBUGREG     0x1a
 168
 169 /* (new) PTRACE requests using the same numbers as x86 and the same
 170  * argument ordering. Additionally, they support more registers too
 171  */
 172 #define PTRACE_GETREGS            0xc
 173 #define PTRACE_SETREGS            0xd
 174 #define PTRACE_GETFPREGS          0xe
 175 #define PTRACE_SETFPREGS          0xf
 176 #define PTRACE_GETREGS64          0x16
 177 #define PTRACE_SETREGS64          0x17
 178
 179 /* Calls to trace a 64bit program from a 32bit program */
 180 #define PPC_PTRACE_PEEKTEXT_3264 0x95
 181 #define PPC_PTRACE_PEEKDATA_3264 0x94
 182 #define PPC_PTRACE_POKETEXT_3264 0x93
 183 #define PPC_PTRACE_POKEDATA_3264 0x92
 184 #define PPC_PTRACE_PEEKUSR_3264  0x91
 185 #define PPC_PTRACE_POKEUSR_3264  0x90
 186
 187 #define PTRACE_SINGLEBLOCK      0x100   /* resume execution until next branch */
 188
 189 #define PPC_PTRACE_GETHWDBGINFO 0x89
 190 #define PPC_PTRACE_SETHWDEBUG   0x88
 191 #define PPC_PTRACE_DELHWDEBUG   0x87
 192
 193 #ifndef __ASSEMBLY__
 194
 195 struct ppc_debug_info {
 196         __u32 version;                  /* Only version 1 exists to date */
 197         __u32 num_instruction_bps;
 198         __u32 num_data_bps;
 199         __u32 num_condition_regs;
 200         __u32 data_bp_alignment;
 201         __u32 sizeof_condition;         /* size of the DVC register */
 202         __u64 features;
 203 };
 204
 205 #endif /* __ASSEMBLY__ */
 206
 207 /*
 208  * features will have bits indication whether there is support for:
 209  */
 210 #define PPC_DEBUG_FEATURE_INSN_BP_RANGE         0x0000000000000001
 211 #define PPC_DEBUG_FEATURE_INSN_BP_MASK          0x0000000000000002
 212 #define PPC_DEBUG_FEATURE_DATA_BP_RANGE         0x0000000000000004
 213 #define PPC_DEBUG_FEATURE_DATA_BP_MASK          0x0000000000000008
 214 #define PPC_DEBUG_FEATURE_DATA_BP_DAWR          0x0000000000000010
 215
 216 #ifndef __ASSEMBLY__
 217
 218 struct ppc_hw_breakpoint {
 219         __u32 version;          /* currently, version must be 1 */
 220         __u32 trigger_type;     /* only some combinations allowed */
 221         __u32 addr_mode;        /* address match mode */
 222         __u32 condition_mode;   /* break/watchpoint condition flags */
 223         __u64 addr;             /* break/watchpoint address */
 224         __u64 addr2;            /* range end or mask */
 225         __u64 condition_value;  /* contents of the DVC register */
 226 };
 227
 228 #endif /* __ASSEMBLY__ */
 229
 230 /*
 231  * Trigger Type
 232  */
 233 #define PPC_BREAKPOINT_TRIGGER_EXECUTE  0x00000001
 234 #define PPC_BREAKPOINT_TRIGGER_READ     0x00000002
 235 #define PPC_BREAKPOINT_TRIGGER_WRITE    0x00000004
 236 #define PPC_BREAKPOINT_TRIGGER_RW       \
 237         (PPC_BREAKPOINT_TRIGGER_READ | PPC_BREAKPOINT_TRIGGER_WRITE)
 238
 239 /*
 240  * Address Mode
 241  */
 242 #define PPC_BREAKPOINT_MODE_EXACT               0x00000000
 243 #define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE     0x00000001
 244 #define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE     0x00000002
 245 #define PPC_BREAKPOINT_MODE_MASK                0x00000003
 246
 247 /*
 248  * Condition Mode
 249  */
 250 #define PPC_BREAKPOINT_CONDITION_MODE   0x00000003
 251 #define PPC_BREAKPOINT_CONDITION_NONE   0x00000000
 252 #define PPC_BREAKPOINT_CONDITION_AND    0x00000001
 253 #define PPC_BREAKPOINT_CONDITION_EXACT  PPC_BREAKPOINT_CONDITION_AND
 254 #define PPC_BREAKPOINT_CONDITION_OR     0x00000002
 255 #define PPC_BREAKPOINT_CONDITION_AND_OR 0x00000003
 256 #define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000
 257 #define PPC_BREAKPOINT_CONDITION_BE_SHIFT       16
 258 #define PPC_BREAKPOINT_CONDITION_BE(n)  \
 259         (1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT))
 260
 261 #endif /* _UAPI_ASM_POWERPC_PTRACE_H */