x86/mm/pat: Don't report PAT on CPUs that don't support it
[linux/fpc-iii.git] / arch / sh / drivers / pci / ops-sh5.c
blob45361946460fedd7fa2873a32a828542655aadb8
1 /*
2 * Support functions for the SH5 PCI hardware.
4 * Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
5 * Copyright (C) 2003, 2004 Paul Mundt
6 * Copyright (C) 2004 Richard Curnow
8 * May be copied or modified under the terms of the GNU General Public
9 * License. See linux/COPYING for more information.
11 #include <linux/kernel.h>
12 #include <linux/rwsem.h>
13 #include <linux/smp.h>
14 #include <linux/interrupt.h>
15 #include <linux/init.h>
16 #include <linux/errno.h>
17 #include <linux/pci.h>
18 #include <linux/delay.h>
19 #include <linux/types.h>
20 #include <linux/irq.h>
21 #include <asm/io.h>
22 #include "pci-sh5.h"
24 static int sh5pci_read(struct pci_bus *bus, unsigned int devfn, int where,
25 int size, u32 *val)
27 SH5PCI_WRITE(PAR, CONFIG_CMD(bus, devfn, where));
29 switch (size) {
30 case 1:
31 *val = (u8)SH5PCI_READ_BYTE(PDR + (where & 3));
32 break;
33 case 2:
34 *val = (u16)SH5PCI_READ_SHORT(PDR + (where & 2));
35 break;
36 case 4:
37 *val = SH5PCI_READ(PDR);
38 break;
41 return PCIBIOS_SUCCESSFUL;
44 static int sh5pci_write(struct pci_bus *bus, unsigned int devfn, int where,
45 int size, u32 val)
47 SH5PCI_WRITE(PAR, CONFIG_CMD(bus, devfn, where));
49 switch (size) {
50 case 1:
51 SH5PCI_WRITE_BYTE(PDR + (where & 3), (u8)val);
52 break;
53 case 2:
54 SH5PCI_WRITE_SHORT(PDR + (where & 2), (u16)val);
55 break;
56 case 4:
57 SH5PCI_WRITE(PDR, val);
58 break;
61 return PCIBIOS_SUCCESSFUL;
64 struct pci_ops sh5_pci_ops = {
65 .read = sh5pci_read,
66 .write = sh5pci_write,