x86/mm/pat: Don't report PAT on CPUs that don't support it
[linux/fpc-iii.git] / arch / sparc / include / asm / head_64.h
blobf0700cfeedd7b270fa874aae03c8df6bf862152d
1 #ifndef _SPARC64_HEAD_H
2 #define _SPARC64_HEAD_H
4 #include <asm/pstate.h>
6 /* wrpr %g0, val, %gl */
7 #define SET_GL(val) \
8 .word 0xa1902000 | val
10 /* rdpr %gl, %gN */
11 #define GET_GL_GLOBAL(N) \
12 .word 0x81540000 | (N << 25)
14 #define KERNBASE 0x400000
16 #define PTREGS_OFF (STACK_BIAS + STACKFRAME_SZ)
18 #define RTRAP_PSTATE (PSTATE_TSO|PSTATE_PEF|PSTATE_PRIV|PSTATE_IE)
19 #define RTRAP_PSTATE_IRQOFF (PSTATE_TSO|PSTATE_PEF|PSTATE_PRIV)
20 #define RTRAP_PSTATE_AG_IRQOFF (PSTATE_TSO|PSTATE_PEF|PSTATE_PRIV|PSTATE_AG)
22 #define __CHEETAH_ID 0x003e0014
23 #define __JALAPENO_ID 0x003e0016
24 #define __SERRANO_ID 0x003e0022
26 #define CHEETAH_MANUF 0x003e
27 #define CHEETAH_IMPL 0x0014 /* Ultra-III */
28 #define CHEETAH_PLUS_IMPL 0x0015 /* Ultra-III+ */
29 #define JALAPENO_IMPL 0x0016 /* Ultra-IIIi */
30 #define JAGUAR_IMPL 0x0018 /* Ultra-IV */
31 #define PANTHER_IMPL 0x0019 /* Ultra-IV+ */
32 #define SERRANO_IMPL 0x0022 /* Ultra-IIIi+ */
34 #define BRANCH_IF_SUN4V(tmp1,label) \
35 sethi %hi(is_sun4v), %tmp1; \
36 lduw [%tmp1 + %lo(is_sun4v)], %tmp1; \
37 brnz,pn %tmp1, label; \
38 nop
40 #define BRANCH_IF_CHEETAH_BASE(tmp1,tmp2,label) \
41 rdpr %ver, %tmp1; \
42 sethi %hi(__CHEETAH_ID), %tmp2; \
43 srlx %tmp1, 32, %tmp1; \
44 or %tmp2, %lo(__CHEETAH_ID), %tmp2;\
45 cmp %tmp1, %tmp2; \
46 be,pn %icc, label; \
47 nop;
49 #define BRANCH_IF_JALAPENO(tmp1,tmp2,label) \
50 rdpr %ver, %tmp1; \
51 sethi %hi(__JALAPENO_ID), %tmp2; \
52 srlx %tmp1, 32, %tmp1; \
53 or %tmp2, %lo(__JALAPENO_ID), %tmp2;\
54 cmp %tmp1, %tmp2; \
55 be,pn %icc, label; \
56 nop;
58 #define BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(tmp1,tmp2,label) \
59 rdpr %ver, %tmp1; \
60 srlx %tmp1, (32 + 16), %tmp2; \
61 cmp %tmp2, CHEETAH_MANUF; \
62 bne,pt %xcc, 99f; \
63 sllx %tmp1, 16, %tmp1; \
64 srlx %tmp1, (32 + 16), %tmp2; \
65 cmp %tmp2, CHEETAH_PLUS_IMPL; \
66 bgeu,pt %xcc, label; \
67 99: nop;
69 #define BRANCH_IF_ANY_CHEETAH(tmp1,tmp2,label) \
70 rdpr %ver, %tmp1; \
71 srlx %tmp1, (32 + 16), %tmp2; \
72 cmp %tmp2, CHEETAH_MANUF; \
73 bne,pt %xcc, 99f; \
74 sllx %tmp1, 16, %tmp1; \
75 srlx %tmp1, (32 + 16), %tmp2; \
76 cmp %tmp2, CHEETAH_IMPL; \
77 bgeu,pt %xcc, label; \
78 99: nop;
80 #endif /* !(_SPARC64_HEAD_H) */