arch/tile/include/asm/pci.h

   1 /*
   2  * Copyright 2010 Tilera Corporation. All Rights Reserved.
   3  *
   4  *   This program is free software; you can redistribute it and/or
   5  *   modify it under the terms of the GNU General Public License
   6  *   as published by the Free Software Foundation, version 2.
   7  *
   8  *   This program is distributed in the hope that it will be useful, but
   9  *   WITHOUT ANY WARRANTY; without even the implied warranty of
  10  *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  11  *   NON INFRINGEMENT.  See the GNU General Public License for
  12  *   more details.
  13  */
  14
  15 #ifndef _ASM_TILE_PCI_H
  16 #define _ASM_TILE_PCI_H
  17
  18 #include <linux/dma-mapping.h>
  19 #include <linux/pci.h>
  20 #include <asm-generic/pci_iomap.h>
  21
  22 #ifndef __tilegx__
  23
  24 /*
  25  * Structure of a PCI controller (host bridge)
  26  */
  27 struct pci_controller {
  28         int index;              /* PCI domain number */
  29         struct pci_bus *root_bus;
  30
  31         int last_busno;
  32
  33         int hv_cfg_fd[2];       /* config{0,1} fds for this PCIe controller */
  34         int hv_mem_fd;          /* fd to Hypervisor for MMIO operations */
  35
  36         struct pci_ops *ops;
  37
  38         int irq_base;           /* Base IRQ from the Hypervisor */
  39         int plx_gen1;           /* flag for PLX Gen 1 configuration */
  40
  41         /* Address ranges that are routed to this controller/bridge. */
  42         struct resource mem_resources[3];
  43 };
  44
  45 /*
  46  * This flag tells if the platform is TILEmpower that needs
  47  * special configuration for the PLX switch chip.
  48  */
  49 extern int tile_plx_gen1;
  50
  51 static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {}
  52
  53 #define TILE_NUM_PCIE   2
  54
  55 /*
  56  * The hypervisor maps the entirety of CPA-space as bus addresses, so
  57  * bus addresses are physical addresses.  The networking and block
  58  * device layers use this boolean for bounce buffer decisions.
  59  */
  60 #define PCI_DMA_BUS_IS_PHYS     1
  61
  62 /* generic pci stuff */
  63 #include <asm-generic/pci.h>
  64
  65 #else
  66
  67 #include <asm/page.h>
  68 #include <gxio/trio.h>
  69
  70 /**
  71  * We reserve the hugepage-size address range at the top of the 64-bit address
  72  * space to serve as the PCI window, emulating the BAR0 space of an endpoint
  73  * device. This window is used by the chip-to-chip applications running on
  74  * the RC node. The reason for carving out this window is that Mem-Maps that
  75  * back up this window will not overlap with those that map the real physical
  76  * memory.
  77  */
  78 #define PCIE_HOST_BAR0_SIZE             HPAGE_SIZE
  79 #define PCIE_HOST_BAR0_START            HPAGE_MASK
  80
  81 /**
  82  * The first PAGE_SIZE of the above "BAR" window is mapped to the
  83  * gxpci_host_regs structure.
  84  */
  85 #define PCIE_HOST_REGS_SIZE             PAGE_SIZE
  86
  87 /*
  88  * This is the PCI address where the Mem-Map interrupt regions start.
  89  * We use the 2nd to the last huge page of the 64-bit address space.
  90  * The last huge page is used for the rootcomplex "bar", for C2C purpose.
  91  */
  92 #define MEM_MAP_INTR_REGIONS_BASE       (HPAGE_MASK - HPAGE_SIZE)
  93
  94 /*
  95  * Each Mem-Map interrupt region occupies 4KB.
  96  */
  97 #define MEM_MAP_INTR_REGION_SIZE        (1 << TRIO_MAP_MEM_LIM__ADDR_SHIFT)
  98
  99 /*
 100  * Allocate the PCI BAR window right below 4GB.
 101  */
 102 #define TILE_PCI_BAR_WINDOW_TOP         (1ULL << 32)
 103
 104 /*
 105  * Allocate 1GB for the PCI BAR window.
 106  */
 107 #define TILE_PCI_BAR_WINDOW_SIZE        (1 << 30)
 108
 109 /*
 110  * This is the highest bus address targeting the host memory that
 111  * can be generated by legacy PCI devices with 32-bit or less
 112  * DMA capability, dictated by the BAR window size and location.
 113  */
 114 #define TILE_PCI_MAX_DIRECT_DMA_ADDRESS \
 115         (TILE_PCI_BAR_WINDOW_TOP - TILE_PCI_BAR_WINDOW_SIZE - 1)
 116
 117 /*
 118  * We shift the PCI bus range for all the physical memory up by the whole PA
 119  * range. The corresponding CPA of an incoming PCI request will be the PCI
 120  * address minus TILE_PCI_MEM_MAP_BASE_OFFSET. This also implies
 121  * that the 64-bit capable devices will be given DMA addresses as
 122  * the CPA plus TILE_PCI_MEM_MAP_BASE_OFFSET. To support 32-bit
 123  * devices, we create a separate map region that handles the low
 124  * 4GB.
 125  *
 126  * This design lets us avoid the "PCI hole" problem where the host bridge
 127  * won't pass DMA traffic with target addresses that happen to fall within the
 128  * BAR space. This enables us to use all the physical memory for DMA, instead
 129  * of wasting the same amount of physical memory as the BAR window size.
 130  */
 131 #define TILE_PCI_MEM_MAP_BASE_OFFSET    (1ULL << CHIP_PA_WIDTH())
 132
 133 /*
 134  * Start of the PCI memory resource, which starts at the end of the
 135  * maximum system physical RAM address.
 136  */
 137 #define TILE_PCI_MEM_START      (1ULL << CHIP_PA_WIDTH())
 138
 139 /*
 140  * Structure of a PCI controller (host bridge) on Gx.
 141  */
 142 struct pci_controller {
 143
 144         /* Pointer back to the TRIO that this PCIe port is connected to. */
 145         gxio_trio_context_t *trio;
 146         int mac;                /* PCIe mac index on the TRIO shim */
 147         int trio_index;         /* Index of TRIO shim that contains the MAC. */
 148
 149         int pio_mem_index;      /* PIO region index for memory access */
 150
 151 #ifdef CONFIG_TILE_PCI_IO
 152         int pio_io_index;       /* PIO region index for I/O space access */
 153 #endif
 154
 155         /*
 156          * Mem-Map regions for all the memory controllers so that Linux can
 157          * map all of its physical memory space to the PCI bus.
 158          */
 159         int mem_maps[MAX_NUMNODES];
 160
 161         int index;              /* PCI domain number */
 162         struct pci_bus *root_bus;
 163
 164         /* PCI I/O space resource for this controller. */
 165         struct resource io_space;
 166         char io_space_name[32];
 167
 168         /* PCI memory space resource for this controller. */
 169         struct resource mem_space;
 170         char mem_space_name[32];
 171
 172         uint64_t mem_offset;    /* cpu->bus memory mapping offset. */
 173
 174         int first_busno;
 175
 176         struct pci_ops *ops;
 177
 178         /* Table that maps the INTx numbers to Linux irq numbers. */
 179         int irq_intx_table[4];
 180 };
 181
 182 extern struct pci_controller pci_controllers[TILEGX_NUM_TRIO * TILEGX_TRIO_PCIES];
 183 extern gxio_trio_context_t trio_contexts[TILEGX_NUM_TRIO];
 184 extern int num_trio_shims;
 185
 186 extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
 187
 188 /*
 189  * The PCI address space does not equal the physical memory address
 190  * space (we have an IOMMU). The IDE and SCSI device layers use this
 191  * boolean for bounce buffer decisions.
 192  */
 193 #define PCI_DMA_BUS_IS_PHYS     0
 194
 195 #endif /* __tilegx__ */
 196
 197 int __init tile_pci_init(void);
 198 int __init pcibios_init(void);
 199
 200 void pcibios_fixup_bus(struct pci_bus *bus);
 201
 202 #define pci_domain_nr(bus) (((struct pci_controller *)(bus)->sysdata)->index)
 203
 204 /*
 205  * This decides whether to display the domain number in /proc.
 206  */
 207 static inline int pci_proc_domain(struct pci_bus *bus)
 208 {
 209         return 1;
 210 }
 211
 212 /*
 213  * pcibios_assign_all_busses() tells whether or not the bus numbers
 214  * should be reassigned, in case the BIOS didn't do it correctly, or
 215  * in case we don't have a BIOS and we want to let Linux do it.
 216  */
 217 static inline int pcibios_assign_all_busses(void)
 218 {
 219         return 1;
 220 }
 221
 222 #define PCIBIOS_MIN_MEM         0
 223 /* Minimum PCI I/O address, starting at the page boundary. */
 224 #define PCIBIOS_MIN_IO          PAGE_SIZE
 225
 226 /* Use any cpu for PCI. */
 227 #define cpumask_of_pcibus(bus) cpu_online_mask
 228
 229 #endif /* _ASM_TILE_PCI_H */