arch/x86/include/asm/apic.h

   1 #ifndef _ASM_X86_APIC_H
   2 #define _ASM_X86_APIC_H
   3
   4 #include <linux/cpumask.h>
   5
   6 #include <asm/alternative.h>
   7 #include <asm/cpufeature.h>
   8 #include <asm/apicdef.h>
   9 #include <linux/atomic.h>
  10 #include <asm/fixmap.h>
  11 #include <asm/mpspec.h>
  12 #include <asm/msr.h>
  13
  14 #define ARCH_APICTIMER_STOPS_ON_C3      1
  15
  16 /*
  17  * Debugging macros
  18  */
  19 #define APIC_QUIET   0
  20 #define APIC_VERBOSE 1
  21 #define APIC_DEBUG   2
  22
  23 /* Macros for apic_extnmi which controls external NMI masking */
  24 #define APIC_EXTNMI_BSP         0 /* Default */
  25 #define APIC_EXTNMI_ALL         1
  26 #define APIC_EXTNMI_NONE        2
  27
  28 /*
  29  * Define the default level of output to be very little
  30  * This can be turned up by using apic=verbose for more
  31  * information and apic=debug for _lots_ of information.
  32  * apic_verbosity is defined in apic.c
  33  */
  34 #define apic_printk(v, s, a...) do {       \
  35                 if ((v) <= apic_verbosity) \
  36                         printk(s, ##a);    \
  37         } while (0)
  38
  39
  40 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
  41 extern void generic_apic_probe(void);
  42 #else
  43 static inline void generic_apic_probe(void)
  44 {
  45 }
  46 #endif
  47
  48 #ifdef CONFIG_X86_LOCAL_APIC
  49
  50 extern unsigned int apic_verbosity;
  51 extern int local_apic_timer_c2_ok;
  52
  53 extern int disable_apic;
  54 extern unsigned int lapic_timer_frequency;
  55
  56 #ifdef CONFIG_SMP
  57 extern void __inquire_remote_apic(int apicid);
  58 #else /* CONFIG_SMP */
  59 static inline void __inquire_remote_apic(int apicid)
  60 {
  61 }
  62 #endif /* CONFIG_SMP */
  63
  64 static inline void default_inquire_remote_apic(int apicid)
  65 {
  66         if (apic_verbosity >= APIC_DEBUG)
  67                 __inquire_remote_apic(apicid);
  68 }
  69
  70 /*
  71  * With 82489DX we can't rely on apic feature bit
  72  * retrieved via cpuid but still have to deal with
  73  * such an apic chip so we assume that SMP configuration
  74  * is found from MP table (64bit case uses ACPI mostly
  75  * which set smp presence flag as well so we are safe
  76  * to use this helper too).
  77  */
  78 static inline bool apic_from_smp_config(void)
  79 {
  80         return smp_found_config && !disable_apic;
  81 }
  82
  83 /*
  84  * Basic functions accessing APICs.
  85  */
  86 #ifdef CONFIG_PARAVIRT
  87 #include <asm/paravirt.h>
  88 #endif
  89
  90 extern int setup_profiling_timer(unsigned int);
  91
  92 static inline void native_apic_mem_write(u32 reg, u32 v)
  93 {
  94         volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
  95
  96         alternative_io("movl %0, %P1", "xchgl %0, %P1", X86_BUG_11AP,
  97                        ASM_OUTPUT2("=r" (v), "=m" (*addr)),
  98                        ASM_OUTPUT2("0" (v), "m" (*addr)));
  99 }
 100
 101 static inline u32 native_apic_mem_read(u32 reg)
 102 {
 103         return *((volatile u32 *)(APIC_BASE + reg));
 104 }
 105
 106 extern void native_apic_wait_icr_idle(void);
 107 extern u32 native_safe_apic_wait_icr_idle(void);
 108 extern void native_apic_icr_write(u32 low, u32 id);
 109 extern u64 native_apic_icr_read(void);
 110
 111 static inline bool apic_is_x2apic_enabled(void)
 112 {
 113         u64 msr;
 114
 115         if (rdmsrl_safe(MSR_IA32_APICBASE, &msr))
 116                 return false;
 117         return msr & X2APIC_ENABLE;
 118 }
 119
 120 extern void enable_IR_x2apic(void);
 121
 122 extern int get_physical_broadcast(void);
 123
 124 extern int lapic_get_maxlvt(void);
 125 extern void clear_local_APIC(void);
 126 extern void disconnect_bsp_APIC(int virt_wire_setup);
 127 extern void disable_local_APIC(void);
 128 extern void lapic_shutdown(void);
 129 extern void sync_Arb_IDs(void);
 130 extern void init_bsp_APIC(void);
 131 extern void setup_local_APIC(void);
 132 extern void init_apic_mappings(void);
 133 void register_lapic_address(unsigned long address);
 134 extern void setup_boot_APIC_clock(void);
 135 extern void setup_secondary_APIC_clock(void);
 136 extern void lapic_update_tsc_freq(void);
 137 extern int APIC_init_uniprocessor(void);
 138
 139 #ifdef CONFIG_X86_64
 140 static inline int apic_force_enable(unsigned long addr)
 141 {
 142         return -1;
 143 }
 144 #else
 145 extern int apic_force_enable(unsigned long addr);
 146 #endif
 147
 148 extern int apic_bsp_setup(bool upmode);
 149 extern void apic_ap_setup(void);
 150
 151 /*
 152  * On 32bit this is mach-xxx local
 153  */
 154 #ifdef CONFIG_X86_64
 155 extern int apic_is_clustered_box(void);
 156 #else
 157 static inline int apic_is_clustered_box(void)
 158 {
 159         return 0;
 160 }
 161 #endif
 162
 163 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask);
 164
 165 #else /* !CONFIG_X86_LOCAL_APIC */
 166 static inline void lapic_shutdown(void) { }
 167 #define local_apic_timer_c2_ok          1
 168 static inline void init_apic_mappings(void) { }
 169 static inline void disable_local_APIC(void) { }
 170 # define setup_boot_APIC_clock x86_init_noop
 171 # define setup_secondary_APIC_clock x86_init_noop
 172 static inline void lapic_update_tsc_freq(void) { }
 173 #endif /* !CONFIG_X86_LOCAL_APIC */
 174
 175 #ifdef CONFIG_X86_X2APIC
 176 /*
 177  * Make previous memory operations globally visible before
 178  * sending the IPI through x2apic wrmsr. We need a serializing instruction or
 179  * mfence for this.
 180  */
 181 static inline void x2apic_wrmsr_fence(void)
 182 {
 183         asm volatile("mfence" : : : "memory");
 184 }
 185
 186 static inline void native_apic_msr_write(u32 reg, u32 v)
 187 {
 188         if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
 189             reg == APIC_LVR)
 190                 return;
 191
 192         wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
 193 }
 194
 195 static inline void native_apic_msr_eoi_write(u32 reg, u32 v)
 196 {
 197         __wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0);
 198 }
 199
 200 static inline u32 native_apic_msr_read(u32 reg)
 201 {
 202         u64 msr;
 203
 204         if (reg == APIC_DFR)
 205                 return -1;
 206
 207         rdmsrl(APIC_BASE_MSR + (reg >> 4), msr);
 208         return (u32)msr;
 209 }
 210
 211 static inline void native_x2apic_wait_icr_idle(void)
 212 {
 213         /* no need to wait for icr idle in x2apic */
 214         return;
 215 }
 216
 217 static inline u32 native_safe_x2apic_wait_icr_idle(void)
 218 {
 219         /* no need to wait for icr idle in x2apic */
 220         return 0;
 221 }
 222
 223 static inline void native_x2apic_icr_write(u32 low, u32 id)
 224 {
 225         wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
 226 }
 227
 228 static inline u64 native_x2apic_icr_read(void)
 229 {
 230         unsigned long val;
 231
 232         rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
 233         return val;
 234 }
 235
 236 extern int x2apic_mode;
 237 extern int x2apic_phys;
 238 extern void __init check_x2apic(void);
 239 extern void x2apic_setup(void);
 240 static inline int x2apic_enabled(void)
 241 {
 242         return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled();
 243 }
 244
 245 #define x2apic_supported()      (boot_cpu_has(X86_FEATURE_X2APIC))
 246 #else /* !CONFIG_X86_X2APIC */
 247 static inline void check_x2apic(void) { }
 248 static inline void x2apic_setup(void) { }
 249 static inline int x2apic_enabled(void) { return 0; }
 250
 251 #define x2apic_mode             (0)
 252 #define x2apic_supported()      (0)
 253 #endif /* !CONFIG_X86_X2APIC */
 254
 255 #ifdef CONFIG_X86_64
 256 #define SET_APIC_ID(x)          (apic->set_apic_id(x))
 257 #else
 258
 259 #endif
 260
 261 /*
 262  * Copyright 2004 James Cleverdon, IBM.
 263  * Subject to the GNU Public License, v.2
 264  *
 265  * Generic APIC sub-arch data struct.
 266  *
 267  * Hacked for x86-64 by James Cleverdon from i386 architecture code by
 268  * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
 269  * James Cleverdon.
 270  */
 271 struct apic {
 272         char *name;
 273
 274         int (*probe)(void);
 275         int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
 276         int (*apic_id_valid)(int apicid);
 277         int (*apic_id_registered)(void);
 278
 279         u32 irq_delivery_mode;
 280         u32 irq_dest_mode;
 281
 282         const struct cpumask *(*target_cpus)(void);
 283
 284         int disable_esr;
 285
 286         int dest_logical;
 287         unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid);
 288
 289         void (*vector_allocation_domain)(int cpu, struct cpumask *retmask,
 290                                          const struct cpumask *mask);
 291         void (*init_apic_ldr)(void);
 292
 293         void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap);
 294
 295         void (*setup_apic_routing)(void);
 296         int (*cpu_present_to_apicid)(int mps_cpu);
 297         void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap);
 298         int (*check_phys_apicid_present)(int phys_apicid);
 299         int (*phys_pkg_id)(int cpuid_apic, int index_msb);
 300
 301         unsigned int (*get_apic_id)(unsigned long x);
 302         unsigned long (*set_apic_id)(unsigned int id);
 303
 304         int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask,
 305                                       const struct cpumask *andmask,
 306                                       unsigned int *apicid);
 307
 308         /* ipi */
 309         void (*send_IPI)(int cpu, int vector);
 310         void (*send_IPI_mask)(const struct cpumask *mask, int vector);
 311         void (*send_IPI_mask_allbutself)(const struct cpumask *mask,
 312                                          int vector);
 313         void (*send_IPI_allbutself)(int vector);
 314         void (*send_IPI_all)(int vector);
 315         void (*send_IPI_self)(int vector);
 316
 317         /* wakeup_secondary_cpu */
 318         int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);
 319
 320         void (*inquire_remote_apic)(int apicid);
 321
 322         /* apic ops */
 323         u32 (*read)(u32 reg);
 324         void (*write)(u32 reg, u32 v);
 325         /*
 326          * ->eoi_write() has the same signature as ->write().
 327          *
 328          * Drivers can support both ->eoi_write() and ->write() by passing the same
 329          * callback value. Kernel can override ->eoi_write() and fall back
 330          * on write for EOI.
 331          */
 332         void (*eoi_write)(u32 reg, u32 v);
 333         void (*native_eoi_write)(u32 reg, u32 v);
 334         u64 (*icr_read)(void);
 335         void (*icr_write)(u32 low, u32 high);
 336         void (*wait_icr_idle)(void);
 337         u32 (*safe_wait_icr_idle)(void);
 338
 339 #ifdef CONFIG_X86_32
 340         /*
 341          * Called very early during boot from get_smp_config().  It should
 342          * return the logical apicid.  x86_[bios]_cpu_to_apicid is
 343          * initialized before this function is called.
 344          *
 345          * If logical apicid can't be determined that early, the function
 346          * may return BAD_APICID.  Logical apicid will be configured after
 347          * init_apic_ldr() while bringing up CPUs.  Note that NUMA affinity
 348          * won't be applied properly during early boot in this case.
 349          */
 350         int (*x86_32_early_logical_apicid)(int cpu);
 351 #endif
 352 };
 353
 354 /*
 355  * Pointer to the local APIC driver in use on this system (there's
 356  * always just one such driver in use - the kernel decides via an
 357  * early probing process which one it picks - and then sticks to it):
 358  */
 359 extern struct apic *apic;
 360
 361 /*
 362  * APIC drivers are probed based on how they are listed in the .apicdrivers
 363  * section. So the order is important and enforced by the ordering
 364  * of different apic driver files in the Makefile.
 365  *
 366  * For the files having two apic drivers, we use apic_drivers()
 367  * to enforce the order with in them.
 368  */
 369 #define apic_driver(sym)                                        \
 370         static const struct apic *__apicdrivers_##sym __used            \
 371         __aligned(sizeof(struct apic *))                        \
 372         __section(.apicdrivers) = { &sym }
 373
 374 #define apic_drivers(sym1, sym2)                                        \
 375         static struct apic *__apicdrivers_##sym1##sym2[2] __used        \
 376         __aligned(sizeof(struct apic *))                                \
 377         __section(.apicdrivers) = { &sym1, &sym2 }
 378
 379 extern struct apic *__apicdrivers[], *__apicdrivers_end[];
 380
 381 /*
 382  * APIC functionality to boot other CPUs - only used on SMP:
 383  */
 384 #ifdef CONFIG_SMP
 385 extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip);
 386 #endif
 387
 388 #ifdef CONFIG_X86_LOCAL_APIC
 389
 390 static inline u32 apic_read(u32 reg)
 391 {
 392         return apic->read(reg);
 393 }
 394
 395 static inline void apic_write(u32 reg, u32 val)
 396 {
 397         apic->write(reg, val);
 398 }
 399
 400 static inline void apic_eoi(void)
 401 {
 402         apic->eoi_write(APIC_EOI, APIC_EOI_ACK);
 403 }
 404
 405 static inline u64 apic_icr_read(void)
 406 {
 407         return apic->icr_read();
 408 }
 409
 410 static inline void apic_icr_write(u32 low, u32 high)
 411 {
 412         apic->icr_write(low, high);
 413 }
 414
 415 static inline void apic_wait_icr_idle(void)
 416 {
 417         apic->wait_icr_idle();
 418 }
 419
 420 static inline u32 safe_apic_wait_icr_idle(void)
 421 {
 422         return apic->safe_wait_icr_idle();
 423 }
 424
 425 extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v));
 426
 427 #else /* CONFIG_X86_LOCAL_APIC */
 428
 429 static inline u32 apic_read(u32 reg) { return 0; }
 430 static inline void apic_write(u32 reg, u32 val) { }
 431 static inline void apic_eoi(void) { }
 432 static inline u64 apic_icr_read(void) { return 0; }
 433 static inline void apic_icr_write(u32 low, u32 high) { }
 434 static inline void apic_wait_icr_idle(void) { }
 435 static inline u32 safe_apic_wait_icr_idle(void) { return 0; }
 436 static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {}
 437
 438 #endif /* CONFIG_X86_LOCAL_APIC */
 439
 440 static inline void ack_APIC_irq(void)
 441 {
 442         /*
 443          * ack_APIC_irq() actually gets compiled as a single instruction
 444          * ... yummie.
 445          */
 446         apic_eoi();
 447 }
 448
 449 static inline unsigned default_get_apic_id(unsigned long x)
 450 {
 451         unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
 452
 453         if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID))
 454                 return (x >> 24) & 0xFF;
 455         else
 456                 return (x >> 24) & 0x0F;
 457 }
 458
 459 /*
 460  * Warm reset vector position:
 461  */
 462 #define TRAMPOLINE_PHYS_LOW             0x467
 463 #define TRAMPOLINE_PHYS_HIGH            0x469
 464
 465 #ifdef CONFIG_X86_64
 466 extern void apic_send_IPI_self(int vector);
 467
 468 DECLARE_PER_CPU(int, x2apic_extra_bits);
 469
 470 extern int default_cpu_present_to_apicid(int mps_cpu);
 471 extern int default_check_phys_apicid_present(int phys_apicid);
 472 #endif
 473
 474 extern void generic_bigsmp_probe(void);
 475
 476
 477 #ifdef CONFIG_X86_LOCAL_APIC
 478
 479 #include <asm/smp.h>
 480
 481 #define APIC_DFR_VALUE  (APIC_DFR_FLAT)
 482
 483 static inline const struct cpumask *default_target_cpus(void)
 484 {
 485 #ifdef CONFIG_SMP
 486         return cpu_online_mask;
 487 #else
 488         return cpumask_of(0);
 489 #endif
 490 }
 491
 492 static inline const struct cpumask *online_target_cpus(void)
 493 {
 494         return cpu_online_mask;
 495 }
 496
 497 DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid);
 498
 499
 500 static inline unsigned int read_apic_id(void)
 501 {
 502         unsigned int reg;
 503
 504         reg = apic_read(APIC_ID);
 505
 506         return apic->get_apic_id(reg);
 507 }
 508
 509 static inline int default_apic_id_valid(int apicid)
 510 {
 511         return (apicid < 255);
 512 }
 513
 514 extern int default_acpi_madt_oem_check(char *, char *);
 515
 516 extern void default_setup_apic_routing(void);
 517
 518 extern struct apic apic_noop;
 519
 520 #ifdef CONFIG_X86_32
 521
 522 static inline int noop_x86_32_early_logical_apicid(int cpu)
 523 {
 524         return BAD_APICID;
 525 }
 526
 527 /*
 528  * Set up the logical destination ID.
 529  *
 530  * Intel recommends to set DFR, LDR and TPR before enabling
 531  * an APIC.  See e.g. "AP-388 82489DX User's Manual" (Intel
 532  * document number 292116).  So here it goes...
 533  */
 534 extern void default_init_apic_ldr(void);
 535
 536 static inline int default_apic_id_registered(void)
 537 {
 538         return physid_isset(read_apic_id(), phys_cpu_present_map);
 539 }
 540
 541 static inline int default_phys_pkg_id(int cpuid_apic, int index_msb)
 542 {
 543         return cpuid_apic >> index_msb;
 544 }
 545
 546 #endif
 547
 548 static inline int
 549 flat_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
 550                             const struct cpumask *andmask,
 551                             unsigned int *apicid)
 552 {
 553         unsigned long cpu_mask = cpumask_bits(cpumask)[0] &
 554                                  cpumask_bits(andmask)[0] &
 555                                  cpumask_bits(cpu_online_mask)[0] &
 556                                  APIC_ALL_CPUS;
 557
 558         if (likely(cpu_mask)) {
 559                 *apicid = (unsigned int)cpu_mask;
 560                 return 0;
 561         } else {
 562                 return -EINVAL;
 563         }
 564 }
 565
 566 extern int
 567 default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
 568                                const struct cpumask *andmask,
 569                                unsigned int *apicid);
 570
 571 static inline void
 572 flat_vector_allocation_domain(int cpu, struct cpumask *retmask,
 573                               const struct cpumask *mask)
 574 {
 575         /* Careful. Some cpus do not strictly honor the set of cpus
 576          * specified in the interrupt destination when using lowest
 577          * priority interrupt delivery mode.
 578          *
 579          * In particular there was a hyperthreading cpu observed to
 580          * deliver interrupts to the wrong hyperthread when only one
 581          * hyperthread was specified in the interrupt desitination.
 582          */
 583         cpumask_clear(retmask);
 584         cpumask_bits(retmask)[0] = APIC_ALL_CPUS;
 585 }
 586
 587 static inline void
 588 default_vector_allocation_domain(int cpu, struct cpumask *retmask,
 589                                  const struct cpumask *mask)
 590 {
 591         cpumask_copy(retmask, cpumask_of(cpu));
 592 }
 593
 594 static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid)
 595 {
 596         return physid_isset(apicid, *map);
 597 }
 598
 599 static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap)
 600 {
 601         *retmap = *phys_map;
 602 }
 603
 604 static inline int __default_cpu_present_to_apicid(int mps_cpu)
 605 {
 606         if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu))
 607                 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
 608         else
 609                 return BAD_APICID;
 610 }
 611
 612 static inline int
 613 __default_check_phys_apicid_present(int phys_apicid)
 614 {
 615         return physid_isset(phys_apicid, phys_cpu_present_map);
 616 }
 617
 618 #ifdef CONFIG_X86_32
 619 static inline int default_cpu_present_to_apicid(int mps_cpu)
 620 {
 621         return __default_cpu_present_to_apicid(mps_cpu);
 622 }
 623
 624 static inline int
 625 default_check_phys_apicid_present(int phys_apicid)
 626 {
 627         return __default_check_phys_apicid_present(phys_apicid);
 628 }
 629 #else
 630 extern int default_cpu_present_to_apicid(int mps_cpu);
 631 extern int default_check_phys_apicid_present(int phys_apicid);
 632 #endif
 633
 634 #endif /* CONFIG_X86_LOCAL_APIC */
 635 extern void irq_enter(void);
 636 extern void irq_exit(void);
 637
 638 static inline void entering_irq(void)
 639 {
 640         irq_enter();
 641 }
 642
 643 static inline void entering_ack_irq(void)
 644 {
 645         entering_irq();
 646         ack_APIC_irq();
 647 }
 648
 649 static inline void ipi_entering_ack_irq(void)
 650 {
 651         irq_enter();
 652         ack_APIC_irq();
 653 }
 654
 655 static inline void exiting_irq(void)
 656 {
 657         irq_exit();
 658 }
 659
 660 static inline void exiting_ack_irq(void)
 661 {
 662         ack_APIC_irq();
 663         irq_exit();
 664 }
 665
 666 extern void ioapic_zap_locks(void);
 667
 668 #endif /* _ASM_X86_APIC_H */