1 #ifndef _ASM_X86_DESC_H
2 #define _ASM_X86_DESC_H
4 #include <asm/desc_defs.h>
9 #include <linux/percpu.h>
11 static inline void fill_ldt(struct desc_struct
*desc
, const struct user_desc
*info
)
13 desc
->limit0
= info
->limit
& 0x0ffff;
15 desc
->base0
= (info
->base_addr
& 0x0000ffff);
16 desc
->base1
= (info
->base_addr
& 0x00ff0000) >> 16;
18 desc
->type
= (info
->read_exec_only
^ 1) << 1;
19 desc
->type
|= info
->contents
<< 2;
23 desc
->p
= info
->seg_not_present
^ 1;
24 desc
->limit
= (info
->limit
& 0xf0000) >> 16;
25 desc
->avl
= info
->useable
;
26 desc
->d
= info
->seg_32bit
;
27 desc
->g
= info
->limit_in_pages
;
29 desc
->base2
= (info
->base_addr
& 0xff000000) >> 24;
31 * Don't allow setting of the lm bit. It would confuse
32 * user_64bit_mode and would get overridden by sysret anyway.
37 extern struct desc_ptr idt_descr
;
38 extern gate_desc idt_table
[];
39 extern const struct desc_ptr debug_idt_descr
;
40 extern gate_desc debug_idt_table
[];
43 struct desc_struct gdt
[GDT_ENTRIES
];
44 } __attribute__((aligned(PAGE_SIZE
)));
46 DECLARE_PER_CPU_PAGE_ALIGNED(struct gdt_page
, gdt_page
);
48 static inline struct desc_struct
*get_cpu_gdt_table(unsigned int cpu
)
50 return per_cpu(gdt_page
, cpu
).gdt
;
55 static inline void pack_gate(gate_desc
*gate
, unsigned type
, unsigned long func
,
56 unsigned dpl
, unsigned ist
, unsigned seg
)
58 gate
->offset_low
= PTR_LOW(func
);
59 gate
->segment
= __KERNEL_CS
;
66 gate
->offset_middle
= PTR_MIDDLE(func
);
67 gate
->offset_high
= PTR_HIGH(func
);
71 static inline void pack_gate(gate_desc
*gate
, unsigned char type
,
72 unsigned long base
, unsigned dpl
, unsigned flags
,
75 gate
->a
= (seg
<< 16) | (base
& 0xffff);
76 gate
->b
= (base
& 0xffff0000) | (((0x80 | type
| (dpl
<< 5)) & 0xff) << 8);
81 static inline int desc_empty(const void *ptr
)
83 const u32
*desc
= ptr
;
85 return !(desc
[0] | desc
[1]);
88 #ifdef CONFIG_PARAVIRT
89 #include <asm/paravirt.h>
91 #define load_TR_desc() native_load_tr_desc()
92 #define load_gdt(dtr) native_load_gdt(dtr)
93 #define load_idt(dtr) native_load_idt(dtr)
94 #define load_tr(tr) asm volatile("ltr %0"::"m" (tr))
95 #define load_ldt(ldt) asm volatile("lldt %0"::"m" (ldt))
97 #define store_gdt(dtr) native_store_gdt(dtr)
98 #define store_idt(dtr) native_store_idt(dtr)
99 #define store_tr(tr) (tr = native_store_tr())
101 #define load_TLS(t, cpu) native_load_tls(t, cpu)
102 #define set_ldt native_set_ldt
104 #define write_ldt_entry(dt, entry, desc) native_write_ldt_entry(dt, entry, desc)
105 #define write_gdt_entry(dt, entry, desc, type) native_write_gdt_entry(dt, entry, desc, type)
106 #define write_idt_entry(dt, entry, g) native_write_idt_entry(dt, entry, g)
108 static inline void paravirt_alloc_ldt(struct desc_struct
*ldt
, unsigned entries
)
112 static inline void paravirt_free_ldt(struct desc_struct
*ldt
, unsigned entries
)
115 #endif /* CONFIG_PARAVIRT */
117 #define store_ldt(ldt) asm("sldt %0" : "=m"(ldt))
119 static inline void native_write_idt_entry(gate_desc
*idt
, int entry
, const gate_desc
*gate
)
121 memcpy(&idt
[entry
], gate
, sizeof(*gate
));
124 static inline void native_write_ldt_entry(struct desc_struct
*ldt
, int entry
, const void *desc
)
126 memcpy(&ldt
[entry
], desc
, 8);
130 native_write_gdt_entry(struct desc_struct
*gdt
, int entry
, const void *desc
, int type
)
135 case DESC_TSS
: size
= sizeof(tss_desc
); break;
136 case DESC_LDT
: size
= sizeof(ldt_desc
); break;
137 default: size
= sizeof(*gdt
); break;
140 memcpy(&gdt
[entry
], desc
, size
);
143 static inline void pack_descriptor(struct desc_struct
*desc
, unsigned long base
,
144 unsigned long limit
, unsigned char type
,
147 desc
->a
= ((base
& 0xffff) << 16) | (limit
& 0xffff);
148 desc
->b
= (base
& 0xff000000) | ((base
& 0xff0000) >> 16) |
149 (limit
& 0x000f0000) | ((type
& 0xff) << 8) |
150 ((flags
& 0xf) << 20);
155 static inline void set_tssldt_descriptor(void *d
, unsigned long addr
, unsigned type
, unsigned size
)
158 struct ldttss_desc64
*desc
= d
;
160 memset(desc
, 0, sizeof(*desc
));
162 desc
->limit0
= size
& 0xFFFF;
163 desc
->base0
= PTR_LOW(addr
);
164 desc
->base1
= PTR_MIDDLE(addr
) & 0xFF;
167 desc
->limit1
= (size
>> 16) & 0xF;
168 desc
->base2
= (PTR_MIDDLE(addr
) >> 8) & 0xFF;
169 desc
->base3
= PTR_HIGH(addr
);
171 pack_descriptor((struct desc_struct
*)d
, addr
, size
, 0x80 | type
, 0);
175 static inline void __set_tss_desc(unsigned cpu
, unsigned int entry
, void *addr
)
177 struct desc_struct
*d
= get_cpu_gdt_table(cpu
);
180 set_tssldt_descriptor(&tss
, (unsigned long)addr
, DESC_TSS
,
182 write_gdt_entry(d
, entry
, &tss
, DESC_TSS
);
185 #define set_tss_desc(cpu, addr) __set_tss_desc(cpu, GDT_ENTRY_TSS, addr)
187 static inline void native_set_ldt(const void *addr
, unsigned int entries
)
189 if (likely(entries
== 0))
190 asm volatile("lldt %w0"::"q" (0));
192 unsigned cpu
= smp_processor_id();
195 set_tssldt_descriptor(&ldt
, (unsigned long)addr
, DESC_LDT
,
196 entries
* LDT_ENTRY_SIZE
- 1);
197 write_gdt_entry(get_cpu_gdt_table(cpu
), GDT_ENTRY_LDT
,
199 asm volatile("lldt %w0"::"q" (GDT_ENTRY_LDT
*8));
203 static inline void native_load_tr_desc(void)
205 asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS
*8));
208 DECLARE_PER_CPU(bool, __tss_limit_invalid
);
210 static inline void force_reload_TR(void)
212 struct desc_struct
*d
= get_cpu_gdt_table(smp_processor_id());
215 memcpy(&tss
, &d
[GDT_ENTRY_TSS
], sizeof(tss_desc
));
218 * LTR requires an available TSS, and the TSS is currently
219 * busy. Make it be available so that LTR will work.
222 write_gdt_entry(d
, GDT_ENTRY_TSS
, &tss
, DESC_TSS
);
225 this_cpu_write(__tss_limit_invalid
, false);
229 * Call this if you need the TSS limit to be correct, which should be the case
230 * if and only if you have TIF_IO_BITMAP set or you're switching to a task
231 * with TIF_IO_BITMAP set.
233 static inline void refresh_tss_limit(void)
235 DEBUG_LOCKS_WARN_ON(preemptible());
237 if (unlikely(this_cpu_read(__tss_limit_invalid
)))
242 * If you do something evil that corrupts the cached TSS limit (I'm looking
243 * at you, VMX exits), call this function.
245 * The optimization here is that the TSS limit only matters for Linux if the
246 * IO bitmap is in use. If the TSS limit gets forced to its minimum value,
247 * everything works except that IO bitmap will be ignored and all CPL 3 IO
248 * instructions will #GP, which is exactly what we want for normal tasks.
250 static inline void invalidate_tss_limit(void)
252 DEBUG_LOCKS_WARN_ON(preemptible());
254 if (unlikely(test_thread_flag(TIF_IO_BITMAP
)))
257 this_cpu_write(__tss_limit_invalid
, true);
260 static inline void native_load_gdt(const struct desc_ptr
*dtr
)
262 asm volatile("lgdt %0"::"m" (*dtr
));
265 static inline void native_load_idt(const struct desc_ptr
*dtr
)
267 asm volatile("lidt %0"::"m" (*dtr
));
270 static inline void native_store_gdt(struct desc_ptr
*dtr
)
272 asm volatile("sgdt %0":"=m" (*dtr
));
275 static inline void native_store_idt(struct desc_ptr
*dtr
)
277 asm volatile("sidt %0":"=m" (*dtr
));
280 static inline unsigned long native_store_tr(void)
284 asm volatile("str %0":"=r" (tr
));
289 static inline void native_load_tls(struct thread_struct
*t
, unsigned int cpu
)
291 struct desc_struct
*gdt
= get_cpu_gdt_table(cpu
);
294 for (i
= 0; i
< GDT_ENTRY_TLS_ENTRIES
; i
++)
295 gdt
[GDT_ENTRY_TLS_MIN
+ i
] = t
->tls_array
[i
];
298 /* This intentionally ignores lm, since 32-bit apps don't have that field. */
299 #define LDT_empty(info) \
300 ((info)->base_addr == 0 && \
301 (info)->limit == 0 && \
302 (info)->contents == 0 && \
303 (info)->read_exec_only == 1 && \
304 (info)->seg_32bit == 0 && \
305 (info)->limit_in_pages == 0 && \
306 (info)->seg_not_present == 1 && \
307 (info)->useable == 0)
309 /* Lots of programs expect an all-zero user_desc to mean "no segment at all". */
310 static inline bool LDT_zero(const struct user_desc
*info
)
312 return (info
->base_addr
== 0 &&
314 info
->contents
== 0 &&
315 info
->read_exec_only
== 0 &&
316 info
->seg_32bit
== 0 &&
317 info
->limit_in_pages
== 0 &&
318 info
->seg_not_present
== 0 &&
322 static inline void clear_LDT(void)
327 static inline unsigned long get_desc_base(const struct desc_struct
*desc
)
329 return (unsigned)(desc
->base0
| ((desc
->base1
) << 16) | ((desc
->base2
) << 24));
332 static inline void set_desc_base(struct desc_struct
*desc
, unsigned long base
)
334 desc
->base0
= base
& 0xffff;
335 desc
->base1
= (base
>> 16) & 0xff;
336 desc
->base2
= (base
>> 24) & 0xff;
339 static inline unsigned long get_desc_limit(const struct desc_struct
*desc
)
341 return desc
->limit0
| (desc
->limit
<< 16);
344 static inline void set_desc_limit(struct desc_struct
*desc
, unsigned long limit
)
346 desc
->limit0
= limit
& 0xffff;
347 desc
->limit
= (limit
>> 16) & 0xf;
351 static inline void set_nmi_gate(int gate
, void *addr
)
355 pack_gate(&s
, GATE_INTERRUPT
, (unsigned long)addr
, 0, 0, __KERNEL_CS
);
356 write_idt_entry(debug_idt_table
, gate
, &s
);
360 #ifdef CONFIG_TRACING
361 extern struct desc_ptr trace_idt_descr
;
362 extern gate_desc trace_idt_table
[];
363 static inline void write_trace_idt_entry(int entry
, const gate_desc
*gate
)
365 write_idt_entry(trace_idt_table
, entry
, gate
);
368 static inline void _trace_set_gate(int gate
, unsigned type
, void *addr
,
369 unsigned dpl
, unsigned ist
, unsigned seg
)
373 pack_gate(&s
, type
, (unsigned long)addr
, dpl
, ist
, seg
);
375 * does not need to be atomic because it is only done once at
378 write_trace_idt_entry(gate
, &s
);
381 static inline void write_trace_idt_entry(int entry
, const gate_desc
*gate
)
385 #define _trace_set_gate(gate, type, addr, dpl, ist, seg)
388 static inline void _set_gate(int gate
, unsigned type
, void *addr
,
389 unsigned dpl
, unsigned ist
, unsigned seg
)
393 pack_gate(&s
, type
, (unsigned long)addr
, dpl
, ist
, seg
);
395 * does not need to be atomic because it is only done once at
398 write_idt_entry(idt_table
, gate
, &s
);
399 write_trace_idt_entry(gate
, &s
);
403 * This needs to use 'idt_table' rather than 'idt', and
404 * thus use the _nonmapped_ version of the IDT, as the
405 * Pentium F0 0F bugfix can have resulted in the mapped
406 * IDT being write-protected.
408 #define set_intr_gate_notrace(n, addr) \
410 BUG_ON((unsigned)n > 0xFF); \
411 _set_gate(n, GATE_INTERRUPT, (void *)addr, 0, 0, \
415 #define set_intr_gate(n, addr) \
417 set_intr_gate_notrace(n, addr); \
418 _trace_set_gate(n, GATE_INTERRUPT, (void *)trace_##addr,\
419 0, 0, __KERNEL_CS); \
422 extern int first_system_vector
;
423 /* used_vectors is BITMAP for irq is not managed by percpu vector_irq */
424 extern unsigned long used_vectors
[];
426 static inline void alloc_system_vector(int vector
)
428 if (!test_bit(vector
, used_vectors
)) {
429 set_bit(vector
, used_vectors
);
430 if (first_system_vector
> vector
)
431 first_system_vector
= vector
;
437 #define alloc_intr_gate(n, addr) \
439 alloc_system_vector(n); \
440 set_intr_gate(n, addr); \
444 * This routine sets up an interrupt gate at directory privilege level 3.
446 static inline void set_system_intr_gate(unsigned int n
, void *addr
)
448 BUG_ON((unsigned)n
> 0xFF);
449 _set_gate(n
, GATE_INTERRUPT
, addr
, 0x3, 0, __KERNEL_CS
);
452 static inline void set_system_trap_gate(unsigned int n
, void *addr
)
454 BUG_ON((unsigned)n
> 0xFF);
455 _set_gate(n
, GATE_TRAP
, addr
, 0x3, 0, __KERNEL_CS
);
458 static inline void set_trap_gate(unsigned int n
, void *addr
)
460 BUG_ON((unsigned)n
> 0xFF);
461 _set_gate(n
, GATE_TRAP
, addr
, 0, 0, __KERNEL_CS
);
464 static inline void set_task_gate(unsigned int n
, unsigned int gdt_entry
)
466 BUG_ON((unsigned)n
> 0xFF);
467 _set_gate(n
, GATE_TASK
, (void *)0, 0, 0, (gdt_entry
<<3));
470 static inline void set_intr_gate_ist(int n
, void *addr
, unsigned ist
)
472 BUG_ON((unsigned)n
> 0xFF);
473 _set_gate(n
, GATE_INTERRUPT
, addr
, 0, ist
, __KERNEL_CS
);
476 static inline void set_system_intr_gate_ist(int n
, void *addr
, unsigned ist
)
478 BUG_ON((unsigned)n
> 0xFF);
479 _set_gate(n
, GATE_INTERRUPT
, addr
, 0x3, ist
, __KERNEL_CS
);
483 DECLARE_PER_CPU(u32
, debug_idt_ctr
);
484 static inline bool is_debug_idt_enabled(void)
486 if (this_cpu_read(debug_idt_ctr
))
492 static inline void load_debug_idt(void)
494 load_idt((const struct desc_ptr
*)&debug_idt_descr
);
497 static inline bool is_debug_idt_enabled(void)
502 static inline void load_debug_idt(void)
507 #ifdef CONFIG_TRACING
508 extern atomic_t trace_idt_ctr
;
509 static inline bool is_trace_idt_enabled(void)
511 if (atomic_read(&trace_idt_ctr
))
517 static inline void load_trace_idt(void)
519 load_idt((const struct desc_ptr
*)&trace_idt_descr
);
522 static inline bool is_trace_idt_enabled(void)
527 static inline void load_trace_idt(void)
533 * The load_current_idt() must be called with interrupts disabled
534 * to avoid races. That way the IDT will always be set back to the expected
535 * descriptor. It's also called when a CPU is being initialized, and
536 * that doesn't need to disable interrupts, as nothing should be
537 * bothering the CPU then.
539 static inline void load_current_idt(void)
541 if (is_debug_idt_enabled())
543 else if (is_trace_idt_enabled())
546 load_idt((const struct desc_ptr
*)&idt_descr
);
548 #endif /* _ASM_X86_DESC_H */