arch/x86/include/asm/processor.h

   1 #ifndef _ASM_X86_PROCESSOR_H
   2 #define _ASM_X86_PROCESSOR_H
   3
   4 #include <asm/processor-flags.h>
   5
   6 /* Forward declaration, a strange C thing */
   7 struct task_struct;
   8 struct mm_struct;
   9 struct vm86;
  10
  11 #include <asm/math_emu.h>
  12 #include <asm/segment.h>
  13 #include <asm/types.h>
  14 #include <uapi/asm/sigcontext.h>
  15 #include <asm/current.h>
  16 #include <asm/cpufeatures.h>
  17 #include <asm/page.h>
  18 #include <asm/pgtable_types.h>
  19 #include <asm/percpu.h>
  20 #include <asm/msr.h>
  21 #include <asm/desc_defs.h>
  22 #include <asm/nops.h>
  23 #include <asm/special_insns.h>
  24 #include <asm/fpu/types.h>
  25
  26 #include <linux/personality.h>
  27 #include <linux/cache.h>
  28 #include <linux/threads.h>
  29 #include <linux/math64.h>
  30 #include <linux/err.h>
  31 #include <linux/irqflags.h>
  32
  33 /*
  34  * We handle most unaligned accesses in hardware.  On the other hand
  35  * unaligned DMA can be quite expensive on some Nehalem processors.
  36  *
  37  * Based on this we disable the IP header alignment in network drivers.
  38  */
  39 #define NET_IP_ALIGN    0
  40
  41 #define HBP_NUM 4
  42 /*
  43  * Default implementation of macro that returns current
  44  * instruction pointer ("program counter").
  45  */
  46 static inline void *current_text_addr(void)
  47 {
  48         void *pc;
  49
  50         asm volatile("mov $1f, %0; 1:":"=r" (pc));
  51
  52         return pc;
  53 }
  54
  55 /*
  56  * These alignment constraints are for performance in the vSMP case,
  57  * but in the task_struct case we must also meet hardware imposed
  58  * alignment requirements of the FPU state:
  59  */
  60 #ifdef CONFIG_X86_VSMP
  61 # define ARCH_MIN_TASKALIGN             (1 << INTERNODE_CACHE_SHIFT)
  62 # define ARCH_MIN_MMSTRUCT_ALIGN        (1 << INTERNODE_CACHE_SHIFT)
  63 #else
  64 # define ARCH_MIN_TASKALIGN             __alignof__(union fpregs_state)
  65 # define ARCH_MIN_MMSTRUCT_ALIGN        0
  66 #endif
  67
  68 enum tlb_infos {
  69         ENTRIES,
  70         NR_INFO
  71 };
  72
  73 extern u16 __read_mostly tlb_lli_4k[NR_INFO];
  74 extern u16 __read_mostly tlb_lli_2m[NR_INFO];
  75 extern u16 __read_mostly tlb_lli_4m[NR_INFO];
  76 extern u16 __read_mostly tlb_lld_4k[NR_INFO];
  77 extern u16 __read_mostly tlb_lld_2m[NR_INFO];
  78 extern u16 __read_mostly tlb_lld_4m[NR_INFO];
  79 extern u16 __read_mostly tlb_lld_1g[NR_INFO];
  80
  81 /*
  82  *  CPU type and hardware bug flags. Kept separately for each CPU.
  83  *  Members of this structure are referenced in head.S, so think twice
  84  *  before touching them. [mj]
  85  */
  86
  87 struct cpuinfo_x86 {
  88         __u8                    x86;            /* CPU family */
  89         __u8                    x86_vendor;     /* CPU vendor */
  90         __u8                    x86_model;
  91         __u8                    x86_mask;
  92 #ifdef CONFIG_X86_32
  93         char                    wp_works_ok;    /* It doesn't on 386's */
  94
  95         /* Problems on some 486Dx4's and old 386's: */
  96         char                    rfu;
  97         char                    pad0;
  98         char                    pad1;
  99 #else
 100         /* Number of 4K pages in DTLB/ITLB combined(in pages): */
 101         int                     x86_tlbsize;
 102 #endif
 103         __u8                    x86_virt_bits;
 104         __u8                    x86_phys_bits;
 105         /* CPUID returned core id bits: */
 106         __u8                    x86_coreid_bits;
 107         __u8                    cu_id;
 108         /* Max extended CPUID function supported: */
 109         __u32                   extended_cpuid_level;
 110         /* Maximum supported CPUID level, -1=no CPUID: */
 111         int                     cpuid_level;
 112         __u32                   x86_capability[NCAPINTS + NBUGINTS];
 113         char                    x86_vendor_id[16];
 114         char                    x86_model_id[64];
 115         /* in KB - valid for CPUS which support this call: */
 116         int                     x86_cache_size;
 117         int                     x86_cache_alignment;    /* In bytes */
 118         /* Cache QoS architectural values: */
 119         int                     x86_cache_max_rmid;     /* max index */
 120         int                     x86_cache_occ_scale;    /* scale to bytes */
 121         int                     x86_power;
 122         unsigned long           loops_per_jiffy;
 123         /* cpuid returned max cores value: */
 124         u16                      x86_max_cores;
 125         u16                     apicid;
 126         u16                     initial_apicid;
 127         u16                     x86_clflush_size;
 128         /* number of cores as seen by the OS: */
 129         u16                     booted_cores;
 130         /* Physical processor id: */
 131         u16                     phys_proc_id;
 132         /* Logical processor id: */
 133         u16                     logical_proc_id;
 134         /* Core id: */
 135         u16                     cpu_core_id;
 136         /* Index into per_cpu list: */
 137         u16                     cpu_index;
 138         u32                     microcode;
 139 };
 140
 141 struct cpuid_regs {
 142         u32 eax, ebx, ecx, edx;
 143 };
 144
 145 enum cpuid_regs_idx {
 146         CPUID_EAX = 0,
 147         CPUID_EBX,
 148         CPUID_ECX,
 149         CPUID_EDX,
 150 };
 151
 152 #define X86_VENDOR_INTEL        0
 153 #define X86_VENDOR_CYRIX        1
 154 #define X86_VENDOR_AMD          2
 155 #define X86_VENDOR_UMC          3
 156 #define X86_VENDOR_CENTAUR      5
 157 #define X86_VENDOR_TRANSMETA    7
 158 #define X86_VENDOR_NSC          8
 159 #define X86_VENDOR_NUM          9
 160
 161 #define X86_VENDOR_UNKNOWN      0xff
 162
 163 /*
 164  * capabilities of CPUs
 165  */
 166 extern struct cpuinfo_x86       boot_cpu_data;
 167 extern struct cpuinfo_x86       new_cpu_data;
 168
 169 extern struct tss_struct        doublefault_tss;
 170 extern __u32                    cpu_caps_cleared[NCAPINTS];
 171 extern __u32                    cpu_caps_set[NCAPINTS];
 172
 173 #ifdef CONFIG_SMP
 174 DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
 175 #define cpu_data(cpu)           per_cpu(cpu_info, cpu)
 176 #else
 177 #define cpu_info                boot_cpu_data
 178 #define cpu_data(cpu)           boot_cpu_data
 179 #endif
 180
 181 extern const struct seq_operations cpuinfo_op;
 182
 183 #define cache_line_size()       (boot_cpu_data.x86_cache_alignment)
 184
 185 extern void cpu_detect(struct cpuinfo_x86 *c);
 186
 187 extern void early_cpu_init(void);
 188 extern void identify_boot_cpu(void);
 189 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
 190 extern void print_cpu_info(struct cpuinfo_x86 *);
 191 void print_cpu_msr(struct cpuinfo_x86 *);
 192 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
 193 extern u32 get_scattered_cpuid_leaf(unsigned int level,
 194                                     unsigned int sub_leaf,
 195                                     enum cpuid_regs_idx reg);
 196 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
 197 extern void init_amd_cacheinfo(struct cpuinfo_x86 *c);
 198
 199 extern void detect_extended_topology(struct cpuinfo_x86 *c);
 200 extern void detect_ht(struct cpuinfo_x86 *c);
 201
 202 #ifdef CONFIG_X86_32
 203 extern int have_cpuid_p(void);
 204 #else
 205 static inline int have_cpuid_p(void)
 206 {
 207         return 1;
 208 }
 209 #endif
 210 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
 211                                 unsigned int *ecx, unsigned int *edx)
 212 {
 213         /* ecx is often an input as well as an output. */
 214         asm volatile("cpuid"
 215             : "=a" (*eax),
 216               "=b" (*ebx),
 217               "=c" (*ecx),
 218               "=d" (*edx)
 219             : "0" (*eax), "2" (*ecx)
 220             : "memory");
 221 }
 222
 223 #define native_cpuid_reg(reg)                                   \
 224 static inline unsigned int native_cpuid_##reg(unsigned int op)  \
 225 {                                                               \
 226         unsigned int eax = op, ebx, ecx = 0, edx;               \
 227                                                                 \
 228         native_cpuid(&eax, &ebx, &ecx, &edx);                   \
 229                                                                 \
 230         return reg;                                             \
 231 }
 232
 233 /*
 234  * Native CPUID functions returning a single datum.
 235  */
 236 native_cpuid_reg(eax)
 237 native_cpuid_reg(ebx)
 238 native_cpuid_reg(ecx)
 239 native_cpuid_reg(edx)
 240
 241 static inline void load_cr3(pgd_t *pgdir)
 242 {
 243         write_cr3(__pa(pgdir));
 244 }
 245
 246 #ifdef CONFIG_X86_32
 247 /* This is the TSS defined by the hardware. */
 248 struct x86_hw_tss {
 249         unsigned short          back_link, __blh;
 250         unsigned long           sp0;
 251         unsigned short          ss0, __ss0h;
 252         unsigned long           sp1;
 253
 254         /*
 255          * We don't use ring 1, so ss1 is a convenient scratch space in
 256          * the same cacheline as sp0.  We use ss1 to cache the value in
 257          * MSR_IA32_SYSENTER_CS.  When we context switch
 258          * MSR_IA32_SYSENTER_CS, we first check if the new value being
 259          * written matches ss1, and, if it's not, then we wrmsr the new
 260          * value and update ss1.
 261          *
 262          * The only reason we context switch MSR_IA32_SYSENTER_CS is
 263          * that we set it to zero in vm86 tasks to avoid corrupting the
 264          * stack if we were to go through the sysenter path from vm86
 265          * mode.
 266          */
 267         unsigned short          ss1;    /* MSR_IA32_SYSENTER_CS */
 268
 269         unsigned short          __ss1h;
 270         unsigned long           sp2;
 271         unsigned short          ss2, __ss2h;
 272         unsigned long           __cr3;
 273         unsigned long           ip;
 274         unsigned long           flags;
 275         unsigned long           ax;
 276         unsigned long           cx;
 277         unsigned long           dx;
 278         unsigned long           bx;
 279         unsigned long           sp;
 280         unsigned long           bp;
 281         unsigned long           si;
 282         unsigned long           di;
 283         unsigned short          es, __esh;
 284         unsigned short          cs, __csh;
 285         unsigned short          ss, __ssh;
 286         unsigned short          ds, __dsh;
 287         unsigned short          fs, __fsh;
 288         unsigned short          gs, __gsh;
 289         unsigned short          ldt, __ldth;
 290         unsigned short          trace;
 291         unsigned short          io_bitmap_base;
 292
 293 } __attribute__((packed));
 294 #else
 295 struct x86_hw_tss {
 296         u32                     reserved1;
 297         u64                     sp0;
 298         u64                     sp1;
 299         u64                     sp2;
 300         u64                     reserved2;
 301         u64                     ist[7];
 302         u32                     reserved3;
 303         u32                     reserved4;
 304         u16                     reserved5;
 305         u16                     io_bitmap_base;
 306
 307 } __attribute__((packed));
 308 #endif
 309
 310 /*
 311  * IO-bitmap sizes:
 312  */
 313 #define IO_BITMAP_BITS                  65536
 314 #define IO_BITMAP_BYTES                 (IO_BITMAP_BITS/8)
 315 #define IO_BITMAP_LONGS                 (IO_BITMAP_BYTES/sizeof(long))
 316 #define IO_BITMAP_OFFSET                offsetof(struct tss_struct, io_bitmap)
 317 #define INVALID_IO_BITMAP_OFFSET        0x8000
 318
 319 struct tss_struct {
 320         /*
 321          * The hardware state:
 322          */
 323         struct x86_hw_tss       x86_tss;
 324
 325         /*
 326          * The extra 1 is there because the CPU will access an
 327          * additional byte beyond the end of the IO permission
 328          * bitmap. The extra byte must be all 1 bits, and must
 329          * be within the limit.
 330          */
 331         unsigned long           io_bitmap[IO_BITMAP_LONGS + 1];
 332
 333 #ifdef CONFIG_X86_32
 334         /*
 335          * Space for the temporary SYSENTER stack.
 336          */
 337         unsigned long           SYSENTER_stack_canary;
 338         unsigned long           SYSENTER_stack[64];
 339 #endif
 340
 341 } ____cacheline_aligned;
 342
 343 DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss);
 344
 345 /*
 346  * sizeof(unsigned long) coming from an extra "long" at the end
 347  * of the iobitmap.
 348  *
 349  * -1? seg base+limit should be pointing to the address of the
 350  * last valid byte
 351  */
 352 #define __KERNEL_TSS_LIMIT      \
 353         (IO_BITMAP_OFFSET + IO_BITMAP_BYTES + sizeof(unsigned long) - 1)
 354
 355 #ifdef CONFIG_X86_32
 356 DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack);
 357 #endif
 358
 359 /*
 360  * Save the original ist values for checking stack pointers during debugging
 361  */
 362 struct orig_ist {
 363         unsigned long           ist[7];
 364 };
 365
 366 #ifdef CONFIG_X86_64
 367 DECLARE_PER_CPU(struct orig_ist, orig_ist);
 368
 369 union irq_stack_union {
 370         char irq_stack[IRQ_STACK_SIZE];
 371         /*
 372          * GCC hardcodes the stack canary as %gs:40.  Since the
 373          * irq_stack is the object at %gs:0, we reserve the bottom
 374          * 48 bytes of the irq stack for the canary.
 375          */
 376         struct {
 377                 char gs_base[40];
 378                 unsigned long stack_canary;
 379         };
 380 };
 381
 382 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union) __visible;
 383 DECLARE_INIT_PER_CPU(irq_stack_union);
 384
 385 DECLARE_PER_CPU(char *, irq_stack_ptr);
 386 DECLARE_PER_CPU(unsigned int, irq_count);
 387 extern asmlinkage void ignore_sysret(void);
 388 #else   /* X86_64 */
 389 #ifdef CONFIG_CC_STACKPROTECTOR
 390 /*
 391  * Make sure stack canary segment base is cached-aligned:
 392  *   "For Intel Atom processors, avoid non zero segment base address
 393  *    that is not aligned to cache line boundary at all cost."
 394  * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
 395  */
 396 struct stack_canary {
 397         char __pad[20];         /* canary at %gs:20 */
 398         unsigned long canary;
 399 };
 400 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
 401 #endif
 402 /*
 403  * per-CPU IRQ handling stacks
 404  */
 405 struct irq_stack {
 406         u32                     stack[THREAD_SIZE/sizeof(u32)];
 407 } __aligned(THREAD_SIZE);
 408
 409 DECLARE_PER_CPU(struct irq_stack *, hardirq_stack);
 410 DECLARE_PER_CPU(struct irq_stack *, softirq_stack);
 411 #endif  /* X86_64 */
 412
 413 extern unsigned int fpu_kernel_xstate_size;
 414 extern unsigned int fpu_user_xstate_size;
 415
 416 struct perf_event;
 417
 418 typedef struct {
 419         unsigned long           seg;
 420 } mm_segment_t;
 421
 422 struct thread_struct {
 423         /* Cached TLS descriptors: */
 424         struct desc_struct      tls_array[GDT_ENTRY_TLS_ENTRIES];
 425         unsigned long           sp0;
 426         unsigned long           sp;
 427 #ifdef CONFIG_X86_32
 428         unsigned long           sysenter_cs;
 429 #else
 430         unsigned short          es;
 431         unsigned short          ds;
 432         unsigned short          fsindex;
 433         unsigned short          gsindex;
 434 #endif
 435
 436         u32                     status;         /* thread synchronous flags */
 437
 438 #ifdef CONFIG_X86_64
 439         unsigned long           fsbase;
 440         unsigned long           gsbase;
 441 #else
 442         /*
 443          * XXX: this could presumably be unsigned short.  Alternatively,
 444          * 32-bit kernels could be taught to use fsindex instead.
 445          */
 446         unsigned long fs;
 447         unsigned long gs;
 448 #endif
 449
 450         /* Save middle states of ptrace breakpoints */
 451         struct perf_event       *ptrace_bps[HBP_NUM];
 452         /* Debug status used for traps, single steps, etc... */
 453         unsigned long           debugreg6;
 454         /* Keep track of the exact dr7 value set by the user */
 455         unsigned long           ptrace_dr7;
 456         /* Fault info: */
 457         unsigned long           cr2;
 458         unsigned long           trap_nr;
 459         unsigned long           error_code;
 460 #ifdef CONFIG_VM86
 461         /* Virtual 86 mode info */
 462         struct vm86             *vm86;
 463 #endif
 464         /* IO permissions: */
 465         unsigned long           *io_bitmap_ptr;
 466         unsigned long           iopl;
 467         /* Max allowed port in the bitmap, in bytes: */
 468         unsigned                io_bitmap_max;
 469
 470         mm_segment_t            addr_limit;
 471
 472         unsigned int            sig_on_uaccess_err:1;
 473         unsigned int            uaccess_err:1;  /* uaccess failed */
 474
 475         /* Floating point and extended processor state */
 476         struct fpu              fpu;
 477         /*
 478          * WARNING: 'fpu' is dynamically-sized.  It *MUST* be at
 479          * the end.
 480          */
 481 };
 482
 483 /*
 484  * Thread-synchronous status.
 485  *
 486  * This is different from the flags in that nobody else
 487  * ever touches our thread-synchronous status, so we don't
 488  * have to worry about atomic accesses.
 489  */
 490 #define TS_COMPAT               0x0002  /* 32bit syscall active (64BIT)*/
 491
 492 /*
 493  * Set IOPL bits in EFLAGS from given mask
 494  */
 495 static inline void native_set_iopl_mask(unsigned mask)
 496 {
 497 #ifdef CONFIG_X86_32
 498         unsigned int reg;
 499
 500         asm volatile ("pushfl;"
 501                       "popl %0;"
 502                       "andl %1, %0;"
 503                       "orl %2, %0;"
 504                       "pushl %0;"
 505                       "popfl"
 506                       : "=&r" (reg)
 507                       : "i" (~X86_EFLAGS_IOPL), "r" (mask));
 508 #endif
 509 }
 510
 511 static inline void
 512 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
 513 {
 514         tss->x86_tss.sp0 = thread->sp0;
 515 #ifdef CONFIG_X86_32
 516         /* Only happens when SEP is enabled, no need to test "SEP"arately: */
 517         if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
 518                 tss->x86_tss.ss1 = thread->sysenter_cs;
 519                 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
 520         }
 521 #endif
 522 }
 523
 524 static inline void native_swapgs(void)
 525 {
 526 #ifdef CONFIG_X86_64
 527         asm volatile("swapgs" ::: "memory");
 528 #endif
 529 }
 530
 531 static inline unsigned long current_top_of_stack(void)
 532 {
 533 #ifdef CONFIG_X86_64
 534         return this_cpu_read_stable(cpu_tss.x86_tss.sp0);
 535 #else
 536         /* sp0 on x86_32 is special in and around vm86 mode. */
 537         return this_cpu_read_stable(cpu_current_top_of_stack);
 538 #endif
 539 }
 540
 541 #ifdef CONFIG_PARAVIRT
 542 #include <asm/paravirt.h>
 543 #else
 544 #define __cpuid                 native_cpuid
 545
 546 static inline void load_sp0(struct tss_struct *tss,
 547                             struct thread_struct *thread)
 548 {
 549         native_load_sp0(tss, thread);
 550 }
 551
 552 #define set_iopl_mask native_set_iopl_mask
 553 #endif /* CONFIG_PARAVIRT */
 554
 555 /* Free all resources held by a thread. */
 556 extern void release_thread(struct task_struct *);
 557
 558 unsigned long get_wchan(struct task_struct *p);
 559
 560 /*
 561  * Generic CPUID function
 562  * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
 563  * resulting in stale register contents being returned.
 564  */
 565 static inline void cpuid(unsigned int op,
 566                          unsigned int *eax, unsigned int *ebx,
 567                          unsigned int *ecx, unsigned int *edx)
 568 {
 569         *eax = op;
 570         *ecx = 0;
 571         __cpuid(eax, ebx, ecx, edx);
 572 }
 573
 574 /* Some CPUID calls want 'count' to be placed in ecx */
 575 static inline void cpuid_count(unsigned int op, int count,
 576                                unsigned int *eax, unsigned int *ebx,
 577                                unsigned int *ecx, unsigned int *edx)
 578 {
 579         *eax = op;
 580         *ecx = count;
 581         __cpuid(eax, ebx, ecx, edx);
 582 }
 583
 584 /*
 585  * CPUID functions returning a single datum
 586  */
 587 static inline unsigned int cpuid_eax(unsigned int op)
 588 {
 589         unsigned int eax, ebx, ecx, edx;
 590
 591         cpuid(op, &eax, &ebx, &ecx, &edx);
 592
 593         return eax;
 594 }
 595
 596 static inline unsigned int cpuid_ebx(unsigned int op)
 597 {
 598         unsigned int eax, ebx, ecx, edx;
 599
 600         cpuid(op, &eax, &ebx, &ecx, &edx);
 601
 602         return ebx;
 603 }
 604
 605 static inline unsigned int cpuid_ecx(unsigned int op)
 606 {
 607         unsigned int eax, ebx, ecx, edx;
 608
 609         cpuid(op, &eax, &ebx, &ecx, &edx);
 610
 611         return ecx;
 612 }
 613
 614 static inline unsigned int cpuid_edx(unsigned int op)
 615 {
 616         unsigned int eax, ebx, ecx, edx;
 617
 618         cpuid(op, &eax, &ebx, &ecx, &edx);
 619
 620         return edx;
 621 }
 622
 623 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
 624 static __always_inline void rep_nop(void)
 625 {
 626         asm volatile("rep; nop" ::: "memory");
 627 }
 628
 629 static __always_inline void cpu_relax(void)
 630 {
 631         rep_nop();
 632 }
 633
 634 /*
 635  * This function forces the icache and prefetched instruction stream to
 636  * catch up with reality in two very specific cases:
 637  *
 638  *  a) Text was modified using one virtual address and is about to be executed
 639  *     from the same physical page at a different virtual address.
 640  *
 641  *  b) Text was modified on a different CPU, may subsequently be
 642  *     executed on this CPU, and you want to make sure the new version
 643  *     gets executed.  This generally means you're calling this in a IPI.
 644  *
 645  * If you're calling this for a different reason, you're probably doing
 646  * it wrong.
 647  */
 648 static inline void sync_core(void)
 649 {
 650         /*
 651          * There are quite a few ways to do this.  IRET-to-self is nice
 652          * because it works on every CPU, at any CPL (so it's compatible
 653          * with paravirtualization), and it never exits to a hypervisor.
 654          * The only down sides are that it's a bit slow (it seems to be
 655          * a bit more than 2x slower than the fastest options) and that
 656          * it unmasks NMIs.  The "push %cs" is needed because, in
 657          * paravirtual environments, __KERNEL_CS may not be a valid CS
 658          * value when we do IRET directly.
 659          *
 660          * In case NMI unmasking or performance ever becomes a problem,
 661          * the next best option appears to be MOV-to-CR2 and an
 662          * unconditional jump.  That sequence also works on all CPUs,
 663          * but it will fault at CPL3 (i.e. Xen PV and lguest).
 664          *
 665          * CPUID is the conventional way, but it's nasty: it doesn't
 666          * exist on some 486-like CPUs, and it usually exits to a
 667          * hypervisor.
 668          *
 669          * Like all of Linux's memory ordering operations, this is a
 670          * compiler barrier as well.
 671          */
 672         register void *__sp asm(_ASM_SP);
 673
 674 #ifdef CONFIG_X86_32
 675         asm volatile (
 676                 "pushfl\n\t"
 677                 "pushl %%cs\n\t"
 678                 "pushl $1f\n\t"
 679                 "iret\n\t"
 680                 "1:"
 681                 : "+r" (__sp) : : "memory");
 682 #else
 683         unsigned int tmp;
 684
 685         asm volatile (
 686                 "mov %%ss, %0\n\t"
 687                 "pushq %q0\n\t"
 688                 "pushq %%rsp\n\t"
 689                 "addq $8, (%%rsp)\n\t"
 690                 "pushfq\n\t"
 691                 "mov %%cs, %0\n\t"
 692                 "pushq %q0\n\t"
 693                 "pushq $1f\n\t"
 694                 "iretq\n\t"
 695                 "1:"
 696                 : "=&r" (tmp), "+r" (__sp) : : "cc", "memory");
 697 #endif
 698 }
 699
 700 extern void select_idle_routine(const struct cpuinfo_x86 *c);
 701 extern void amd_e400_c1e_apic_setup(void);
 702
 703 extern unsigned long            boot_option_idle_override;
 704
 705 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
 706                          IDLE_POLL};
 707
 708 extern void enable_sep_cpu(void);
 709 extern int sysenter_setup(void);
 710
 711 extern void early_trap_init(void);
 712 void early_trap_pf_init(void);
 713
 714 /* Defined in head.S */
 715 extern struct desc_ptr          early_gdt_descr;
 716
 717 extern void cpu_set_gdt(int);
 718 extern void switch_to_new_gdt(int);
 719 extern void load_percpu_segment(int);
 720 extern void cpu_init(void);
 721
 722 static inline unsigned long get_debugctlmsr(void)
 723 {
 724         unsigned long debugctlmsr = 0;
 725
 726 #ifndef CONFIG_X86_DEBUGCTLMSR
 727         if (boot_cpu_data.x86 < 6)
 728                 return 0;
 729 #endif
 730         rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
 731
 732         return debugctlmsr;
 733 }
 734
 735 static inline void update_debugctlmsr(unsigned long debugctlmsr)
 736 {
 737 #ifndef CONFIG_X86_DEBUGCTLMSR
 738         if (boot_cpu_data.x86 < 6)
 739                 return;
 740 #endif
 741         wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
 742 }
 743
 744 extern void set_task_blockstep(struct task_struct *task, bool on);
 745
 746 /* Boot loader type from the setup header: */
 747 extern int                      bootloader_type;
 748 extern int                      bootloader_version;
 749
 750 extern char                     ignore_fpu_irq;
 751
 752 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
 753 #define ARCH_HAS_PREFETCHW
 754 #define ARCH_HAS_SPINLOCK_PREFETCH
 755
 756 #ifdef CONFIG_X86_32
 757 # define BASE_PREFETCH          ""
 758 # define ARCH_HAS_PREFETCH
 759 #else
 760 # define BASE_PREFETCH          "prefetcht0 %P1"
 761 #endif
 762
 763 /*
 764  * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
 765  *
 766  * It's not worth to care about 3dnow prefetches for the K6
 767  * because they are microcoded there and very slow.
 768  */
 769 static inline void prefetch(const void *x)
 770 {
 771         alternative_input(BASE_PREFETCH, "prefetchnta %P1",
 772                           X86_FEATURE_XMM,
 773                           "m" (*(const char *)x));
 774 }
 775
 776 /*
 777  * 3dnow prefetch to get an exclusive cache line.
 778  * Useful for spinlocks to avoid one state transition in the
 779  * cache coherency protocol:
 780  */
 781 static inline void prefetchw(const void *x)
 782 {
 783         alternative_input(BASE_PREFETCH, "prefetchw %P1",
 784                           X86_FEATURE_3DNOWPREFETCH,
 785                           "m" (*(const char *)x));
 786 }
 787
 788 static inline void spin_lock_prefetch(const void *x)
 789 {
 790         prefetchw(x);
 791 }
 792
 793 #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \
 794                            TOP_OF_KERNEL_STACK_PADDING)
 795
 796 #ifdef CONFIG_X86_32
 797 /*
 798  * User space process size: 3GB (default).
 799  */
 800 #define TASK_SIZE               PAGE_OFFSET
 801 #define TASK_SIZE_MAX           TASK_SIZE
 802 #define STACK_TOP               TASK_SIZE
 803 #define STACK_TOP_MAX           STACK_TOP
 804
 805 #define INIT_THREAD  {                                                    \
 806         .sp0                    = TOP_OF_INIT_STACK,                      \
 807         .sysenter_cs            = __KERNEL_CS,                            \
 808         .io_bitmap_ptr          = NULL,                                   \
 809         .addr_limit             = KERNEL_DS,                              \
 810 }
 811
 812 /*
 813  * TOP_OF_KERNEL_STACK_PADDING reserves 8 bytes on top of the ring0 stack.
 814  * This is necessary to guarantee that the entire "struct pt_regs"
 815  * is accessible even if the CPU haven't stored the SS/ESP registers
 816  * on the stack (interrupt gate does not save these registers
 817  * when switching to the same priv ring).
 818  * Therefore beware: accessing the ss/esp fields of the
 819  * "struct pt_regs" is possible, but they may contain the
 820  * completely wrong values.
 821  */
 822 #define task_pt_regs(task) \
 823 ({                                                                      \
 824         unsigned long __ptr = (unsigned long)task_stack_page(task);     \
 825         __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING;             \
 826         ((struct pt_regs *)__ptr) - 1;                                  \
 827 })
 828
 829 #define KSTK_ESP(task)          (task_pt_regs(task)->sp)
 830
 831 #else
 832 /*
 833  * User space process size. 47bits minus one guard page.  The guard
 834  * page is necessary on Intel CPUs: if a SYSCALL instruction is at
 835  * the highest possible canonical userspace address, then that
 836  * syscall will enter the kernel with a non-canonical return
 837  * address, and SYSRET will explode dangerously.  We avoid this
 838  * particular problem by preventing anything from being mapped
 839  * at the maximum canonical address.
 840  */
 841 #define TASK_SIZE_MAX   ((1UL << 47) - PAGE_SIZE)
 842
 843 /* This decides where the kernel will search for a free chunk of vm
 844  * space during mmap's.
 845  */
 846 #define IA32_PAGE_OFFSET        ((current->personality & ADDR_LIMIT_3GB) ? \
 847                                         0xc0000000 : 0xFFFFe000)
 848
 849 #define TASK_SIZE               (test_thread_flag(TIF_ADDR32) ? \
 850                                         IA32_PAGE_OFFSET : TASK_SIZE_MAX)
 851 #define TASK_SIZE_OF(child)     ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \
 852                                         IA32_PAGE_OFFSET : TASK_SIZE_MAX)
 853
 854 #define STACK_TOP               TASK_SIZE
 855 #define STACK_TOP_MAX           TASK_SIZE_MAX
 856
 857 #define INIT_THREAD  {                                          \
 858         .sp0                    = TOP_OF_INIT_STACK,            \
 859         .addr_limit             = KERNEL_DS,                    \
 860 }
 861
 862 #define task_pt_regs(tsk)       ((struct pt_regs *)(tsk)->thread.sp0 - 1)
 863 extern unsigned long KSTK_ESP(struct task_struct *task);
 864
 865 #endif /* CONFIG_X86_64 */
 866
 867 extern unsigned long thread_saved_pc(struct task_struct *tsk);
 868
 869 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
 870                                                unsigned long new_sp);
 871
 872 /*
 873  * This decides where the kernel will search for a free chunk of vm
 874  * space during mmap's.
 875  */
 876 #define TASK_UNMAPPED_BASE      (PAGE_ALIGN(TASK_SIZE / 3))
 877
 878 #define KSTK_EIP(task)          (task_pt_regs(task)->ip)
 879
 880 /* Get/set a process' ability to use the timestamp counter instruction */
 881 #define GET_TSC_CTL(adr)        get_tsc_mode((adr))
 882 #define SET_TSC_CTL(val)        set_tsc_mode((val))
 883
 884 extern int get_tsc_mode(unsigned long adr);
 885 extern int set_tsc_mode(unsigned int val);
 886
 887 /* Register/unregister a process' MPX related resource */
 888 #define MPX_ENABLE_MANAGEMENT() mpx_enable_management()
 889 #define MPX_DISABLE_MANAGEMENT()        mpx_disable_management()
 890
 891 #ifdef CONFIG_X86_INTEL_MPX
 892 extern int mpx_enable_management(void);
 893 extern int mpx_disable_management(void);
 894 #else
 895 static inline int mpx_enable_management(void)
 896 {
 897         return -EINVAL;
 898 }
 899 static inline int mpx_disable_management(void)
 900 {
 901         return -EINVAL;
 902 }
 903 #endif /* CONFIG_X86_INTEL_MPX */
 904
 905 extern u16 amd_get_nb_id(int cpu);
 906 extern u32 amd_get_nodes_per_socket(void);
 907
 908 static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves)
 909 {
 910         uint32_t base, eax, signature[3];
 911
 912         for (base = 0x40000000; base < 0x40010000; base += 0x100) {
 913                 cpuid(base, &eax, &signature[0], &signature[1], &signature[2]);
 914
 915                 if (!memcmp(sig, signature, 12) &&
 916                     (leaves == 0 || ((eax - base) >= leaves)))
 917                         return base;
 918         }
 919
 920         return 0;
 921 }
 922
 923 extern unsigned long arch_align_stack(unsigned long sp);
 924 extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
 925
 926 void default_idle(void);
 927 #ifdef  CONFIG_XEN
 928 bool xen_set_default_idle(void);
 929 #else
 930 #define xen_set_default_idle 0
 931 #endif
 932
 933 void stop_this_cpu(void *dummy);
 934 void df_debug(struct pt_regs *regs, long error_code);
 935 #endif /* _ASM_X86_PROCESSOR_H */